Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	402784877	1925974	0	0
intr_enable_rd_A	402784877	2585	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402784877	1925974	0	0
T7	379009	155304	0	0
T8	0	132739	0	0
T9	0	90174	0	0
T10	0	80856	0	0
T18	850	0	0	0
T24	0	60754	0	0
T28	6443	0	0	0
T33	281175	0	0	0
T34	303421	0	0	0
T35	4799	0	0	0
T43	0	194705	0	0
T62	0	212708	0	0
T63	0	118240	0	0
T64	0	155678	0	0
T65	0	8452	0	0
T66	38632	0	0	0
T67	3777	0	0	0
T68	160112	0	0	0
T69	7306	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402784877	2585	0	0
T16	1289	0	0	0
T17	1017	0	0	0
T27	0	7	0	0
T48	0	32	0	0
T49	345305	10	0	0
T52	28463	0	0	0
T70	0	28	0	0
T71	0	25	0	0
T72	0	10	0	0
T73	0	28	0	0
T74	0	6	0	0
T75	0	8	0	0
T76	0	31	0	0
T77	119773	0	0	0
T78	4267	0	0	0
T79	5606	0	0	0
T80	14642	0	0	0
T81	154637	0	0	0
T82	233062	0	0	0