Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30985780 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 33034893 1 T1 2574 T2 13943 T3 7643



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 25682168 1 T1 2228 T2 13982 T3 1502
values[0x0] 17862109 1 T1 1001 T2 7562 T3 3631
values[0x1] 20476396 1 T1 1181 T2 8972 T3 3639



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 22774744 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 41245929 1 T1 3044 T2 17874 T3 8066



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 546810 1 T1 18 T2 89 T3 34
valid_sources[0x01] 245265 1 T1 22 T2 122 T3 34
valid_sources[0x02] 208287 1 T1 19 T2 114 T3 33
valid_sources[0x03] 206089 1 T1 19 T2 121 T3 37
valid_sources[0x04] 624722 1 T1 14 T2 110 T3 42
valid_sources[0x05] 199000 1 T1 20 T2 139 T3 30
valid_sources[0x06] 185401 1 T1 19 T2 95 T3 40
valid_sources[0x07] 225185 1 T1 20 T2 126 T3 29
valid_sources[0x08] 244173 1 T1 11 T2 97 T3 25
valid_sources[0x09] 186685 1 T1 16 T2 127 T3 32
valid_sources[0x0a] 208224 1 T1 10 T2 112 T3 42
valid_sources[0x0b] 203604 1 T1 15 T2 144 T3 33
valid_sources[0x0c] 208123 1 T1 14 T2 107 T3 44
valid_sources[0x0d] 234282 1 T1 21 T2 152 T3 34
valid_sources[0x0e] 230216 1 T1 21 T2 106 T3 30
valid_sources[0x0f] 198324 1 T1 20 T2 124 T3 39
valid_sources[0x10] 218008 1 T1 24 T2 115 T3 34
valid_sources[0x11] 214530 1 T1 26 T2 144 T3 28
valid_sources[0x12] 208564 1 T1 17 T2 94 T3 38
valid_sources[0x13] 213284 1 T1 16 T2 105 T3 46
valid_sources[0x14] 212864 1 T1 13 T2 137 T3 47
valid_sources[0x15] 203237 1 T1 19 T2 113 T3 36
valid_sources[0x16] 193782 1 T1 17 T2 129 T3 32
valid_sources[0x17] 203289 1 T1 16 T2 113 T3 32
valid_sources[0x18] 206089 1 T1 12 T2 129 T3 35
valid_sources[0x19] 192433 1 T1 12 T2 124 T3 47
valid_sources[0x1a] 204170 1 T1 16 T2 113 T3 48
valid_sources[0x1b] 195300 1 T1 19 T2 121 T3 29
valid_sources[0x1c] 567628 1 T1 19 T2 136 T3 35
valid_sources[0x1d] 203894 1 T1 15 T2 100 T3 20
valid_sources[0x1e] 214437 1 T1 14 T2 117 T3 30
valid_sources[0x1f] 207465 1 T1 14 T2 143 T3 39
valid_sources[0x20] 993936 1 T1 17 T2 130 T3 45
valid_sources[0x21] 210354 1 T1 21 T2 122 T3 32
valid_sources[0x22] 205007 1 T1 15 T2 111 T3 22
valid_sources[0x23] 260582 1 T1 14 T2 123 T3 37
valid_sources[0x24] 199581 1 T1 23 T2 124 T3 40
valid_sources[0x25] 184764 1 T1 18 T2 131 T3 20
valid_sources[0x26] 197498 1 T1 19 T2 103 T3 33
valid_sources[0x27] 195434 1 T1 15 T2 126 T3 31
valid_sources[0x28] 233582 1 T1 15 T2 132 T3 41
valid_sources[0x29] 558061 1 T1 17 T2 136 T3 35
valid_sources[0x2a] 195780 1 T1 18 T2 104 T3 46
valid_sources[0x2b] 203220 1 T1 13 T2 123 T3 30
valid_sources[0x2c] 614746 1 T1 20 T2 128 T3 31
valid_sources[0x2d] 191410 1 T1 13 T2 126 T3 30
valid_sources[0x2e] 219858 1 T1 14 T2 111 T3 33
valid_sources[0x2f] 202080 1 T1 15 T2 144 T3 36
valid_sources[0x30] 187755 1 T1 19 T2 117 T3 21
valid_sources[0x31] 201467 1 T1 23 T2 104 T3 33
valid_sources[0x32] 205370 1 T1 24 T2 117 T3 35
valid_sources[0x33] 197954 1 T1 18 T2 117 T3 30
valid_sources[0x34] 207764 1 T1 20 T2 133 T3 33
valid_sources[0x35] 213429 1 T1 16 T2 132 T3 32
valid_sources[0x36] 212433 1 T1 19 T2 108 T3 26
valid_sources[0x37] 187408 1 T1 16 T2 143 T3 47
valid_sources[0x38] 208442 1 T1 13 T2 108 T3 37
valid_sources[0x39] 242678 1 T1 18 T2 123 T3 31
valid_sources[0x3a] 209765 1 T1 11 T2 108 T3 43
valid_sources[0x3b] 195568 1 T1 20 T2 83 T3 25
valid_sources[0x3c] 197005 1 T1 21 T2 150 T3 32
valid_sources[0x3d] 198553 1 T1 14 T2 129 T3 32
valid_sources[0x3e] 196498 1 T1 29 T2 118 T3 37
valid_sources[0x3f] 581154 1 T1 19 T2 112 T3 38
valid_sources[0x40] 188492 1 T1 23 T2 138 T3 31
valid_sources[0x41] 199617 1 T1 20 T2 119 T3 31
valid_sources[0x42] 206037 1 T1 14 T2 118 T3 45
valid_sources[0x43] 205650 1 T1 25 T2 132 T3 39
valid_sources[0x44] 219046 1 T1 15 T2 116 T3 25
valid_sources[0x45] 214244 1 T1 19 T2 110 T3 46
valid_sources[0x46] 197702 1 T1 17 T2 137 T3 33
valid_sources[0x47] 540237 1 T1 18 T2 112 T3 26
valid_sources[0x48] 196678 1 T1 16 T2 95 T3 27
valid_sources[0x49] 605251 1 T1 18 T2 114 T3 38
valid_sources[0x4a] 628307 1 T1 24 T2 141 T3 42
valid_sources[0x4b] 193705 1 T1 17 T2 114 T3 26
valid_sources[0x4c] 191504 1 T1 22 T2 111 T3 30
valid_sources[0x4d] 192171 1 T1 14 T2 99 T3 30
valid_sources[0x4e] 195864 1 T1 21 T2 105 T3 28
valid_sources[0x4f] 189244 1 T1 16 T2 123 T3 28
valid_sources[0x50] 190637 1 T1 17 T2 119 T3 33
valid_sources[0x51] 199624 1 T1 17 T2 113 T3 36
valid_sources[0x52] 188645 1 T1 11 T2 152 T3 36
valid_sources[0x53] 213957 1 T1 16 T2 137 T3 27
valid_sources[0x54] 217613 1 T1 22 T2 130 T3 40
valid_sources[0x55] 182497 1 T1 18 T2 128 T3 38
valid_sources[0x56] 273803 1 T1 16 T2 124 T3 22
valid_sources[0x57] 198522 1 T1 21 T2 118 T3 29
valid_sources[0x58] 206435 1 T1 15 T2 104 T3 40
valid_sources[0x59] 198534 1 T1 11 T2 119 T3 40
valid_sources[0x5a] 187524 1 T1 18 T2 118 T3 38
valid_sources[0x5b] 211159 1 T1 10 T2 111 T3 38
valid_sources[0x5c] 188077 1 T1 27 T2 126 T3 29
valid_sources[0x5d] 568059 1 T1 21 T2 109 T3 32
valid_sources[0x5e] 210429 1 T1 11 T2 116 T3 33
valid_sources[0x5f] 586399 1 T1 18 T2 121 T3 37
valid_sources[0x60] 204968 1 T1 13 T2 113 T3 36
valid_sources[0x61] 199005 1 T1 15 T2 110 T3 37
valid_sources[0x62] 242336 1 T1 18 T2 141 T3 29
valid_sources[0x63] 216935 1 T1 18 T2 125 T3 37
valid_sources[0x64] 219069 1 T1 10 T2 114 T3 35
valid_sources[0x65] 208722 1 T1 17 T2 128 T3 36
valid_sources[0x66] 226161 1 T1 10 T2 122 T3 26
valid_sources[0x67] 205343 1 T1 12 T2 109 T3 31
valid_sources[0x68] 196939 1 T1 23 T2 107 T3 39
valid_sources[0x69] 182587 1 T1 18 T2 92 T3 35
valid_sources[0x6a] 187342 1 T1 21 T2 113 T3 27
valid_sources[0x6b] 202213 1 T1 17 T2 132 T3 46
valid_sources[0x6c] 188877 1 T1 21 T2 111 T3 41
valid_sources[0x6d] 193880 1 T1 12 T2 124 T3 49
valid_sources[0x6e] 226125 1 T1 17 T2 120 T3 36
valid_sources[0x6f] 195666 1 T1 16 T2 145 T3 40
valid_sources[0x70] 200957 1 T1 20 T2 95 T3 28
valid_sources[0x71] 206448 1 T1 15 T2 125 T3 28
valid_sources[0x72] 188568 1 T1 13 T2 122 T3 33
valid_sources[0x73] 582462 1 T1 7 T2 159 T3 37
valid_sources[0x74] 200363 1 T1 20 T2 134 T3 34
valid_sources[0x75] 190409 1 T1 11 T2 133 T3 25
valid_sources[0x76] 673594 1 T1 19 T2 112 T3 43
valid_sources[0x77] 184490 1 T1 15 T2 126 T3 40
valid_sources[0x78] 200049 1 T1 23 T2 129 T3 29
valid_sources[0x79] 611774 1 T1 21 T2 125 T3 37
valid_sources[0x7a] 214350 1 T1 15 T2 113 T3 29
valid_sources[0x7b] 222035 1 T1 25 T2 106 T3 26
valid_sources[0x7c] 239392 1 T1 23 T2 105 T3 41
valid_sources[0x7d] 247281 1 T1 18 T2 111 T3 25
valid_sources[0x7e] 194279 1 T1 21 T2 114 T3 29
valid_sources[0x7f] 205024 1 T1 9 T2 120 T3 22
valid_sources[0x80] 199255 1 T1 17 T2 108 T3 26



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 12346922 1 T1 944 T2 7108 T3 454
values[0x0] all_enables biggest_size 10879879 1 T1 776 T2 3773 T3 3593
values[0x1] all_enables biggest_size 9808092 1 T1 854 T2 3062 T3 3596

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%