Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

34189844

1

T1

1836

T2

16573

T3

1129

full_word

33244157

1

T1

2574

T2

13943

T3

7643

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67433571	1			T1	4410		T2	30516		T3	8772
auto[TlIntgErrCmd]	135	1			T66	6		T67	6		T68	2
auto[TlIntgErrData]	149	1			T66	9		T67	6		T68	4
auto[TlIntgErrBoth]	146	1			T66	5		T67	8		T68	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26778895

1

T1

2228

T2

13982

T3

1502

auto[1]

40655106

1

T1

2182

T2

16534

T3

7270

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14348242	1			T1	1284		T2	6874		T3	1048
auto[TlIntgErrNone]	partial	auto[1]	19841217	1			T1	552		T2	9699		T3	81
auto[TlIntgErrNone]	full_word	auto[0]	12430455	1			T1	944		T2	7108		T3	454
auto[TlIntgErrNone]	full_word	auto[1]	20813657	1			T1	1630		T2	6835		T3	7189
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T66	3		T67	2		T68	1
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T66	2		T67	3		T68	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T124	1		T126	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T66	1		T67	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T66	3		T67	4		T68	3
auto[TlIntgErrData]	partial	auto[1]	72	1			T66	3		T67	2		T68	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T66	1		T131	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T66	2		T131	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T66	4		T67	5		T68	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T66	1		T67	3		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T125	1		T126	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T124	1		T133	1		T134	2