Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34415467 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 36714755 1 T2 182502 T3 181895 T4 163



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 28439189 1 T1 1 T2 143493 T3 141727
values[0x0] 19883434 1 T1 2 T2 101309 T3 101706
values[0x1] 22807599 1 T1 8 T2 114112 T3 114407



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 25295816 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 45834406 1 T1 3 T2 226114 T3 225430



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 220905 1 T2 1527 T5 11 T29 37
valid_sources[0x01] 223377 1 T2 1429 T4 1 T5 25
valid_sources[0x02] 223696 1 T2 1305 T5 20 T29 56
valid_sources[0x03] 228434 1 T2 1401 T5 14 T6 4
valid_sources[0x04] 241508 1 T2 1300 T4 2 T5 15
valid_sources[0x05] 281617 1 T2 1363 T5 14 T6 5
valid_sources[0x06] 224918 1 T2 1442 T5 14 T6 8
valid_sources[0x07] 240585 1 T2 1351 T5 15 T29 45
valid_sources[0x08] 217732 1 T2 1301 T5 10 T21 2
valid_sources[0x09] 218544 1 T2 1529 T4 5 T5 13
valid_sources[0x0a] 233349 1 T2 1430 T5 18 T21 43
valid_sources[0x0b] 217195 1 T2 1332 T5 12 T21 1
valid_sources[0x0c] 237152 1 T2 1439 T5 9 T6 21
valid_sources[0x0d] 244397 1 T2 1301 T5 31 T21 1
valid_sources[0x0e] 244667 1 T2 1347 T5 10 T21 24
valid_sources[0x0f] 244889 1 T2 1340 T5 10 T21 2
valid_sources[0x10] 229009 1 T2 1393 T4 4 T5 16
valid_sources[0x11] 228845 1 T2 1449 T4 3 T5 12
valid_sources[0x12] 253476 1 T2 1426 T4 2 T5 20
valid_sources[0x13] 616238 1 T2 1376 T4 3 T5 19
valid_sources[0x14] 228577 1 T2 1434 T4 1 T5 12
valid_sources[0x15] 224899 1 T2 1358 T5 9 T6 22
valid_sources[0x16] 653912 1 T2 1503 T5 19 T6 1
valid_sources[0x17] 222081 1 T2 1261 T5 29 T28 5
valid_sources[0x18] 239266 1 T2 1334 T5 9 T6 2
valid_sources[0x19] 220573 1 T1 1 T2 1442 T5 8
valid_sources[0x1a] 234468 1 T2 1404 T5 22 T21 5
valid_sources[0x1b] 239420 1 T2 1386 T5 18 T21 31
valid_sources[0x1c] 221618 1 T2 1386 T5 11 T21 6
valid_sources[0x1d] 220263 1 T2 1449 T5 5 T28 273
valid_sources[0x1e] 253099 1 T2 1322 T5 19 T6 2
valid_sources[0x1f] 261110 1 T2 1340 T5 6 T21 12
valid_sources[0x20] 217239 1 T2 1475 T5 17 T21 31
valid_sources[0x21] 240618 1 T2 1545 T5 6 T21 5
valid_sources[0x22] 249360 1 T2 1420 T4 3 T5 17
valid_sources[0x23] 232683 1 T2 1381 T5 4 T21 41
valid_sources[0x24] 253821 1 T2 1414 T4 1 T5 16
valid_sources[0x25] 222088 1 T2 1353 T5 14 T6 3
valid_sources[0x26] 585037 1 T2 1474 T4 1 T5 6
valid_sources[0x27] 220595 1 T2 1472 T5 14 T29 49
valid_sources[0x28] 221737 1 T2 1469 T4 4 T5 11
valid_sources[0x29] 246834 1 T2 1433 T5 23 T21 1
valid_sources[0x2a] 226893 1 T2 1407 T5 19 T21 3
valid_sources[0x2b] 224254 1 T2 1403 T5 10 T21 19
valid_sources[0x2c] 243136 1 T2 1340 T4 2 T5 14
valid_sources[0x2d] 230749 1 T2 1395 T4 1 T5 4
valid_sources[0x2e] 226290 1 T2 1367 T5 18 T6 5
valid_sources[0x2f] 227598 1 T1 1 T2 1431 T4 1
valid_sources[0x30] 236051 1 T2 1510 T4 1 T5 13
valid_sources[0x31] 220356 1 T2 1377 T5 5 T6 28
valid_sources[0x32] 226828 1 T2 1413 T5 12 T21 10
valid_sources[0x33] 273258 1 T2 1341 T5 18 T29 34
valid_sources[0x34] 244831 1 T2 1431 T5 24 T21 38
valid_sources[0x35] 231654 1 T2 1331 T5 14 T22 1
valid_sources[0x36] 242001 1 T2 1309 T4 1 T5 15
valid_sources[0x37] 617963 1 T2 1266 T5 11 T21 507
valid_sources[0x38] 249100 1 T2 1418 T4 2 T5 16
valid_sources[0x39] 232211 1 T2 1413 T5 11 T28 5
valid_sources[0x3a] 218031 1 T2 1533 T5 7 T21 5
valid_sources[0x3b] 263728 1 T2 1322 T4 7 T5 18
valid_sources[0x3c] 225405 1 T2 1436 T5 7 T29 43
valid_sources[0x3d] 218536 1 T2 1424 T5 19 T6 12
valid_sources[0x3e] 232844 1 T2 1413 T4 9 T5 19
valid_sources[0x3f] 227567 1 T2 1468 T5 12 T21 1
valid_sources[0x40] 224607 1 T2 1497 T5 20 T21 3
valid_sources[0x41] 221762 1 T1 1 T2 1346 T4 3
valid_sources[0x42] 626299 1 T2 1415 T5 8 T21 7
valid_sources[0x43] 608382 1 T2 1402 T3 357840 T4 1
valid_sources[0x44] 226975 1 T2 1340 T4 1 T5 27
valid_sources[0x45] 244577 1 T2 1380 T5 18 T6 12
valid_sources[0x46] 220380 1 T2 1402 T4 3 T5 12
valid_sources[0x47] 229234 1 T2 1347 T4 3 T5 17
valid_sources[0x48] 231040 1 T2 1404 T4 2 T5 8
valid_sources[0x49] 235679 1 T2 1319 T4 1 T5 6
valid_sources[0x4a] 219544 1 T2 1443 T5 11 T6 10
valid_sources[0x4b] 224422 1 T2 1434 T4 4 T5 22
valid_sources[0x4c] 242193 1 T2 1468 T5 9 T21 23
valid_sources[0x4d] 221104 1 T2 1434 T4 2 T5 20
valid_sources[0x4e] 219919 1 T2 1398 T5 9 T29 48
valid_sources[0x4f] 224679 1 T2 1500 T4 3 T5 12
valid_sources[0x50] 223245 1 T2 1475 T5 11 T21 6
valid_sources[0x51] 218484 1 T2 1245 T5 18 T21 1
valid_sources[0x52] 235203 1 T2 1318 T5 22 T21 13
valid_sources[0x53] 225548 1 T1 3 T2 1385 T4 4
valid_sources[0x54] 224462 1 T2 1417 T5 10 T21 7
valid_sources[0x55] 217473 1 T2 1363 T5 21 T21 45
valid_sources[0x56] 289736 1 T2 1337 T5 10 T6 6
valid_sources[0x57] 240480 1 T2 1538 T5 14 T6 9
valid_sources[0x58] 238949 1 T2 1352 T5 15 T21 10
valid_sources[0x59] 226199 1 T2 1371 T5 25 T21 3
valid_sources[0x5a] 222026 1 T2 1325 T5 13 T6 7
valid_sources[0x5b] 233720 1 T2 1457 T5 14 T21 1
valid_sources[0x5c] 266561 1 T2 1431 T4 1 T5 20
valid_sources[0x5d] 223188 1 T2 1457 T5 11 T6 2
valid_sources[0x5e] 226226 1 T2 1323 T5 15 T21 1
valid_sources[0x5f] 1021265 1 T2 1347 T4 1 T5 14
valid_sources[0x60] 573857 1 T2 1408 T5 17 T6 9
valid_sources[0x61] 248225 1 T2 1429 T5 19 T21 5
valid_sources[0x62] 252385 1 T2 1336 T5 23 T6 13
valid_sources[0x63] 230914 1 T2 1410 T4 2 T5 16
valid_sources[0x64] 220312 1 T2 1481 T5 17 T6 27
valid_sources[0x65] 224394 1 T2 1490 T5 17 T6 20
valid_sources[0x66] 231861 1 T2 1464 T4 3 T5 12
valid_sources[0x67] 226403 1 T2 1392 T5 19 T6 3
valid_sources[0x68] 223947 1 T2 1472 T5 8 T6 1
valid_sources[0x69] 586638 1 T2 1411 T4 1 T5 19
valid_sources[0x6a] 218878 1 T2 1413 T5 13 T21 21
valid_sources[0x6b] 227166 1 T2 1380 T5 28 T21 5
valid_sources[0x6c] 224164 1 T2 1408 T4 3 T5 9
valid_sources[0x6d] 248226 1 T2 1404 T5 18 T21 13
valid_sources[0x6e] 227301 1 T2 1415 T5 12 T21 1
valid_sources[0x6f] 221795 1 T2 1379 T5 23 T6 10
valid_sources[0x70] 228190 1 T2 1414 T5 10 T6 10
valid_sources[0x71] 226472 1 T2 1403 T4 5 T5 15
valid_sources[0x72] 229024 1 T2 1479 T5 22 T6 4
valid_sources[0x73] 953195 1 T2 1305 T4 7 T5 11
valid_sources[0x74] 266082 1 T2 1346 T5 11 T6 10
valid_sources[0x75] 246768 1 T2 1446 T4 3 T5 14
valid_sources[0x76] 224228 1 T2 1397 T5 21 T21 27
valid_sources[0x77] 221857 1 T2 1414 T4 2 T5 16
valid_sources[0x78] 660453 1 T2 1398 T5 13 T21 23
valid_sources[0x79] 224762 1 T2 1314 T5 9 T6 12
valid_sources[0x7a] 227023 1 T2 1319 T4 1 T5 14
valid_sources[0x7b] 219899 1 T2 1365 T4 3 T5 11
valid_sources[0x7c] 232217 1 T2 1435 T5 10 T6 11
valid_sources[0x7d] 227431 1 T2 1345 T4 1 T5 17
valid_sources[0x7e] 234523 1 T2 1476 T5 22 T21 1
valid_sources[0x7f] 227821 1 T2 1538 T5 19 T21 7
valid_sources[0x80] 261275 1 T2 1555 T5 11 T21 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 13698116 1 T2 71809 T3 71190 T4 70
values[0x0] all_enables biggest_size 12102943 1 T2 58840 T3 59070 T4 53
values[0x1] all_enables biggest_size 10913696 1 T2 51853 T3 51635 T4 40

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%