Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38350505

1

T1

11

T2

176412

T3

175945

full_word

36972703

1

T2

182502

T3

181895

T4

163

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75322788	1			T1	11		T2	358914		T3	357840
auto[TlIntgErrCmd]	132	1			T62	3		T63	6		T64	4
auto[TlIntgErrData]	152	1			T62	4		T63	11		T64	2
auto[TlIntgErrBoth]	136	1			T62	3		T63	13		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29779873

1

T1

1

T2

143493

T3

141727

auto[1]

45543335

1

T1

10

T2

215421

T3

216113

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15979156	1			T1	1		T2	71684		T3	70537
auto[TlIntgErrNone]	partial	auto[1]	22370970	1			T1	10		T2	104728		T3	105408
auto[TlIntgErrNone]	full_word	auto[0]	13800526	1			T2	71809		T3	71190		T4	70
auto[TlIntgErrNone]	full_word	auto[1]	23172136	1			T2	110693		T3	110705		T4	93
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T62	2		T63	2		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T63	4		T64	2		T122	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T62	1		T126	1		T127	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T122	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T62	3		T63	5		T122	8
auto[TlIntgErrData]	partial	auto[1]	64	1			T63	4		T64	2		T122	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T62	1		T63	2		T130	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T124	1		T131	2		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T63	5		T64	1		T122	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T62	3		T63	6		T64	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T63	1		T124	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T63	1		T122	4		T126	1