Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	364193187	2227144	0	0
intr_enable_rd_A	364193187	3247	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364193187	2227144	0	0
T7	310083	14004	0	0
T8	171283	77816	0	0
T9	0	268922	0	0
T12	0	84064	0	0
T47	0	61086	0	0
T67	0	205713	0	0
T68	0	120839	0	0
T69	0	14484	0	0
T70	0	343000	0	0
T71	0	49338	0	0
T72	264615	0	0	0
T73	1407	0	0	0
T74	401379	0	0	0
T75	724714	0	0	0
T76	2629	0	0	0
T77	6479	0	0	0
T78	460988	0	0	0
T79	39747	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364193187	3247	0	0
T9	0	217	0	0
T17	493709	72	0	0
T55	33923	0	0	0
T56	41510	0	0	0
T57	125300	0	0	0
T58	263535	0	0	0
T68	0	70	0	0
T80	0	22	0	0
T81	0	10	0	0
T82	0	31	0	0
T83	0	34	0	0
T84	0	17	0	0
T85	0	28	0	0
T86	0	23	0	0
T87	13359	0	0	0
T88	739448	0	0	0
T89	477194	0	0	0
T90	6761	0	0	0
T91	46435	0	0	0