Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

36257121

1

T1

1325

T2

9

T3

18671

full_word

36333332

1

T1

7390

T2

4

T3

15683

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	72590003	1			T1	8715		T2	13		T3	34354
auto[TlIntgErrCmd]	125	1			T64	4		T65	3		T66	7
auto[TlIntgErrData]	157	1			T64	11		T65	3		T66	5
auto[TlIntgErrBoth]	168	1			T64	15		T65	4		T66	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28809922

1

T1

1742

T2

1

T3

13800

auto[1]

43780531

1

T1

6973

T2

12

T3

20554

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15148801	1			T1	1143		T3	6796		T4	10356
auto[TlIntgErrNone]	partial	auto[1]	21107910	1			T1	182		T2	9		T3	11875
auto[TlIntgErrNone]	full_word	auto[0]	13660916	1			T1	599		T2	1		T3	7004
auto[TlIntgErrNone]	full_word	auto[1]	22672376	1			T1	6791		T2	3		T3	8679
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T64	3		T65	2		T66	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T64	1		T65	1		T66	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T66	1		T103	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T105	2		T106	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T64	3		T66	3		T98	5
auto[TlIntgErrData]	partial	auto[1]	71	1			T64	4		T65	2		T66	2
auto[TlIntgErrData]	full_word	auto[0]	11	1			T64	3		T65	1		T98	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T64	1		T98	1		T107	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T64	4		T65	2		T66	3
auto[TlIntgErrBoth]	partial	auto[1]	90	1			T64	7		T65	1		T66	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T64	3		T65	1		T100	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T64	1		T98	2		T108	2