Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	387528230	1213168	0	0
intr_enable_rd_A	387528230	2245	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	1213168	0	0
T9	202494	63461	0	0
T10	0	82837	0	0
T11	0	32113	0	0
T12	0	107732	0	0
T15	139295	0	0	0
T17	228113	0	0	0
T24	372084	0	0	0
T25	262365	0	0	0
T27	126330	0	0	0
T51	0	101070	0	0
T52	0	180377	0	0
T70	0	203448	0	0
T71	0	38679	0	0
T72	0	112295	0	0
T73	0	11283	0	0
T74	63522	0	0	0
T75	234442	0	0	0
T76	3966	0	0	0
T77	7502	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	2245	0	0
T5	778696	16	0	0
T6	153766	0	0	0
T7	2474	0	0	0
T8	187234	0	0	0
T9	202494	0	0	0
T18	387090	0	0	0
T22	1531	0	0	0
T25	262365	0	0	0
T27	126330	0	0	0
T31	0	23	0	0
T46	0	36	0	0
T63	0	34	0	0
T74	63522	0	0	0
T78	0	11	0	0
T79	0	59	0	0
T80	0	32	0	0
T81	0	19	0	0
T82	0	7	0	0
T83	0	17	0	0