Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.71	96.67	54.17			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter.u_rspfifo	91.87	92.86	88.89			85.71	100.00
tb.dut.u_tlul_adapter.u_sramreqfifo	93.91	92.31	83.33			100.00	100.00
tb.dut.u_msg_fifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	92.86	88.89			85.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.31	87.18	68.97			61.11	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	98.44	100.00			100.00	85.71	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

---

Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.91	92.31	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.68	86.84	65.38			62.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	98.44	100.00			100.00	85.71	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

---

Module Instance : tb.dut.u_msg_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	98.44	100.00			100.00	85.71	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

SCORE	LINE
93.91	92.31

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
91.87	92.86

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
91.87	88.89

tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T20,T21
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.91	83.33

tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_msg_fifo

SCORE	BRANCH
91.87	85.71

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

SCORE	BRANCH
93.91	100.00

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	492327805	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1521464184	85658244	0	0
gen_passthru_fifo.paramCheckPass	4386	4386	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	492327805	0	0
T1	496992	70789	0	0
T2	7792	52	0	0
T3	2482376	359976	0	0
T4	4308440	711542	0	0
T5	6229568	1279505	0	0
T6	1230128	436457	0	0
T7	19792	1966	0	0
T8	1497872	311685	0	0
T9	0	552988	0	0
T18	3096720	1804785	0	0
T22	12248	182	0	0
T25	0	80451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	621240	620520	0	0
T2	9740	9210	0	0
T3	3102970	3102140	0	0
T4	5385550	5384890	0	0
T5	7786960	7783610	0	0
T6	1537660	1536800	0	0
T7	24740	24160	0	0
T8	1872340	1871750	0	0
T18	3870900	3870840	0	0
T22	15310	14730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	621240	620520	0	0
T2	9740	9210	0	0
T3	3102970	3102140	0	0
T4	5385550	5384890	0	0
T5	7786960	7783610	0	0
T6	1537660	1536800	0	0
T7	24740	24160	0	0
T8	1872340	1871750	0	0
T18	3870900	3870840	0	0
T22	15310	14730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	621240	620520	0	0
T2	9740	9210	0	0
T3	3102970	3102140	0	0
T4	5385550	5384890	0	0
T5	7786960	7783610	0	0
T6	1537660	1536800	0	0
T7	24740	24160	0	0
T8	1872340	1871750	0	0
T18	3870900	3870840	0	0
T22	15310	14730	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521464184	85658244	0	0
T1	124248	35385	0	0
T2	1948	0	0	0
T3	620594	74642	0	0
T4	1077110	135422	0	0
T5	1557392	386041	0	0
T6	307532	127333	0	0
T7	4948	790	0	0
T8	374468	90583	0	0
T9	0	307756	0	0
T18	774180	439823	0	0
T22	3062	0	0	0
T25	0	51829	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	4386	4386	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T18	6	6	0	0
T22	6	6	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	13	92.86
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete	Exclusion	Exclude Annotation
DataKnown_A					Excluded	[UNSUPPORTED] excluded by fpv
DepthKnown_A	380366046	380296906	0	0
RvalidKnown_A	380366046	380296906	0	0
WreadyKnown_A	380366046	380296906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth					Excluded	[UNSUPPORTED] excluded by fpv

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	0	0
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108		excluded
			Exclude Annotation: [UNR] Pass is always '1'
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete	Exclusion	Exclude Annotation
DataKnown_A					Excluded	[UNSUPPORTED] excluded by fpv
DepthKnown_A	380366046	380296906	0	0
RvalidKnown_A	380366046	380296906	0	0
WreadyKnown_A	380366046	380296906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth					Excluded	[UNSUPPORTED] excluded by fpv

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

Line Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T20,T21
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T3,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_msg_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380366046	52292725	0	0
DepthKnown_A	380366046	380296906	0	0
RvalidKnown_A	380366046	380296906	0	0
WreadyKnown_A	380366046	380296906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	380366046	52292725	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	52292725	0	0
T1	62124	29017	0	0
T2	974	0	0	0
T3	310297	32771	0	0
T4	538555	45293	0	0
T5	778696	171851	0	0
T6	153766	99236	0	0
T7	2474	741	0	0
T8	187234	70596	0	0
T9	0	187081	0	0
T18	387090	105648	0	0
T22	1531	0	0	0
T25	0	37627	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	52292725	0	0
T1	62124	29017	0	0
T2	974	0	0	0
T3	310297	32771	0	0
T4	538555	45293	0	0
T5	778696	171851	0	0
T6	153766	99236	0	0
T7	2474	741	0	0
T8	187234	70596	0	0
T9	0	187081	0	0
T18	387090	105648	0	0
T22	1531	0	0	0
T25	0	37627	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T3,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380366046	33365519	0	0
DepthKnown_A	380366046	380296906	0	0
RvalidKnown_A	380366046	380296906	0	0
WreadyKnown_A	380366046	380296906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	380366046	33365519	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	33365519	0	0
T1	62124	6368	0	0
T2	974	0	0	0
T3	310297	41871	0	0
T4	538555	90129	0	0
T5	778696	214190	0	0
T6	153766	28097	0	0
T7	2474	49	0	0
T8	187234	19987	0	0
T9	0	120675	0	0
T18	387090	334175	0	0
T22	1531	0	0	0
T25	0	14202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	380296906	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	380366046	33365519	0	0
T1	62124	6368	0	0
T2	974	0	0	0
T3	310297	41871	0	0
T4	538555	90129	0	0
T5	778696	214190	0	0
T6	153766	28097	0	0
T7	2474	49	0	0
T8	187234	19987	0	0
T9	0	120675	0	0
T18	387090	334175	0	0
T22	1531	0	0	0
T25	0	14202	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	80834105	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	80834105	0	0
T1	62124	8987	0	0
T2	974	13	0	0
T3	310297	36351	0	0
T4	538555	55766	0	0
T5	778696	98865	0	0
T6	153766	82104	0	0
T7	2474	294	0	0
T8	187234	57347	0	0
T18	387090	366990	0	0
T22	1531	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	123255142	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	123255142	0	0
T1	62124	8715	0	0
T2	974	13	0	0
T3	310297	106316	0	0
T4	538555	232294	0	0
T5	778696	347867	0	0
T6	153766	72458	0	0
T7	2474	294	0	0
T8	187234	53204	0	0
T18	387090	165112	0	0
T22	1531	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	25568438	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	25568438	0	0
T1	62124	6640	0	0
T2	974	0	0	0
T3	310297	15426	0	0
T4	538555	23975	0	0
T5	778696	69347	0	0
T6	153766	37743	0	0
T7	2474	49	0	0
T8	187234	24128	0	0
T9	0	124557	0	0
T18	387090	74191	0	0
T22	1531	0	0	0
T25	0	14420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	33615319	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	33615319	0	0
T1	62124	6368	0	0
T2	974	0	0	0
T3	310297	41871	0	0
T4	538555	90129	0	0
T5	778696	214190	0	0
T6	153766	28097	0	0
T7	2474	49	0	0
T8	187234	19987	0	0
T9	0	120675	0	0
T18	387090	334175	0	0
T22	1531	0	0	0
T25	0	14202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	53756734	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	53756734	0	0
T1	62124	2347	0	0
T2	974	13	0	0
T3	310297	20925	0	0
T4	538555	31791	0	0
T5	778696	29518	0	0
T6	153766	44361	0	0
T7	2474	245	0	0
T8	187234	33219	0	0
T18	387090	292799	0	0
T22	1531	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387528230	89639823	0	0
DepthKnown_A	387528230	387410814	0	0
RvalidKnown_A	387528230	387410814	0	0
WreadyKnown_A	387528230	387410814	0	0
gen_passthru_fifo.paramCheckPass	731	731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	89639823	0	0
T1	62124	2347	0	0
T2	974	13	0	0
T3	310297	64445	0	0
T4	538555	142165	0	0
T5	778696	133677	0	0
T6	153766	44361	0	0
T7	2474	245	0	0
T8	187234	33217	0	0
T18	387090	131695	0	0
T22	1531	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387528230	387410814	0	0
T1	62124	62052	0	0
T2	974	921	0	0
T3	310297	310214	0	0
T4	538555	538489	0	0
T5	778696	778361	0	0
T6	153766	153680	0	0
T7	2474	2416	0	0
T8	187234	187175	0	0
T18	387090	387084	0	0
T22	1531	1473	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	731	731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0