Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44325998

1

T1

33885

T2

6871

T3

188470

full_word

43270813

1

T1

35255

T2

5927

T3

192521

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87596371	1			T1	69140		T2	12798		T3	380991
auto[TlIntgErrCmd]	151	1			T61	7		T62	6		T63	5
auto[TlIntgErrData]	138	1			T61	9		T62	4		T63	9
auto[TlIntgErrBoth]	151	1			T61	14		T63	6		T113	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34795503

1

T1

30428

T2

5226

T3

147439

auto[1]

52801308

1

T1

38712

T2

7572

T3

233552

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18534082	1			T1	15265		T2	2594		T3	73582
auto[TlIntgErrNone]	partial	auto[1]	25791516	1			T1	18620		T2	4277		T3	114888
auto[TlIntgErrNone]	full_word	auto[0]	16261225	1			T1	15163		T2	2632		T3	73857
auto[TlIntgErrNone]	full_word	auto[1]	27009548	1			T1	20092		T2	3295		T3	118664
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T61	2		T62	2		T63	3
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T61	5		T62	4		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T63	1		T116	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T118	1		T119	1		T67	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T61	5		T62	1		T63	5
auto[TlIntgErrData]	partial	auto[1]	60	1			T61	4		T62	2		T63	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T114	1		T116	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T62	1		T63	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T61	4		T63	2		T113	1
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T61	8		T63	3		T113	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T114	1		T116	1		T117	2
auto[TlIntgErrBoth]	full_word	auto[1]	13	1			T61	2		T63	1		T64	1