Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506095285	2131172	0	0
intr_enable_rd_A	506095285	2355	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506095285	2131172	0	0
T7	351708	104736	0	0
T8	0	283960	0	0
T9	0	69818	0	0
T10	0	177649	0	0
T11	0	447665	0	0
T12	0	142056	0	0
T45	0	83636	0	0
T68	0	27311	0	0
T69	0	50308	0	0
T70	0	12333	0	0
T71	108156	0	0	0
T72	700956	0	0	0
T73	33815	0	0	0
T74	82825	0	0	0
T75	317083	0	0	0
T76	194630	0	0	0
T77	1420	0	0	0
T78	102663	0	0	0
T79	353851	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506095285	2355	0	0
T16	815784	42	0	0
T52	133159	0	0	0
T80	0	23	0	0
T81	0	43	0	0
T82	0	26	0	0
T83	0	28	0	0
T84	0	11	0	0
T85	0	28	0	0
T86	0	55	0	0
T87	0	27	0	0
T88	0	206	0	0
T89	114454	0	0	0
T90	101084	0	0	0
T91	6594	0	0	0
T92	19253	0	0	0
T93	724590	0	0	0
T94	753509	0	0	0
T95	287607	0	0	0
T96	5697	0	0	0