Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38642538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42017741

1

T1

9562

T2

680236

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32104090	1			T1	1072		T2	534180		T3	1
values[0x0]	22633441	1			T1	4970		T2	378990		T3	4
values[0x1]	25922748	1			T1	5261		T2	428490		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28409678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52250601

1

T1

10203

T2

846087

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	315828	1			T1	44		T2	5546		T4	11
valid_sources[0x01]	293954	1			T1	45		T2	5090		T4	18
valid_sources[0x02]	275134	1			T1	38		T2	5114		T4	118
valid_sources[0x03]	277826	1			T1	41		T2	5083		T4	32
valid_sources[0x04]	322888	1			T1	51		T2	5139		T4	35
valid_sources[0x05]	276414	1			T1	34		T2	5239		T3	3
valid_sources[0x06]	286711	1			T1	58		T2	5346		T4	5
valid_sources[0x07]	288770	1			T1	39		T2	5338		T4	40
valid_sources[0x08]	659276	1			T1	49		T2	5198		T4	164
valid_sources[0x09]	655062	1			T1	41		T2	5143		T4	34
valid_sources[0x0a]	264551	1			T1	36		T2	5280		T4	331
valid_sources[0x0b]	269567	1			T1	54		T2	5263		T4	55
valid_sources[0x0c]	274980	1			T1	29		T2	5089		T4	221
valid_sources[0x0d]	286352	1			T1	41		T2	5322		T4	5
valid_sources[0x0e]	276691	1			T1	46		T2	5374		T4	31
valid_sources[0x0f]	679599	1			T1	42		T2	5270		T4	7
valid_sources[0x10]	271493	1			T1	37		T2	5267		T4	33
valid_sources[0x11]	304609	1			T1	53		T2	5213		T4	295
valid_sources[0x12]	287095	1			T1	38		T2	5293		T4	1
valid_sources[0x13]	269966	1			T1	33		T2	5248		T4	18
valid_sources[0x14]	660923	1			T1	40		T2	5087		T4	23
valid_sources[0x15]	293103	1			T1	55		T2	5191		T4	23
valid_sources[0x16]	269155	1			T1	35		T2	5302		T4	68
valid_sources[0x17]	261468	1			T1	49		T2	5068		T4	24
valid_sources[0x18]	278172	1			T1	44		T2	5095		T4	28
valid_sources[0x19]	271280	1			T1	45		T2	5373		T3	1
valid_sources[0x1a]	269365	1			T1	55		T2	5374		T4	48
valid_sources[0x1b]	268345	1			T1	55		T2	5307		T4	33
valid_sources[0x1c]	265999	1			T1	45		T2	5291		T4	14
valid_sources[0x1d]	289561	1			T1	44		T2	5404		T4	44
valid_sources[0x1e]	279709	1			T1	43		T2	5371		T5	81
valid_sources[0x1f]	282194	1			T1	59		T2	5454		T4	10
valid_sources[0x20]	255707	1			T1	60		T2	5299		T4	115
valid_sources[0x21]	274363	1			T1	43		T2	5230		T4	28
valid_sources[0x22]	311199	1			T1	55		T2	5228		T4	220
valid_sources[0x23]	279107	1			T1	30		T2	5097		T4	27
valid_sources[0x24]	289020	1			T1	41		T2	5045		T4	110
valid_sources[0x25]	279925	1			T1	58		T2	4894		T4	73
valid_sources[0x26]	279205	1			T1	42		T2	5149		T4	24
valid_sources[0x27]	272430	1			T1	46		T2	5238		T4	23
valid_sources[0x28]	301317	1			T1	41		T2	5117		T4	1
valid_sources[0x29]	279338	1			T1	52		T2	5246		T4	29
valid_sources[0x2a]	283555	1			T1	48		T2	5605		T4	63
valid_sources[0x2b]	1013290	1			T1	48		T2	5327		T4	78
valid_sources[0x2c]	276586	1			T1	37		T2	5105		T4	9
valid_sources[0x2d]	673990	1			T1	38		T2	5151		T4	131
valid_sources[0x2e]	256066	1			T1	52		T2	5192		T4	103
valid_sources[0x2f]	285326	1			T1	34		T2	5500		T4	217
valid_sources[0x30]	278791	1			T1	41		T2	5211		T4	60
valid_sources[0x31]	276812	1			T1	32		T2	5386		T4	35
valid_sources[0x32]	269981	1			T1	62		T2	5043		T4	49
valid_sources[0x33]	274781	1			T1	61		T2	5199		T4	612
valid_sources[0x34]	289264	1			T1	50		T2	5226		T4	49
valid_sources[0x35]	302004	1			T1	48		T2	5242		T4	33
valid_sources[0x36]	269714	1			T1	50		T2	5285		T4	17
valid_sources[0x37]	274415	1			T1	54		T2	5357		T4	237
valid_sources[0x38]	304974	1			T1	26		T2	5195		T4	24
valid_sources[0x39]	663418	1			T1	37		T2	5511		T4	30
valid_sources[0x3a]	261264	1			T1	57		T2	5209		T4	59
valid_sources[0x3b]	304616	1			T1	37		T2	5236		T4	16
valid_sources[0x3c]	280955	1			T1	56		T2	5331		T4	23
valid_sources[0x3d]	264726	1			T1	48		T2	5313		T4	20
valid_sources[0x3e]	284327	1			T1	55		T2	5449		T4	86
valid_sources[0x3f]	284084	1			T1	42		T2	5329		T4	274
valid_sources[0x40]	275113	1			T1	62		T2	5263		T4	23
valid_sources[0x41]	287618	1			T1	47		T2	5359		T4	21
valid_sources[0x42]	273838	1			T1	31		T2	5394		T4	429
valid_sources[0x43]	307608	1			T1	38		T2	5299		T4	81
valid_sources[0x44]	298350	1			T1	43		T2	5374		T4	17
valid_sources[0x45]	282364	1			T1	34		T2	4957		T4	125
valid_sources[0x46]	259997	1			T1	35		T2	5139		T4	33
valid_sources[0x47]	270042	1			T1	46		T2	5162		T4	73
valid_sources[0x48]	266671	1			T1	44		T2	5575		T4	21
valid_sources[0x49]	285593	1			T1	40		T2	5310		T4	11
valid_sources[0x4a]	262221	1			T1	36		T2	5310		T4	25
valid_sources[0x4b]	257764	1			T1	56		T2	5366		T4	113
valid_sources[0x4c]	299971	1			T1	59		T2	5391		T4	249
valid_sources[0x4d]	286926	1			T1	22		T2	5368		T4	68
valid_sources[0x4e]	273853	1			T1	50		T2	5394		T4	31
valid_sources[0x4f]	270061	1			T1	26		T2	4999		T4	66
valid_sources[0x50]	261194	1			T1	57		T2	5105		T4	24
valid_sources[0x51]	284884	1			T1	37		T2	5199		T4	23
valid_sources[0x52]	286560	1			T1	40		T2	5411		T4	117
valid_sources[0x53]	259534	1			T1	36		T2	5217		T4	21
valid_sources[0x54]	269212	1			T1	37		T2	5269		T4	39
valid_sources[0x55]	275701	1			T1	38		T2	5153		T4	54
valid_sources[0x56]	284012	1			T1	63		T2	5283		T4	170
valid_sources[0x57]	311275	1			T1	41		T2	5127		T4	15
valid_sources[0x58]	265412	1			T1	30		T2	5255		T4	48
valid_sources[0x59]	272808	1			T1	41		T2	5368		T4	11
valid_sources[0x5a]	301141	1			T1	32		T2	5335		T4	30
valid_sources[0x5b]	289754	1			T1	52		T2	5204		T4	5
valid_sources[0x5c]	279871	1			T1	34		T2	5318		T4	35
valid_sources[0x5d]	310645	1			T1	34		T2	5214		T4	30
valid_sources[0x5e]	663860	1			T1	40		T2	5354		T4	21
valid_sources[0x5f]	269719	1			T1	42		T2	4973		T4	12
valid_sources[0x60]	306332	1			T1	42		T2	5011		T4	12
valid_sources[0x61]	269265	1			T1	39		T2	5319		T4	234
valid_sources[0x62]	283225	1			T1	47		T2	5059		T4	53
valid_sources[0x63]	316739	1			T1	47		T2	5397		T4	78
valid_sources[0x64]	274582	1			T1	47		T2	5506		T4	15
valid_sources[0x65]	292011	1			T1	43		T2	5051		T4	13
valid_sources[0x66]	275051	1			T1	63		T2	5170		T4	6
valid_sources[0x67]	618210	1			T1	39		T2	5328		T4	5
valid_sources[0x68]	590396	1			T1	43		T2	5238		T4	35
valid_sources[0x69]	266981	1			T1	49		T2	5095		T4	105
valid_sources[0x6a]	263311	1			T1	50		T2	5377		T4	275
valid_sources[0x6b]	298851	1			T1	28		T2	5396		T4	2
valid_sources[0x6c]	633549	1			T1	41		T2	5227		T4	59
valid_sources[0x6d]	297558	1			T1	45		T2	5296		T4	156
valid_sources[0x6e]	260529	1			T1	29		T2	5165		T4	1
valid_sources[0x6f]	285231	1			T1	48		T2	4947		T4	11
valid_sources[0x70]	655597	1			T1	37		T2	5336		T4	50
valid_sources[0x71]	288254	1			T1	60		T2	5066		T4	29
valid_sources[0x72]	1066416	1			T1	46		T2	5312		T4	36
valid_sources[0x73]	279455	1			T1	44		T2	5279		T4	44
valid_sources[0x74]	275544	1			T1	37		T2	5126		T4	16
valid_sources[0x75]	273978	1			T1	44		T2	5291		T4	39
valid_sources[0x76]	262305	1			T1	66		T2	5185		T4	31
valid_sources[0x77]	273794	1			T1	45		T2	5106		T4	49
valid_sources[0x78]	262607	1			T1	44		T2	5099		T3	2
valid_sources[0x79]	659096	1			T1	64		T2	5262		T4	7
valid_sources[0x7a]	284326	1			T1	48		T2	5331		T4	121
valid_sources[0x7b]	297153	1			T1	45		T2	5208		T4	124
valid_sources[0x7c]	280528	1			T1	68		T2	5022		T4	68
valid_sources[0x7d]	273530	1			T1	58		T2	5346		T4	43
valid_sources[0x7e]	270794	1			T1	44		T2	5348		T4	19
valid_sources[0x7f]	257183	1			T1	45		T2	5105		T4	156
valid_sources[0x80]	271729	1			T1	56		T2	5345		T4	125

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15556882

1

T1

322

T2

267160

T4

4060

values[0x0]

all_enables

biggest_size

13904831

1

T1

4605

T2

219911

T3

1

values[0x1]

all_enables

biggest_size

12556028

1

T1

4635

T2

193165

T3

1