Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44523402

1

T1

1741

T2

661424

T3

7

full_word

42401734

1

T1

9562

T2

680236

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86924796	1			T1	11303		T2	134166		T3	9
auto[TlIntgErrCmd]	124	1			T50	5		T51	3		T52	4
auto[TlIntgErrData]	120	1			T50	5		T51	5		T52	2
auto[TlIntgErrBoth]	96	1			T50	10		T51	2		T52	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34119868

1

T1

1072

T2

534180

T3

1

auto[1]

52805268

1

T1

10231

T2

807480

T3

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18409305	1			T1	750		T2	267020		T3	1
auto[TlIntgErrNone]	partial	auto[1]	26113774	1			T1	991		T2	394404		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	15710415	1			T1	322		T2	267160		T4	4060
auto[TlIntgErrNone]	full_word	auto[1]	26691302	1			T1	9240		T2	413076		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T50	4		T52	2		T96	6
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T50	1		T51	3		T52	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T102	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T104	1		T105	1		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T50	2		T52	1		T96	1
auto[TlIntgErrData]	partial	auto[1]	62	1			T50	3		T51	5		T52	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T106	1		T107	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T96	1		T98	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T50	2		T51	1		T52	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T50	7		T51	1		T52	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T104	1		T108	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T50	1		T101	1		-	-