Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	446868967	3322225	0	0
intr_enable_rd_A	446868967	2316	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446868967	3322225	0	0
T6	632823	272741	0	0
T7	0	118393	0	0
T8	0	49226	0	0
T9	0	206390	0	0
T10	0	213496	0	0
T19	0	48089	0	0
T27	6253	0	0	0
T32	105600	0	0	0
T33	4583	0	0	0
T41	0	35797	0	0
T56	0	143021	0	0
T57	0	73421	0	0
T58	0	306834	0	0
T59	169137	0	0	0
T60	175914	0	0	0
T61	261864	0	0	0
T62	108788	0	0	0
T63	1262	0	0	0
T64	352631	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446868967	2316	0	0
T2	122540	13	0	0
T3	1309	0	0	0
T4	205870	0	0	0
T5	64058	0	0	0
T14	320965	0	0	0
T17	1117	0	0	0
T18	1085	0	0	0
T25	12304	0	0	0
T26	32297	0	0	0
T38	5037	0	0	0
T46	0	5	0	0
T55	0	10	0	0
T65	0	41	0	0
T66	0	31	0	0
T67	0	15	0	0
T68	0	26	0	0
T69	0	48	0	0
T70	0	77	0	0
T71	0	32	0	0