Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42567331

1

T1

8898

T2

6

T3

17154

full_word

42277178

1

T1

7741

T2

1

T3

14410

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84844129	1			T1	16639		T2	7		T3	31564
auto[TlIntgErrCmd]	135	1			T59	4		T60	6		T61	9
auto[TlIntgErrData]	127	1			T59	1		T60	14		T61	6
auto[TlIntgErrBoth]	118	1			T59	5		T60	10		T61	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33489805

1

T1

6823

T2

1

T3

15600

auto[1]

51354704

1

T1

9816

T2

6

T3

15964

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17688198	1			T1	3391		T3	7815		T4	126840
auto[TlIntgErrNone]	partial	auto[1]	24878791	1			T1	5507		T2	6		T3	9339
auto[TlIntgErrNone]	full_word	auto[0]	15801434	1			T1	3432		T2	1		T3	7785
auto[TlIntgErrNone]	full_word	auto[1]	26475706	1			T1	4309		T3	6625		T4	192861
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T59	2		T60	1		T61	7
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T59	2		T60	5		T61	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T110	2		T113	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T61	1		T108	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T60	4		T61	2		T108	2
auto[TlIntgErrData]	partial	auto[1]	60	1			T59	1		T60	9		T61	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T60	1		T116	2		T117	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T110	2		T118	2		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T59	2		T60	6		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T59	3		T60	3		T61	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T110	1		T117	1		T119	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T60	1		T117	2		T118	1