Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44862058

1

T1

22873

T2

32583

T3

135

full_word

43372486

1

T1

21163

T2

28288

T3

130

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88234124	1			T1	44036		T2	60871		T3	265
auto[TlIntgErrCmd]	146	1			T63	3		T64	5		T65	3
auto[TlIntgErrData]	133	1			T63	2		T64	5		T65	4
auto[TlIntgErrBoth]	141	1			T63	5		T64	10		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35035963

1

T1

18362

T2

24817

T3

135

auto[1]

53198581

1

T1

25674

T2

36054

T3

130

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18876205	1			T1	9133		T2	12483		T3	77
auto[TlIntgErrNone]	partial	auto[1]	25985468	1			T1	13740		T2	20100		T3	58
auto[TlIntgErrNone]	full_word	auto[0]	16159560	1			T1	9229		T2	12334		T3	58
auto[TlIntgErrNone]	full_word	auto[1]	27212891	1			T1	11934		T2	15954		T3	72
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T64	2		T65	1		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T63	3		T64	3		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T120	1		T122	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T65	1		T121	1		T119	2
auto[TlIntgErrData]	partial	auto[0]	63	1			T64	4		T65	2		T121	7
auto[TlIntgErrData]	partial	auto[1]	58	1			T63	1		T65	2		T121	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T63	1		T121	2		T119	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T64	1		T124	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T63	1		T64	4		T65	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T63	4		T64	6		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T123	1		T125	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T124	1		T122	1		T123	2