Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	467079243	2369893	0	0
intr_enable_rd_A	467079243	4161	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467079243	2369893	0	0
T8	0	27786	0	0
T9	0	139977	0	0
T10	0	164320	0	0
T11	0	295801	0	0
T12	0	171901	0	0
T21	526513	235814	0	0
T62	264875	0	0	0
T69	0	53397	0	0
T70	0	76596	0	0
T71	0	251181	0	0
T72	0	215245	0	0
T73	6555	0	0	0
T74	131440	0	0	0
T75	2491	0	0	0
T76	10063	0	0	0
T77	140142	0	0	0
T78	46122	0	0	0
T79	768	0	0	0
T80	73412	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467079243	4161	0	0
T4	501065	36	0	0
T6	114696	0	0	0
T7	684978	0	0	0
T17	7666	0	0	0
T25	1022	0	0	0
T27	3163	0	0	0
T29	190331	0	0	0
T30	961341	0	0	0
T33	17451	0	0	0
T39	6532	0	0	0
T49	0	41	0	0
T81	0	10	0	0
T82	0	22	0	0
T83	0	28	0	0
T84	0	25	0	0
T85	0	30	0	0
T86	0	16	0	0
T87	0	30	0	0
T88	0	38	0	0