Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

37104973

1

T1

76868

T2

32810

T3

1488

full_word

36350190

1

T1

72621

T2

27485

T3

1319

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	73454783	1			T1	149489		T2	60295		T3	2807
auto[TlIntgErrCmd]	133	1			T69	2		T70	8		T71	12
auto[TlIntgErrData]	126	1			T69	4		T70	3		T71	8
auto[TlIntgErrBoth]	121	1			T69	4		T70	9		T71	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28990694

1

T1

66558

T2

24518

T3

1410

auto[1]

44464469

1

T1

82931

T2

35777

T3

1397

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15384497	1			T1	33517		T2	12478		T3	665
auto[TlIntgErrNone]	partial	auto[1]	21720123	1			T1	43351		T2	20332		T3	823
auto[TlIntgErrNone]	full_word	auto[0]	13606011	1			T1	33041		T2	12040		T3	745
auto[TlIntgErrNone]	full_word	auto[1]	22744152	1			T1	39580		T2	15445		T3	574
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T69	1		T70	3		T71	5
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T69	1		T70	3		T71	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T70	1		T128	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T70	1		T130	1		T131	2
auto[TlIntgErrData]	partial	auto[0]	63	1			T69	2		T70	2		T71	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T69	2		T71	4		T122	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T122	1		T125	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T70	1		T132	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T69	2		T70	5		T71	2
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T69	2		T70	4		T71	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T132	1		T128	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T125	1		T127	1		-	-