Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	422182487	1865717	0	0
intr_enable_rd_A	422182487	2988	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422182487	1865717	0	0
T8	276282	118441	0	0
T9	0	218843	0	0
T10	0	82048	0	0
T11	0	194528	0	0
T12	0	212216	0	0
T27	0	76166	0	0
T69	0	3	0	0
T70	0	2	0	0
T75	0	147901	0	0
T76	0	1297	0	0
T77	131064	0	0	0
T78	259194	0	0	0
T79	1079	0	0	0
T80	33886	0	0	0
T81	104755	0	0	0
T82	93947	0	0	0
T83	246795	0	0	0
T84	859	0	0	0
T85	40422	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422182487	2988	0	0
T14	955404	31	0	0
T17	132055	13	0	0
T24	1162	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0
T86	0	22	0	0
T87	0	36	0	0
T88	0	10	0	0
T89	0	39	0	0
T90	0	11	0	0
T91	0	8	0	0
T92	0	31	0	0
T93	0	11	0	0
T94	357903	0	0	0
T95	93566	0	0	0
T96	261372	0	0	0
T97	264348	0	0	0