Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.10	100.00	93.75			86.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_packer	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T19,T21,T22
1	Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T19,T21,T22
1	1	Covered	T1,T2,T4

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T21,T22
1	1	Covered	T1,T2,T4

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T4

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	26	86.67
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
CASE	80	5	3	60.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T4
2'b10	Covered	T1,T2,T4
2'b11	Covered	T19,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T2,T4
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T2,T4
FlushSend	-	0	Covered	T1,T2,T4
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T1,T2,T4
2'b01	0	-	Unreachable	T1,T2,T4
2'b10	-	-	Covered	T1,T2,T4
2'b11	-	1	Not Covered
2'b11	-	0	Unreachable	T19,T21,T22
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	399528690	2674130	0	562
DataOStableWhenPending_A	399528690	3311940	0	562
ExFlushValid_M	399528690	39079	0	0
ExcessiveDataStored_A	399528690	15570	0	0
ExcessiveMaskStored_A	399528690	15570	0	0
FlushFollowedByDone_A	399528690	39079	0	562
ValidIDeassertedOnFlush_M	399528690	75524	0	0
ValidOAssertedForStoredDataGTEOutW_A	399528690	16655009	0	0
ValidOPairedWidthReadyI_A	399528690	3311940	0	0
gen_mask_assert.ContiguousOnesMask_M	399528690	20485102	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	2674130	0	562
T17	132055	0	0	1
T19	153566	49785	0	1
T21	0	16742	0	0
T22	0	24480	0	0
T29	164452	0	0	1
T30	244488	0	0	1
T56	0	65691	0	0
T57	0	14130	0	0
T58	0	7084	0	0
T59	0	55754	0	0
T60	0	56087	0	0
T61	0	38118	0	0
T62	0	60881	0	0
T63	50195	0	0	1
T64	34634	0	0	1
T65	266424	0	0	1
T66	202692	0	0	1
T67	6989	0	0	1
T68	724645	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	3311940	0	562
T17	132055	0	0	1
T19	153566	71949	0	1
T21	0	24181	0	0
T22	0	35460	0	0
T29	164452	0	0	1
T30	244488	0	0	1
T56	0	66654	0	0
T57	0	20462	0	0
T58	0	7166	0	0
T59	0	80503	0	0
T60	0	81444	0	0
T61	0	38644	0	0
T62	0	61672	0	0
T63	50195	0	0	1
T64	34634	0	0	1
T65	266424	0	0	1
T66	202692	0	0	1
T67	6989	0	0	1
T68	724645	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	39079	0	0
T1	305474	15	0	0
T2	131872	32	0	0
T3	7093	0	0	0
T4	2593	4	0	0
T5	59080	10	0	0
T6	36213	31	0	0
T7	176559	7	0	0
T13	833421	194	0	0
T26	94266	43	0	0
T28	125905	39	0	0
T48	0	4	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	15570	0	0
T17	132055	0	0	0
T19	153566	282	0	0
T21	0	110	0	0
T22	0	159	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	334	0	0
T57	0	95	0	0
T58	0	37	0	0
T59	0	366	0	0
T60	0	360	0	0
T61	0	216	0	0
T62	0	300	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	15570	0	0
T17	132055	0	0	0
T19	153566	282	0	0
T21	0	110	0	0
T22	0	159	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	334	0	0
T57	0	95	0	0
T58	0	37	0	0
T59	0	366	0	0
T60	0	360	0	0
T61	0	216	0	0
T62	0	300	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	39079	0	562
T1	305474	15	0	1
T2	131872	32	0	1
T3	7093	0	0	1
T4	2593	4	0	1
T5	59080	10	0	1
T6	36213	31	0	1
T7	176559	7	0	1
T13	833421	194	0	1
T26	94266	43	0	1
T28	125905	39	0	1
T48	0	4	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	75524	0	0
T1	305474	27	0	0
T2	131872	64	0	0
T3	7093	0	0	0
T4	2593	6	0	0
T5	59080	17	0	0
T6	36213	48	0	0
T7	176559	11	0	0
T13	833421	338	0	0
T26	94266	76	0	0
T28	125905	65	0	0
T48	0	6	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	16655009	0	0
T1	305474	10185	0	0
T2	131872	16592	0	0
T3	7093	0	0	0
T4	2593	33	0	0
T5	59080	3718	0	0
T6	36213	237	0	0
T7	176559	5706	0	0
T13	833421	53472	0	0
T26	94266	8468	0	0
T28	125905	13279	0	0
T48	0	33	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	3311940	0	0
T17	132055	0	0	0
T19	153566	71949	0	0
T21	0	24181	0	0
T22	0	35460	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	66654	0	0
T57	0	20462	0	0
T58	0	7166	0	0
T59	0	80503	0	0
T60	0	81444	0	0
T61	0	38644	0	0
T62	0	61672	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	20485102	0	0
T1	305474	14101	0	0
T2	131872	23033	0	0
T3	7093	0	0	0
T4	2593	50	0	0
T5	59080	3750	0	0
T6	36213	373	0	0
T7	176559	7940	0	0
T13	833421	74295	0	0
T26	94266	9064	0	0
T28	125905	18454	0	0
T48	0	51	0	0

Line Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
			Exclude Annotation: VC_COV_UNR
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_packer

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------
 Exclude Annotation: [UNR] cannot have (ack_in & ack_out) = 1

-1-	Status	Tests
0	Unreachable	T19,T21,T22
1	Excluded

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T19,T21,T22
1	1	Covered	T1,T2,T4

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T21,T22
1	1	Covered	T1,T2,T4

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
IF	159	2	2	100.00
CASE	185	4	4	100.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	4	4	100.00
CASE	80	3	3	100.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests	Exclude Annotation
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T4
2'b10	Covered	T1,T2,T4
2'b11	Covered	T19,T21,T22
default	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
FlushIdle	1	-	Covered	T1,T2,T4
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T2,T4
FlushSend	-	0	Covered	T1,T2,T4
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T1,T2,T4
2'b01	0	-	Unreachable	T1,T2,T4
2'b10	-	-	Covered	T1,T2,T4
2'b11	-	1	Excluded		[UNR] cannot have (ack_in & ack_out) = 1
2'b11	-	0	Unreachable	T19,T21,T22
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	399528690	2674130	0	562
DataOStableWhenPending_A	399528690	3311940	0	562
ExFlushValid_M	399528690	39079	0	0
ExcessiveDataStored_A	399528690	15570	0	0
ExcessiveMaskStored_A	399528690	15570	0	0
FlushFollowedByDone_A	399528690	39079	0	562
ValidIDeassertedOnFlush_M	399528690	75524	0	0
ValidOAssertedForStoredDataGTEOutW_A	399528690	16655009	0	0
ValidOPairedWidthReadyI_A	399528690	3311940	0	0
gen_mask_assert.ContiguousOnesMask_M	399528690	20485102	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	2674130	0	562
T17	132055	0	0	1
T19	153566	49785	0	1
T21	0	16742	0	0
T22	0	24480	0	0
T29	164452	0	0	1
T30	244488	0	0	1
T56	0	65691	0	0
T57	0	14130	0	0
T58	0	7084	0	0
T59	0	55754	0	0
T60	0	56087	0	0
T61	0	38118	0	0
T62	0	60881	0	0
T63	50195	0	0	1
T64	34634	0	0	1
T65	266424	0	0	1
T66	202692	0	0	1
T67	6989	0	0	1
T68	724645	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	3311940	0	562
T17	132055	0	0	1
T19	153566	71949	0	1
T21	0	24181	0	0
T22	0	35460	0	0
T29	164452	0	0	1
T30	244488	0	0	1
T56	0	66654	0	0
T57	0	20462	0	0
T58	0	7166	0	0
T59	0	80503	0	0
T60	0	81444	0	0
T61	0	38644	0	0
T62	0	61672	0	0
T63	50195	0	0	1
T64	34634	0	0	1
T65	266424	0	0	1
T66	202692	0	0	1
T67	6989	0	0	1
T68	724645	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	39079	0	0
T1	305474	15	0	0
T2	131872	32	0	0
T3	7093	0	0	0
T4	2593	4	0	0
T5	59080	10	0	0
T6	36213	31	0	0
T7	176559	7	0	0
T13	833421	194	0	0
T26	94266	43	0	0
T28	125905	39	0	0
T48	0	4	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	15570	0	0
T17	132055	0	0	0
T19	153566	282	0	0
T21	0	110	0	0
T22	0	159	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	334	0	0
T57	0	95	0	0
T58	0	37	0	0
T59	0	366	0	0
T60	0	360	0	0
T61	0	216	0	0
T62	0	300	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	15570	0	0
T17	132055	0	0	0
T19	153566	282	0	0
T21	0	110	0	0
T22	0	159	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	334	0	0
T57	0	95	0	0
T58	0	37	0	0
T59	0	366	0	0
T60	0	360	0	0
T61	0	216	0	0
T62	0	300	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	39079	0	562
T1	305474	15	0	1
T2	131872	32	0	1
T3	7093	0	0	1
T4	2593	4	0	1
T5	59080	10	0	1
T6	36213	31	0	1
T7	176559	7	0	1
T13	833421	194	0	1
T26	94266	43	0	1
T28	125905	39	0	1
T48	0	4	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	75524	0	0
T1	305474	27	0	0
T2	131872	64	0	0
T3	7093	0	0	0
T4	2593	6	0	0
T5	59080	17	0	0
T6	36213	48	0	0
T7	176559	11	0	0
T13	833421	338	0	0
T26	94266	76	0	0
T28	125905	65	0	0
T48	0	6	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	16655009	0	0
T1	305474	10185	0	0
T2	131872	16592	0	0
T3	7093	0	0	0
T4	2593	33	0	0
T5	59080	3718	0	0
T6	36213	237	0	0
T7	176559	5706	0	0
T13	833421	53472	0	0
T26	94266	8468	0	0
T28	125905	13279	0	0
T48	0	33	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	3311940	0	0
T17	132055	0	0	0
T19	153566	71949	0	0
T21	0	24181	0	0
T22	0	35460	0	0
T29	164452	0	0	0
T30	244488	0	0	0
T56	0	66654	0	0
T57	0	20462	0	0
T58	0	7166	0	0
T59	0	80503	0	0
T60	0	81444	0	0
T61	0	38644	0	0
T62	0	61672	0	0
T63	50195	0	0	0
T64	34634	0	0	0
T65	266424	0	0	0
T66	202692	0	0	0
T67	6989	0	0	0
T68	724645	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399528690	20485102	0	0
T1	305474	14101	0	0
T2	131872	23033	0	0
T3	7093	0	0	0
T4	2593	50	0	0
T5	59080	3750	0	0
T6	36213	373	0	0
T7	176559	7940	0	0
T13	833421	74295	0	0
T26	94266	9064	0	0
T28	125905	18454	0	0
T48	0	51	0	0