Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39349064

1

T1

72350

T2

32578

T3

7721

full_word

37786248

1

T1

72410

T2

26782

T3

24470

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	77134952	1			T1	144760		T2	59360		T3	32191
auto[TlIntgErrCmd]	122	1			T60	9		T61	4		T62	1
auto[TlIntgErrData]	108	1			T60	4		T61	3		T62	4
auto[TlIntgErrBoth]	130	1			T60	7		T61	3		T62	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30393675

1

T1

60572

T2

24340

T3

10269

auto[1]

46741637

1

T1

84188

T2

35020

T3

21922

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16384517	1			T1	30400		T2	12598		T3	7273
auto[TlIntgErrNone]	partial	auto[1]	22964217	1			T1	41950		T2	19980		T3	448
auto[TlIntgErrNone]	full_word	auto[0]	14009015	1			T1	30172		T2	11742		T3	2996
auto[TlIntgErrNone]	full_word	auto[1]	23777203	1			T1	42238		T2	15040		T3	21474
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T60	3		T61	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T60	5		T61	2		T62	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T61	1		T65	1		T105	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T60	1		T105	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T60	1		T61	2		T62	1
auto[TlIntgErrData]	partial	auto[1]	56	1			T60	2		T62	3		T100	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T60	1		T65	1		T106	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T61	1		T107	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T60	1		T61	1		T62	1
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T60	6		T61	2		T62	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T65	2		T109	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T62	1		T65	2		T110	1