Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	444473037	2443678	0	0
intr_enable_rd_A	444473037	3142	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444473037	2443678	0	0
T6	975376	39752	0	0
T7	0	176546	0	0
T8	0	47047	0	0
T9	0	609781	0	0
T12	108891	0	0	0
T13	607549	0	0	0
T17	1106	0	0	0
T20	47284	0	0	0
T21	0	200987	0	0
T41	597758	0	0	0
T42	0	161543	0	0
T43	0	35502	0	0
T55	824621	0	0	0
T56	57023	0	0	0
T57	530090	0	0	0
T58	173266	0	0	0
T66	0	207678	0	0
T67	0	53548	0	0
T68	0	353594	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444473037	3142	0	0
T13	607549	34	0	0
T15	848846	0	0	0
T16	132209	0	0	0
T17	1106	0	0	0
T18	868	0	0	0
T43	0	18	0	0
T59	53487	0	0	0
T69	0	31	0	0
T70	0	21	0	0
T71	0	21	0	0
T72	0	23	0	0
T73	0	29	0	0
T74	0	6	0	0
T75	0	72	0	0
T76	0	26	0	0
T77	225328	0	0	0
T78	130599	0	0	0
T79	2801	0	0	0
T80	118028	0	0	0