Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14920631	1			T1	88510		T2	73560		T3	1259
all_values[1]	14920631	1			T1	88510		T2	73560		T3	1259
all_values[2]	14920631	1			T1	88510		T2	73560		T3	1259

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120896

1

T17

11

T19

120

T36

137

auto[1]

44640997

1

T1

265530

T2

220680

T3

3777

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42414237

1

T1

252474

T2

211404

T3

3714

auto[1]

2347656

1

T1

13056

T2

9276

T3

63

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	45638	1			T19	118		T37	1		T90	367
all_values[0]	auto[0]	auto[1]	526	1			T19	2		T37	2		T90	4
all_values[0]	auto[1]	auto[0]	14823042	1			T1	88316		T2	73366		T3	1196
all_values[0]	auto[1]	auto[1]	51425	1			T1	194		T2	194		T3	63
all_values[1]	auto[0]	auto[0]	39261	1			T36	137		T27	430		T90	289
all_values[1]	auto[0]	auto[1]	224	1			T4	3		T20	1		T5	2
all_values[1]	auto[1]	auto[0]	14880467	1			T1	88510		T2	73560		T3	1259
all_values[1]	auto[1]	auto[1]	679	1			T17	2		T15	2		T4	19
all_values[2]	auto[0]	auto[0]	27074	1			T17	11		T37	3		T90	289
all_values[2]	auto[0]	auto[1]	8173	1			T15	1		T4	4		T5	10
all_values[2]	auto[1]	auto[0]	12598755	1			T1	75648		T2	64478		T3	1259
all_values[2]	auto[1]	auto[1]	2286629	1			T1	12862		T2	9082		T16	11709