Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7201543

1

T1

37406

T2

37302

T3

25

auto[1]

2778265

1

T3

25

T17

10613

T19

175

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2668572

1

T3

24

T17

20873

T36

9422

auto[1]

7311236

1

T1

37406

T2

37302

T3

26

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6493890

1

T1

37406

T2

37302

T3

23

auto[1]

3485918

1

T3

27

T17

16786

T19

175

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6732863	1			T1	26465		T2	23943		T3	5
fifo_depth[1]	478310	1			T1	2528		T2	2445		T17	47
fifo_depth[2]	380122	1			T1	2351		T2	2394		T17	124
fifo_depth[3]	296438	1			T1	1794		T2	2009		T17	136
fifo_depth[4]	249262	1			T1	1069		T2	1512		T17	270
fifo_depth[5]	218428	1			T1	792		T2	1236		T17	190
fifo_depth[6]	205684	1			T1	697		T2	1143		T17	291
fifo_depth[7]	182873	1			T1	591		T2	887		T17	192
fifo_depth[8]	166531	1			T1	464		T2	654		T17	756
fifo_depth[9]	114870	1			T1	308		T2	446		T17	303
fifo_depth[10]	87097	1			T1	170		T2	306		T17	465
fifo_depth[11]	55094	1			T1	100		T2	179		T17	305
fifo_depth[12]	54313	1			T1	50		T2	83		T17	970
fifo_depth[13]	28887	1			T1	12		T2	41		T17	402
fifo_depth[14]	35813	1			T1	10		T2	18		T17	777
fifo_depth[15]	24660	1			T1	4		T2	6		T17	466
fifo_depth[16]	94641	1			T1	1		T17	1808		T19	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3366678

1

T1

10941

T2

13359

T3

50

auto[1]

6613130

1

T1

26465

T2

23943

T17

188

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9860075

1

T1

37406

T2

37302

T3

45

auto[1]

119733

1

T3

5

T17

4378

T18

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

232453

1

T3

6

T17

7660

T36

1946

auto[0]

auto[0]

auto[0]

auto[1]

232126

1

T3

6

T17

2464

T36

197

auto[0]

auto[0]

auto[1]

auto[0]

1020822

1

T1

10941

T2

13359

T3

5

auto[0]

auto[0]

auto[1]

auto[1]

240265

1

T3

6

T17

1040

T36

231

auto[0]

auto[1]

auto[0]

auto[0]

367962

1

T3

8

T17

6091

T36

316

auto[0]

auto[1]

auto[0]

auto[1]

402441

1

T3

4

T17

4589

T36

3689

auto[0]

auto[1]

auto[1]

auto[0]

436134

1

T3

6

T17

3644

T36

768

auto[0]

auto[1]

auto[1]

auto[1]

434475

1

T3

9

T17

2432

T19

174

auto[1]

auto[0]

auto[0]

auto[0]

255415

1

T17

42

T36

1105

T25

9

auto[1]

auto[0]

auto[0]

auto[1]

263455

1

T17

18

T36

121

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

3978834

1

T1

26465

T2

23943

T17

39

auto[1]

auto[0]

auto[1]

auto[1]

270520

1

T17

59

T36

114

T25

20

auto[1]

auto[1]

auto[0]

auto[0]

447997

1

T17

5

T36

153

T38

1706

auto[1]

auto[1]

auto[0]

auto[1]

466723

1

T17

4

T36

1895

T37

123

auto[1]

auto[1]

auto[1]

auto[0]

461926

1

T17

14

T36

393

T38

206

auto[1]

auto[1]

auto[1]

auto[1]

468260

1

T17

7

T19

1

T36

821

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

469592

1

T3

5

T17

7169

T36

3051

auto[0]

auto[0]

auto[0]

auto[1]

483275

1

T3

6

T17

2428

T36

318

auto[0]

auto[0]

auto[1]

auto[0]

4988421

1

T1

37406

T2

37302

T3

4

auto[0]

auto[0]

auto[1]

auto[1]

494311

1

T3

6

T17

1083

T36

345

auto[0]

auto[1]

auto[0]

auto[0]

803603

1

T3

7

T17

5744

T36

469

auto[0]

auto[1]

auto[0]

auto[1]

853456

1

T3

4

T17

2267

T36

5584

auto[0]

auto[1]

auto[1]

auto[0]

878239

1

T3

5

T17

2760

T36

1161

auto[0]

auto[1]

auto[1]

auto[1]

889178

1

T3

8

T17

2317

T19

175

auto[1]

auto[0]

auto[0]

auto[0]

18276

1

T3

1

T17

533

T15

56

auto[1]

auto[0]

auto[0]

auto[1]

12306

1

T17

54

T15

482

T4

314

auto[1]

auto[0]

auto[1]

auto[0]

11235

1

T3

1

T17

77

T15

768

auto[1]

auto[0]

auto[1]

auto[1]

16474

1

T17

16

T18

1

T15

47

auto[1]

auto[1]

auto[0]

auto[0]

12356

1

T3

1

T17

352

T15

550

auto[1]

auto[1]

auto[0]

auto[1]

15708

1

T17

2326

T15

52

T4

272

auto[1]

auto[1]

auto[1]

auto[0]

19821

1

T3

1

T17

898

T15

10

auto[1]

auto[1]

auto[1]

auto[1]

13557

1

T3

1

T17

122

T15

126

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	273691	1			T3	1		T17	575		T36	1105
fifo_depth[0]	auto[0]	auto[0]	auto[1]	275761	1			T17	72		T36	121		T37	1
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3990069	1			T1	26465		T2	23943		T3	1
fifo_depth[0]	auto[0]	auto[1]	auto[1]	286994	1			T17	75		T36	114		T25	20
fifo_depth[0]	auto[1]	auto[0]	auto[0]	460353	1			T3	1		T17	357		T36	153
fifo_depth[0]	auto[1]	auto[0]	auto[1]	482431	1			T17	2330		T36	1895		T37	123
fifo_depth[0]	auto[1]	auto[1]	auto[0]	481747	1			T3	1		T17	912		T36	393
fifo_depth[0]	auto[1]	auto[1]	auto[1]	481817	1			T3	1		T17	129		T19	1
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19939	1			T17	14		T36	224		T26	55
fifo_depth[1]	auto[0]	auto[0]	auto[1]	21988	1			T17	11		T36	24		T26	6
fifo_depth[1]	auto[0]	auto[1]	auto[0]	232526	1			T1	2528		T2	2445		T17	8
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20554	1			T17	8		T36	22		T26	61
fifo_depth[1]	auto[1]	auto[0]	auto[0]	43251	1			T17	1		T36	35		T38	360
fifo_depth[1]	auto[1]	auto[0]	auto[1]	45572	1			T17	1		T36	420		T37	21
fifo_depth[1]	auto[1]	auto[1]	auto[0]	47136	1			T17	4		T36	97		T38	43
fifo_depth[1]	auto[1]	auto[1]	auto[1]	47344	1			T36	179		T38	677		T25	6
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16806	1			T17	18		T36	223		T26	43
fifo_depth[2]	auto[0]	auto[0]	auto[1]	18385	1			T17	40		T36	20		T26	5
fifo_depth[2]	auto[0]	auto[1]	auto[0]	168767	1			T1	2351		T2	2394		T17	42
fifo_depth[2]	auto[0]	auto[1]	auto[1]	17087	1			T17	9		T36	23		T26	30
fifo_depth[2]	auto[1]	auto[0]	auto[0]	37214	1			T17	2		T36	33		T38	341
fifo_depth[2]	auto[1]	auto[0]	auto[1]	39335	1			T17	1		T36	414		T37	22
fifo_depth[2]	auto[1]	auto[1]	auto[0]	41656	1			T17	11		T36	83		T38	46
fifo_depth[2]	auto[1]	auto[1]	auto[1]	40872	1			T17	1		T36	175		T38	614
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13017	1			T17	20		T36	211		T26	12
fifo_depth[3]	auto[0]	auto[0]	auto[1]	14823	1			T17	44		T36	17		T26	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	122625	1			T1	1794		T2	2009		T17	46
fifo_depth[3]	auto[0]	auto[1]	auto[1]	13132	1			T17	7		T36	19		T26	11
fifo_depth[3]	auto[1]	auto[0]	auto[0]	30444	1			T17	1		T36	32		T38	362
fifo_depth[3]	auto[1]	auto[0]	auto[1]	32615	1			T36	411		T37	33		T38	556
fifo_depth[3]	auto[1]	auto[1]	auto[0]	35370	1			T17	16		T36	94		T38	48
fifo_depth[3]	auto[1]	auto[1]	auto[1]	34412	1			T17	2		T36	172		T38	675
fifo_depth[4]	auto[0]	auto[0]	auto[0]	12002	1			T17	127		T36	222		T26	4
fifo_depth[4]	auto[0]	auto[0]	auto[1]	13142	1			T17	41		T36	28		T27	10
fifo_depth[4]	auto[0]	auto[1]	auto[0]	89096	1			T1	1069		T2	1512		T17	47
fifo_depth[4]	auto[0]	auto[1]	auto[1]	12473	1			T17	5		T36	25		T26	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	28193	1			T36	37		T38	370		T26	5
fifo_depth[4]	auto[1]	auto[0]	auto[1]	29947	1			T17	5		T36	413		T37	23
fifo_depth[4]	auto[1]	auto[1]	auto[0]	32836	1			T17	44		T36	78		T38	52
fifo_depth[4]	auto[1]	auto[1]	auto[1]	31573	1			T17	1		T36	166		T38	662
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10543	1			T17	35		T36	214		T91	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11589	1			T17	43		T36	20		T27	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	72795	1			T1	792		T2	1236		T17	52
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10424	1			T17	7		T36	26		T26	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	25515	1			T17	3		T36	42		T38	350
fifo_depth[5]	auto[1]	auto[0]	auto[1]	27502	1			T17	2		T36	392		T37	26
fifo_depth[5]	auto[1]	auto[1]	auto[0]	30210	1			T17	48		T36	77		T38	47
fifo_depth[5]	auto[1]	auto[1]	auto[1]	29850	1			T36	161		T38	677		T26	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10184	1			T17	136		T36	202		T15	160
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11509	1			T17	40		T36	26		T28	26
fifo_depth[6]	auto[0]	auto[1]	auto[0]	63840	1			T1	697		T2	1143		T17	45
fifo_depth[6]	auto[0]	auto[1]	auto[1]	10594	1			T17	6		T36	20		T91	2
fifo_depth[6]	auto[1]	auto[0]	auto[0]	24722	1			T17	13		T36	29		T38	356
fifo_depth[6]	auto[1]	auto[0]	auto[1]	26646	1			T17	1		T36	380		T37	24
fifo_depth[6]	auto[1]	auto[1]	auto[0]	29367	1			T17	40		T36	79		T38	44
fifo_depth[6]	auto[1]	auto[1]	auto[1]	28822	1			T17	10		T36	185		T38	633
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9346	1			T17	31		T36	192		T27	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10439	1			T17	43		T36	16		T28	26
fifo_depth[7]	auto[0]	auto[1]	auto[0]	52041	1			T1	591		T2	887		T17	51
fifo_depth[7]	auto[0]	auto[1]	auto[1]	9441	1			T17	6		T36	28		T15	21
fifo_depth[7]	auto[1]	auto[0]	auto[0]	22639	1			T17	3		T36	27		T38	342
fifo_depth[7]	auto[1]	auto[0]	auto[1]	24894	1			T17	2		T36	349		T37	36
fifo_depth[7]	auto[1]	auto[1]	auto[0]	27188	1			T17	48		T36	76		T38	36
fifo_depth[7]	auto[1]	auto[1]	auto[1]	26885	1			T17	8		T36	157		T38	587
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9675	1			T17	395		T36	174		T15	226
fifo_depth[8]	auto[0]	auto[0]	auto[1]	10681	1			T17	42		T36	18		T28	32
fifo_depth[8]	auto[0]	auto[1]	auto[0]	42823	1			T1	464		T2	654		T17	174
fifo_depth[8]	auto[0]	auto[1]	auto[1]	9860	1			T17	8		T36	26		T15	172
fifo_depth[8]	auto[1]	auto[0]	auto[0]	21403	1			T17	45		T36	27		T38	288
fifo_depth[8]	auto[1]	auto[0]	auto[1]	23043	1			T17	4		T36	316		T37	19
fifo_depth[8]	auto[1]	auto[1]	auto[0]	24494	1			T17	43		T36	69		T38	36
fifo_depth[8]	auto[1]	auto[1]	auto[1]	24552	1			T17	45		T36	137		T38	516
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6233	1			T17	31		T36	130		T15	93
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7294	1			T17	45		T36	13		T28	17
fifo_depth[9]	auto[0]	auto[1]	auto[0]	28234	1			T1	308		T2	446		T17	51
fifo_depth[9]	auto[0]	auto[1]	auto[1]	6412	1			T17	6		T36	17		T15	27
fifo_depth[9]	auto[1]	auto[0]	auto[0]	14436	1			T17	38		T36	20		T38	215
fifo_depth[9]	auto[1]	auto[0]	auto[1]	16448	1			T17	7		T36	254		T37	15
fifo_depth[9]	auto[1]	auto[1]	auto[0]	18087	1			T17	48		T36	55		T38	30
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17726	1			T17	77		T36	107		T38	360
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5294	1			T17	222		T36	83		T15	133
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5933	1			T17	43		T36	9		T28	15
fifo_depth[10]	auto[0]	auto[1]	auto[0]	19994	1			T1	170		T2	306		T17	43
fifo_depth[10]	auto[0]	auto[1]	auto[1]	6092	1			T17	14		T36	11		T15	15
fifo_depth[10]	auto[1]	auto[0]	auto[0]	10571	1			T17	42		T36	14		T38	130
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12238	1			T17	13		T36	155		T37	16
fifo_depth[10]	auto[1]	auto[1]	auto[0]	13577	1			T17	46		T36	28		T38	21
fifo_depth[10]	auto[1]	auto[1]	auto[1]	13398	1			T17	42		T36	67		T38	270
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3171	1			T17	39		T36	40		T15	38
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3981	1			T17	48		T36	5		T28	4
fifo_depth[11]	auto[0]	auto[1]	auto[0]	12057	1			T1	100		T2	179		T17	52
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3996	1			T17	18		T36	9		T15	31
fifo_depth[11]	auto[1]	auto[0]	auto[0]	6514	1			T17	48		T36	8		T38	62
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7821	1			T17	16		T36	86		T37	8
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8700	1			T17	43		T36	19		T38	9
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8854	1			T17	41		T19	1		T36	39
fifo_depth[12]	auto[0]	auto[0]	auto[0]	4456	1			T17	383		T36	21		T15	84
fifo_depth[12]	auto[0]	auto[0]	auto[1]	4580	1			T17	50		T36	1		T28	3
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10441	1			T1	50		T2	83		T17	165
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5754	1			T17	77		T36	4		T15	209
fifo_depth[12]	auto[1]	auto[0]	auto[0]	6399	1			T17	66		T36	7		T38	34
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7644	1			T17	137		T36	56		T37	6
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7042	1			T17	48		T36	8		T38	8
fifo_depth[12]	auto[1]	auto[1]	auto[1]	7997	1			T17	44		T36	22		T38	55
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2060	1			T17	54		T36	6		T15	20
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2572	1			T17	55		T28	1		T15	24
fifo_depth[13]	auto[0]	auto[1]	auto[0]	5066	1			T1	12		T2	41		T17	62
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3460	1			T17	80		T36	1		T15	73
fifo_depth[13]	auto[1]	auto[0]	auto[0]	2994	1			T17	54		T36	4		T38	21
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4165	1			T17	17		T36	21		T37	2
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4082	1			T17	41		T36	5		T38	11
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4488	1			T17	39		T36	13		T38	27
fifo_depth[14]	auto[0]	auto[0]	auto[0]	3812	1			T17	236		T36	2		T15	109
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3477	1			T17	120		T28	2		T15	149
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5932	1			T1	10		T2	18		T17	66
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5133	1			T17	82		T15	127		T4	93
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3467	1			T17	61		T38	10		T28	2
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4649	1			T17	101		T36	20		T37	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	4464	1			T17	48		T38	3		T90	6
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4879	1			T17	63		T36	2		T38	17
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2382	1			T17	55		T36	1		T15	11
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2684	1			T17	100		T15	24		T4	168
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3625	1			T1	4		T2	6		T17	44
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3797	1			T17	76		T15	169		T4	82
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2287	1			T17	54		T36	1		T38	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3170	1			T17	19		T36	2		T37	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3220	1			T17	41		T15	10		T4	279
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3495	1			T17	77		T36	1		T38	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	10725	1			T17	539		T36	1		T15	76
fifo_depth[16]	auto[0]	auto[0]	auto[1]	13161	1			T17	103		T15	399		T4	197
fifo_depth[16]	auto[0]	auto[1]	auto[0]	13801	1			T1	1		T17	258		T15	7
fifo_depth[16]	auto[0]	auto[1]	auto[1]	11776	1			T17	49		T15	259		T4	55
fifo_depth[16]	auto[1]	auto[0]	auto[0]	11500	1			T17	285		T38	1		T15	282
fifo_depth[16]	auto[1]	auto[0]	auto[1]	12221	1			T17	359		T38	2		T15	437
fifo_depth[16]	auto[1]	auto[1]	auto[0]	10095	1			T17	54		T15	44		T4	652
fifo_depth[16]	auto[1]	auto[1]	auto[1]	11362	1			T17	161		T19	1		T36	1