Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14920631	1			T1	88510		T2	73560		T3	1259
all_pins[1]	14920631	1			T1	88510		T2	73560		T3	1259
all_pins[2]	14920631	1			T1	88510		T2	73560		T3	1259

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42421904	1			T1	252474		T2	211404		T3	3705
values[0x1]	2339989	1			T1	13056		T2	9276		T3	72
transitions[0x0=>0x1]	2339802	1			T1	13056		T2	9276		T3	72
transitions[0x1=>0x0]	2339813	1			T1	13056		T2	9276		T3	72

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14867976	1			T1	88316		T2	73366		T3	1187
all_pins[0]	values[0x1]	52655	1			T1	194		T2	194		T3	72
all_pins[0]	transitions[0x0=>0x1]	52595	1			T1	194		T2	194		T3	72
all_pins[0]	transitions[0x1=>0x0]	2286580	1			T1	12862		T2	9082		T16	11709
all_pins[1]	values[0x0]	14919926	1			T1	88510		T2	73560		T3	1259
all_pins[1]	values[0x1]	705	1			T17	2		T15	3		T4	19
all_pins[1]	transitions[0x0=>0x1]	629	1			T17	2		T15	3		T4	17
all_pins[1]	transitions[0x1=>0x0]	52579	1			T1	194		T2	194		T3	72
all_pins[2]	values[0x0]	12634002	1			T1	75648		T2	64478		T3	1259
all_pins[2]	values[0x1]	2286629	1			T1	12862		T2	9082		T16	11709
all_pins[2]	transitions[0x0=>0x1]	2286578	1			T1	12862		T2	9082		T16	11709
all_pins[2]	transitions[0x1=>0x0]	654	1			T17	2		T15	2		T4	17