Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1036 1 T15 7 T4 17 T20 7
all_values[1] 1036 1 T15 7 T4 17 T20 7
all_values[2] 1036 1 T15 7 T4 17 T20 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1542 1 T15 9 T4 19 T20 8
auto[1] 1566 1 T15 12 T4 32 T20 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1056 1 T15 8 T4 15 T20 13
auto[1] 2052 1 T15 13 T4 36 T20 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1710 1 T15 14 T4 26 T20 14
auto[1] 1398 1 T15 7 T4 25 T20 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 176 1 T15 3 T4 3 T20 1
all_values[0] auto[0] auto[0] auto[1] 104 1 T15 1 T4 2 T5 3
all_values[0] auto[0] auto[1] auto[0] 194 1 T15 1 T4 4 T20 2
all_values[0] auto[0] auto[1] auto[1] 100 1 T4 2 T5 2 T14 1
all_values[0] auto[1] auto[0] auto[1] 219 1 T15 1 T4 2 T20 2
all_values[0] auto[1] auto[1] auto[1] 243 1 T15 1 T4 4 T20 2
all_values[1] auto[0] auto[0] auto[0] 154 1 T15 1 T4 2 T20 1
all_values[1] auto[0] auto[0] auto[1] 118 1 T4 1 T5 2 T6 1
all_values[1] auto[0] auto[1] auto[0] 148 1 T15 2 T4 1 T20 3
all_values[1] auto[0] auto[1] auto[1] 145 1 T15 2 T4 4 T20 1
all_values[1] auto[1] auto[0] auto[1] 227 1 T4 3 T20 2 T5 3
all_values[1] auto[1] auto[1] auto[1] 244 1 T15 2 T4 6 T5 8
all_values[2] auto[0] auto[0] auto[0] 188 1 T15 1 T4 2 T20 2
all_values[2] auto[0] auto[0] auto[1] 103 1 T15 1 T5 3 T14 4
all_values[2] auto[0] auto[1] auto[0] 196 1 T4 3 T20 4 T5 10
all_values[2] auto[0] auto[1] auto[1] 84 1 T15 2 T4 2 T5 2
all_values[2] auto[1] auto[0] auto[1] 253 1 T15 1 T4 4 T5 7
all_values[2] auto[1] auto[1] auto[1] 212 1 T15 2 T4 6 T20 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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