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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.92 92.47 85.11 100.00 76.32 85.98 99.49 69.08


Total test records in report: 741
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T529 /workspace/coverage/default/3.hmac_back_pressure.1219114762 Apr 23 02:40:37 PM PDT 24 Apr 23 02:41:18 PM PDT 24 13799894549 ps
T530 /workspace/coverage/default/31.hmac_test_hmac_vectors.3416919897 Apr 23 02:42:07 PM PDT 24 Apr 23 02:42:09 PM PDT 24 52627556 ps
T78 /workspace/coverage/default/10.hmac_stress_all.2501659824 Apr 23 02:40:59 PM PDT 24 Apr 23 03:11:11 PM PDT 24 502099125640 ps
T531 /workspace/coverage/default/2.hmac_datapath_stress.917914849 Apr 23 02:40:28 PM PDT 24 Apr 23 02:40:37 PM PDT 24 328056933 ps
T532 /workspace/coverage/default/27.hmac_error.365228687 Apr 23 02:41:46 PM PDT 24 Apr 23 02:45:25 PM PDT 24 8160301842 ps
T533 /workspace/coverage/default/3.hmac_test_hmac_vectors.1923083074 Apr 23 02:40:32 PM PDT 24 Apr 23 02:40:34 PM PDT 24 106243844 ps
T534 /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.2194864594 Apr 23 02:43:16 PM PDT 24 Apr 23 03:19:01 PM PDT 24 91100286422 ps
T535 /workspace/coverage/default/39.hmac_burst_wr.2660838352 Apr 23 02:42:27 PM PDT 24 Apr 23 02:43:07 PM PDT 24 3710440109 ps
T536 /workspace/coverage/default/49.hmac_error.3323708571 Apr 23 02:43:12 PM PDT 24 Apr 23 02:46:58 PM PDT 24 13269290024 ps
T537 /workspace/coverage/default/12.hmac_burst_wr.3508387326 Apr 23 02:41:00 PM PDT 24 Apr 23 02:41:28 PM PDT 24 12119476455 ps
T538 /workspace/coverage/default/12.hmac_test_sha_vectors.4276536201 Apr 23 02:40:59 PM PDT 24 Apr 23 02:47:46 PM PDT 24 7774575567 ps
T539 /workspace/coverage/default/0.hmac_test_hmac_vectors.1924390819 Apr 23 02:40:21 PM PDT 24 Apr 23 02:40:23 PM PDT 24 43129528 ps
T540 /workspace/coverage/default/5.hmac_test_sha_vectors.2640220045 Apr 23 02:40:42 PM PDT 24 Apr 23 02:48:12 PM PDT 24 154482599569 ps
T541 /workspace/coverage/default/40.hmac_stress_all.1542634025 Apr 23 02:42:33 PM PDT 24 Apr 23 03:06:27 PM PDT 24 77444737562 ps
T101 /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.3366698488 Apr 23 02:42:34 PM PDT 24 Apr 23 02:53:41 PM PDT 24 43584065585 ps
T542 /workspace/coverage/default/39.hmac_long_msg.1543409547 Apr 23 02:42:32 PM PDT 24 Apr 23 02:43:56 PM PDT 24 22466593531 ps
T543 /workspace/coverage/default/43.hmac_wipe_secret.3536741377 Apr 23 02:42:47 PM PDT 24 Apr 23 02:43:44 PM PDT 24 6484766320 ps
T544 /workspace/coverage/default/5.hmac_datapath_stress.364486501 Apr 23 02:40:41 PM PDT 24 Apr 23 02:43:30 PM PDT 24 31864858571 ps
T545 /workspace/coverage/default/25.hmac_wipe_secret.3646009452 Apr 23 02:41:37 PM PDT 24 Apr 23 02:41:57 PM PDT 24 5435987974 ps
T546 /workspace/coverage/default/10.hmac_test_hmac_vectors.3498296237 Apr 23 02:40:55 PM PDT 24 Apr 23 02:40:56 PM PDT 24 54628902 ps
T547 /workspace/coverage/default/10.hmac_test_sha_vectors.3123217475 Apr 23 02:40:57 PM PDT 24 Apr 23 02:48:07 PM PDT 24 30827811506 ps
T548 /workspace/coverage/default/11.hmac_back_pressure.2919237854 Apr 23 02:40:58 PM PDT 24 Apr 23 02:41:37 PM PDT 24 4685242988 ps
T549 /workspace/coverage/default/15.hmac_long_msg.16581648 Apr 23 02:41:06 PM PDT 24 Apr 23 02:41:29 PM PDT 24 405381190 ps
T550 /workspace/coverage/default/14.hmac_test_sha_vectors.1668266036 Apr 23 02:41:05 PM PDT 24 Apr 23 02:48:59 PM PDT 24 17140212187 ps
T551 /workspace/coverage/default/15.hmac_burst_wr.3047223393 Apr 23 02:41:10 PM PDT 24 Apr 23 02:42:15 PM PDT 24 1377204722 ps
T552 /workspace/coverage/default/35.hmac_back_pressure.1092767900 Apr 23 02:42:19 PM PDT 24 Apr 23 02:42:47 PM PDT 24 2360390258 ps
T553 /workspace/coverage/default/34.hmac_datapath_stress.4044778421 Apr 23 02:42:12 PM PDT 24 Apr 23 02:42:17 PM PDT 24 372684360 ps
T554 /workspace/coverage/default/6.hmac_test_hmac_vectors.3193916422 Apr 23 02:40:45 PM PDT 24 Apr 23 02:40:47 PM PDT 24 325143171 ps
T555 /workspace/coverage/default/1.hmac_stress_all.1345167246 Apr 23 02:40:29 PM PDT 24 Apr 23 03:13:09 PM PDT 24 101515344114 ps
T556 /workspace/coverage/default/12.hmac_long_msg.525529488 Apr 23 02:40:59 PM PDT 24 Apr 23 02:42:07 PM PDT 24 16496703396 ps
T557 /workspace/coverage/default/36.hmac_burst_wr.2050208353 Apr 23 02:42:22 PM PDT 24 Apr 23 02:42:51 PM PDT 24 629761257 ps
T558 /workspace/coverage/default/44.hmac_error.3215606716 Apr 23 02:42:49 PM PDT 24 Apr 23 02:43:37 PM PDT 24 927341500 ps
T559 /workspace/coverage/default/32.hmac_error.149162742 Apr 23 02:42:12 PM PDT 24 Apr 23 02:43:37 PM PDT 24 18616002059 ps
T560 /workspace/coverage/default/24.hmac_long_msg.1091929468 Apr 23 02:41:38 PM PDT 24 Apr 23 02:42:11 PM PDT 24 2128755740 ps
T561 /workspace/coverage/default/43.hmac_datapath_stress.1549721436 Apr 23 02:42:42 PM PDT 24 Apr 23 02:45:14 PM PDT 24 2767704331 ps
T562 /workspace/coverage/default/32.hmac_burst_wr.1107411356 Apr 23 02:42:05 PM PDT 24 Apr 23 02:42:45 PM PDT 24 766311261 ps
T563 /workspace/coverage/default/49.hmac_long_msg.2092702209 Apr 23 02:43:06 PM PDT 24 Apr 23 02:43:48 PM PDT 24 1432980910 ps
T564 /workspace/coverage/default/32.hmac_stress_all.2380804156 Apr 23 02:42:08 PM PDT 24 Apr 23 02:54:15 PM PDT 24 108638567760 ps
T565 /workspace/coverage/default/30.hmac_smoke.2765133223 Apr 23 02:41:55 PM PDT 24 Apr 23 02:41:57 PM PDT 24 116296410 ps
T566 /workspace/coverage/default/35.hmac_stress_all.791400467 Apr 23 02:42:19 PM PDT 24 Apr 23 02:53:48 PM PDT 24 57922598285 ps
T567 /workspace/coverage/default/36.hmac_long_msg.118228833 Apr 23 02:42:21 PM PDT 24 Apr 23 02:43:25 PM PDT 24 3190246699 ps
T568 /workspace/coverage/default/26.hmac_alert_test.2079025919 Apr 23 02:41:45 PM PDT 24 Apr 23 02:41:46 PM PDT 24 11915536 ps
T569 /workspace/coverage/default/31.hmac_datapath_stress.615573972 Apr 23 02:42:04 PM PDT 24 Apr 23 02:42:05 PM PDT 24 22491605 ps
T570 /workspace/coverage/default/2.hmac_wipe_secret.1234622786 Apr 23 02:40:31 PM PDT 24 Apr 23 02:41:17 PM PDT 24 4975591291 ps
T571 /workspace/coverage/default/45.hmac_stress_all.715024401 Apr 23 02:42:55 PM PDT 24 Apr 23 03:08:44 PM PDT 24 792067649417 ps
T572 /workspace/coverage/default/6.hmac_stress_all.2952312839 Apr 23 02:40:44 PM PDT 24 Apr 23 03:10:52 PM PDT 24 396786912283 ps
T573 /workspace/coverage/default/8.hmac_stress_all.1969363671 Apr 23 02:40:53 PM PDT 24 Apr 23 02:53:08 PM PDT 24 83241526416 ps
T574 /workspace/coverage/default/46.hmac_back_pressure.1280538772 Apr 23 02:42:58 PM PDT 24 Apr 23 02:43:19 PM PDT 24 1227678295 ps
T575 /workspace/coverage/default/37.hmac_alert_test.2396764604 Apr 23 02:42:26 PM PDT 24 Apr 23 02:42:27 PM PDT 24 18985175 ps
T576 /workspace/coverage/default/29.hmac_error.3984856796 Apr 23 02:41:50 PM PDT 24 Apr 23 02:43:06 PM PDT 24 2656748004 ps
T577 /workspace/coverage/default/12.hmac_stress_all.3637643066 Apr 23 02:41:00 PM PDT 24 Apr 23 03:12:55 PM PDT 24 108644177685 ps
T578 /workspace/coverage/default/42.hmac_stress_all.1155791493 Apr 23 02:42:39 PM PDT 24 Apr 23 02:43:23 PM PDT 24 5016302864 ps
T579 /workspace/coverage/default/41.hmac_burst_wr.2010231961 Apr 23 02:42:35 PM PDT 24 Apr 23 02:42:56 PM PDT 24 2037022064 ps
T580 /workspace/coverage/default/6.hmac_wipe_secret.111373787 Apr 23 02:40:54 PM PDT 24 Apr 23 02:41:42 PM PDT 24 4426745027 ps
T581 /workspace/coverage/default/4.hmac_burst_wr.2037099980 Apr 23 02:40:36 PM PDT 24 Apr 23 02:40:50 PM PDT 24 876209037 ps
T582 /workspace/coverage/default/49.hmac_wipe_secret.4149642364 Apr 23 02:43:09 PM PDT 24 Apr 23 02:43:23 PM PDT 24 3104413885 ps
T583 /workspace/coverage/default/46.hmac_burst_wr.1854378793 Apr 23 02:42:55 PM PDT 24 Apr 23 02:43:15 PM PDT 24 388454586 ps
T584 /workspace/coverage/default/13.hmac_test_hmac_vectors.853114270 Apr 23 02:41:02 PM PDT 24 Apr 23 02:41:03 PM PDT 24 83424948 ps
T585 /workspace/coverage/default/18.hmac_test_hmac_vectors.219134664 Apr 23 02:41:16 PM PDT 24 Apr 23 02:41:18 PM PDT 24 749623745 ps
T586 /workspace/coverage/default/14.hmac_back_pressure.222234072 Apr 23 02:41:04 PM PDT 24 Apr 23 02:41:38 PM PDT 24 964376399 ps
T587 /workspace/coverage/default/35.hmac_test_hmac_vectors.885721647 Apr 23 02:42:19 PM PDT 24 Apr 23 02:42:21 PM PDT 24 152448749 ps
T588 /workspace/coverage/default/26.hmac_test_hmac_vectors.1058710206 Apr 23 02:41:45 PM PDT 24 Apr 23 02:41:47 PM PDT 24 62967289 ps
T589 /workspace/coverage/default/19.hmac_wipe_secret.2231380406 Apr 23 02:41:22 PM PDT 24 Apr 23 02:42:37 PM PDT 24 4046562233 ps
T590 /workspace/coverage/default/48.hmac_smoke.2495313349 Apr 23 02:43:04 PM PDT 24 Apr 23 02:43:11 PM PDT 24 2101922459 ps
T591 /workspace/coverage/default/37.hmac_burst_wr.3791397872 Apr 23 02:42:25 PM PDT 24 Apr 23 02:42:31 PM PDT 24 559459280 ps
T592 /workspace/coverage/default/19.hmac_alert_test.3132251282 Apr 23 02:41:23 PM PDT 24 Apr 23 02:41:23 PM PDT 24 31964200 ps
T593 /workspace/coverage/default/27.hmac_smoke.1737828060 Apr 23 02:41:45 PM PDT 24 Apr 23 02:41:47 PM PDT 24 188783283 ps
T594 /workspace/coverage/default/22.hmac_long_msg.2810632248 Apr 23 02:41:31 PM PDT 24 Apr 23 02:43:29 PM PDT 24 6127011408 ps
T55 /workspace/coverage/default/30.hmac_error.1894607959 Apr 23 02:41:59 PM PDT 24 Apr 23 02:43:07 PM PDT 24 5014601351 ps
T595 /workspace/coverage/default/28.hmac_wipe_secret.1084251636 Apr 23 02:41:51 PM PDT 24 Apr 23 02:43:29 PM PDT 24 29690208459 ps
T596 /workspace/coverage/default/23.hmac_test_sha_vectors.150114056 Apr 23 02:41:36 PM PDT 24 Apr 23 02:49:19 PM PDT 24 258114232578 ps
T597 /workspace/coverage/default/4.hmac_back_pressure.1521956838 Apr 23 02:40:35 PM PDT 24 Apr 23 02:41:09 PM PDT 24 1041967354 ps
T598 /workspace/coverage/default/15.hmac_smoke.917738618 Apr 23 02:41:09 PM PDT 24 Apr 23 02:41:14 PM PDT 24 260129899 ps
T599 /workspace/coverage/default/33.hmac_test_hmac_vectors.4191737133 Apr 23 02:42:14 PM PDT 24 Apr 23 02:42:15 PM PDT 24 57582177 ps
T600 /workspace/coverage/default/4.hmac_long_msg.1411583845 Apr 23 02:40:35 PM PDT 24 Apr 23 02:40:41 PM PDT 24 114448602 ps
T601 /workspace/coverage/default/2.hmac_stress_all.225674744 Apr 23 02:40:31 PM PDT 24 Apr 23 03:07:47 PM PDT 24 336542107318 ps
T79 /workspace/coverage/cover_reg_top/30.hmac_intr_test.302384092 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 166468808 ps
T62 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1711277181 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:40 PM PDT 24 60271946 ps
T602 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1459899148 Apr 23 02:34:35 PM PDT 24 Apr 23 02:34:40 PM PDT 24 273005516 ps
T603 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1358055470 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 123670833 ps
T59 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3838516436 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:55 PM PDT 24 119710141 ps
T63 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.921865428 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:08 PM PDT 24 117470976 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1304905312 Apr 23 02:34:45 PM PDT 24 Apr 23 02:34:47 PM PDT 24 14935503 ps
T60 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4093611891 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:54 PM PDT 24 199890514 ps
T61 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2651644030 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:43 PM PDT 24 1220001565 ps
T605 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1960870465 Apr 23 02:34:32 PM PDT 24 Apr 23 02:34:37 PM PDT 24 170381304 ps
T606 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3793053183 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 13929425 ps
T607 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1166720740 Apr 23 02:34:33 PM PDT 24 Apr 23 02:34:35 PM PDT 24 24888700 ps
T608 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2507761116 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 35829447 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.947063117 Apr 23 02:34:35 PM PDT 24 Apr 23 02:34:40 PM PDT 24 205271701 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1151629971 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:57 PM PDT 24 127181590 ps
T80 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3881859554 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:53 PM PDT 24 243630579 ps
T611 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3536207888 Apr 23 02:35:05 PM PDT 24 Apr 23 02:35:06 PM PDT 24 32044716 ps
T612 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2840278684 Apr 23 02:34:58 PM PDT 24 Apr 23 02:35:00 PM PDT 24 25665819 ps
T102 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.837401732 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:54 PM PDT 24 22106521 ps
T613 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1321049068 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:58 PM PDT 24 279244173 ps
T614 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3305228004 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:53 PM PDT 24 318857317 ps
T615 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.270856069 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:46 PM PDT 24 74598042 ps
T616 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3660182734 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:09 PM PDT 24 88626501 ps
T103 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.208845239 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:42 PM PDT 24 184846669 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3479780817 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:41 PM PDT 24 27001221 ps
T618 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1060000455 Apr 23 02:34:58 PM PDT 24 Apr 23 02:35:00 PM PDT 24 42029655 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.517769238 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:40 PM PDT 24 39266377 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3197153817 Apr 23 02:34:43 PM PDT 24 Apr 23 02:34:46 PM PDT 24 303784614 ps
T113 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3775571469 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:45 PM PDT 24 238709908 ps
T105 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2126079852 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 180971945 ps
T620 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3797110640 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:43 PM PDT 24 163936826 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_intr_test.896784984 Apr 23 02:34:36 PM PDT 24 Apr 23 02:34:38 PM PDT 24 27424082 ps
T622 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.402099162 Apr 23 02:34:45 PM PDT 24 Apr 23 02:34:49 PM PDT 24 251914057 ps
T623 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3628020107 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:58 PM PDT 24 446235204 ps
T624 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1376548225 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:57 PM PDT 24 1638360183 ps
T625 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3210045086 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:59 PM PDT 24 396705964 ps
T626 /workspace/coverage/cover_reg_top/25.hmac_intr_test.781752710 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 14856810 ps
T627 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.514248632 Apr 23 02:34:42 PM PDT 24 Apr 23 02:34:46 PM PDT 24 178693188 ps
T628 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3029120376 Apr 23 02:34:56 PM PDT 24 Apr 23 02:34:58 PM PDT 24 12932958 ps
T629 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.396936381 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:44 PM PDT 24 155387897 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2529126587 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:44 PM PDT 24 559050528 ps
T106 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.972867252 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:48 PM PDT 24 111505847 ps
T112 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3382662181 Apr 23 02:34:35 PM PDT 24 Apr 23 02:34:37 PM PDT 24 27939663 ps
T630 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2617041234 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:54 PM PDT 24 46653549 ps
T631 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3756516397 Apr 23 02:35:01 PM PDT 24 Apr 23 02:35:03 PM PDT 24 14349947 ps
T632 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3753020932 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:42 PM PDT 24 67531103 ps
T633 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3175694743 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:44 PM PDT 24 124297176 ps
T107 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1991508714 Apr 23 02:34:46 PM PDT 24 Apr 23 02:34:48 PM PDT 24 413067220 ps
T634 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3472727391 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:45 PM PDT 24 652813361 ps
T635 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1630125504 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 20082039 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.456301817 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:59 PM PDT 24 545935009 ps
T637 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4209205347 Apr 23 02:34:35 PM PDT 24 Apr 23 02:34:37 PM PDT 24 18917350 ps
T638 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3785970006 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 14389405 ps
T108 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3293947432 Apr 23 02:34:34 PM PDT 24 Apr 23 02:34:43 PM PDT 24 159072252 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_intr_test.614762731 Apr 23 02:34:49 PM PDT 24 Apr 23 02:34:50 PM PDT 24 31186320 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2517343970 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:42 PM PDT 24 33421820 ps
T641 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.448217976 Apr 23 02:34:43 PM PDT 24 Apr 23 02:34:46 PM PDT 24 31875972 ps
T642 /workspace/coverage/cover_reg_top/34.hmac_intr_test.435688642 Apr 23 02:34:59 PM PDT 24 Apr 23 02:35:01 PM PDT 24 29216270 ps
T116 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1631929845 Apr 23 02:34:53 PM PDT 24 Apr 23 02:35:00 PM PDT 24 1597868759 ps
T643 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1783663598 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:55 PM PDT 24 92492514 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1976960026 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:43 PM PDT 24 216838257 ps
T644 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1773797762 Apr 23 02:34:49 PM PDT 24 Apr 23 02:34:53 PM PDT 24 206439275 ps
T110 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1255316575 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 26183676 ps
T111 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.568970131 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 25364649 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3812205496 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:54 PM PDT 24 27197945 ps
T646 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.577953074 Apr 23 02:34:43 PM PDT 24 Apr 23 02:34:45 PM PDT 24 172100025 ps
T647 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2331247649 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:57 PM PDT 24 343497398 ps
T648 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4048071273 Apr 23 02:34:55 PM PDT 24 Apr 23 02:35:00 PM PDT 24 250804471 ps
T649 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3184983534 Apr 23 02:34:42 PM PDT 24 Apr 23 02:34:44 PM PDT 24 63676959 ps
T650 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2909933714 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:56 PM PDT 24 439390235 ps
T651 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.26256551 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:47 PM PDT 24 94596536 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2284785606 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:50 PM PDT 24 74581419 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.845880749 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:41 PM PDT 24 82866972 ps
T654 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1210309404 Apr 23 02:34:51 PM PDT 24 Apr 23 02:38:20 PM PDT 24 159170863082 ps
T114 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2773796099 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:54 PM PDT 24 312165361 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.666198733 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:41 PM PDT 24 17460241 ps
T656 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2649956280 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:41 PM PDT 24 13152562 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1257493158 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:54 PM PDT 24 60843226 ps
T658 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2307230048 Apr 23 02:34:45 PM PDT 24 Apr 23 02:34:46 PM PDT 24 15300203 ps
T659 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3196395528 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:57 PM PDT 24 71376106 ps
T660 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3289148244 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:45 PM PDT 24 20353671 ps
T661 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3702321911 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:38 PM PDT 24 17573387 ps
T662 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2253414983 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:53 PM PDT 24 98678051 ps
T663 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2627649975 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 18749611 ps
T664 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1563219601 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:44 PM PDT 24 159785485 ps
T119 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2742446596 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:53 PM PDT 24 193307379 ps
T665 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3400719950 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:51 PM PDT 24 92969356 ps
T666 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.973950496 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:43 PM PDT 24 84117064 ps
T667 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2135099765 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:54 PM PDT 24 15062890 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.432086928 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:41 PM PDT 24 689155162 ps
T117 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3696083232 Apr 23 02:34:32 PM PDT 24 Apr 23 02:34:36 PM PDT 24 196972326 ps
T668 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4080358747 Apr 23 02:34:43 PM PDT 24 Apr 23 02:34:45 PM PDT 24 403983448 ps
T669 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.589944490 Apr 23 02:34:32 PM PDT 24 Apr 23 02:34:35 PM PDT 24 50517514 ps
T670 /workspace/coverage/cover_reg_top/11.hmac_intr_test.243844057 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 14557163 ps
T671 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2491526872 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:55 PM PDT 24 33787071 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1000069981 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:43 PM PDT 24 4052111107 ps
T673 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2751133799 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:44 PM PDT 24 77074265 ps
T674 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2298084609 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 10644471 ps
T675 /workspace/coverage/cover_reg_top/23.hmac_intr_test.31317194 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:54 PM PDT 24 110100379 ps
T676 /workspace/coverage/cover_reg_top/31.hmac_intr_test.379037766 Apr 23 02:34:59 PM PDT 24 Apr 23 02:35:00 PM PDT 24 12905695 ps
T677 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3837042604 Apr 23 02:35:00 PM PDT 24 Apr 23 02:35:02 PM PDT 24 56870407 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2914906658 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:49 PM PDT 24 709032767 ps
T679 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3620807499 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:43 PM PDT 24 42675854 ps
T680 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2670252422 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:51 PM PDT 24 452165593 ps
T681 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.316761238 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:57 PM PDT 24 318409448 ps
T682 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1987703398 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:50 PM PDT 24 88839500 ps
T683 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4005623750 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:42 PM PDT 24 315633139 ps
T684 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3112007086 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:39 PM PDT 24 199158708 ps
T685 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1660894242 Apr 23 02:34:40 PM PDT 24 Apr 23 02:34:45 PM PDT 24 230936695 ps
T686 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3338043260 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:46 PM PDT 24 181083746 ps
T687 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3944690702 Apr 23 02:34:32 PM PDT 24 Apr 23 02:34:34 PM PDT 24 37766437 ps
T688 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1106322217 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:41 PM PDT 24 45775246 ps
T689 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2444642292 Apr 23 02:34:45 PM PDT 24 Apr 23 02:34:46 PM PDT 24 29826634 ps
T690 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.990738420 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 353295528 ps
T691 /workspace/coverage/cover_reg_top/27.hmac_intr_test.569947881 Apr 23 02:34:56 PM PDT 24 Apr 23 02:34:58 PM PDT 24 20111879 ps
T692 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3731952711 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 59257317 ps
T693 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1584261475 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 23386685 ps
T694 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2636027028 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:52 PM PDT 24 313458170 ps
T695 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3191821525 Apr 23 02:34:37 PM PDT 24 Apr 23 02:34:50 PM PDT 24 2100016647 ps
T696 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3773918518 Apr 23 02:34:42 PM PDT 24 Apr 23 02:34:46 PM PDT 24 308387031 ps
T697 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1366634768 Apr 23 02:34:56 PM PDT 24 Apr 23 02:34:58 PM PDT 24 55015775 ps
T698 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2287727295 Apr 23 02:34:57 PM PDT 24 Apr 23 02:34:58 PM PDT 24 16013452 ps
T699 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2901604724 Apr 23 02:34:39 PM PDT 24 Apr 23 02:34:43 PM PDT 24 313518719 ps
T700 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3369011191 Apr 23 02:34:43 PM PDT 24 Apr 23 02:34:47 PM PDT 24 316629808 ps
T701 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1992037828 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:49 PM PDT 24 772045546 ps
T702 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1611588829 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:43 PM PDT 24 96267101 ps
T703 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3596935882 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 32019384 ps
T704 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.948638924 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:46 PM PDT 24 841808176 ps
T705 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.159115566 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 34644347 ps
T706 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2483570381 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:56 PM PDT 24 66648544 ps
T707 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3544120993 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:58 PM PDT 24 158761569 ps
T708 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3430854978 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:54 PM PDT 24 228441378 ps
T709 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1790339135 Apr 23 02:34:56 PM PDT 24 Apr 23 02:34:58 PM PDT 24 44731492 ps
T710 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3418497258 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:50 PM PDT 24 165580895 ps
T711 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4269185763 Apr 23 02:34:44 PM PDT 24 Apr 23 02:34:45 PM PDT 24 48978707 ps
T712 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3299665422 Apr 23 02:34:55 PM PDT 24 Apr 23 02:34:58 PM PDT 24 424747925 ps
T713 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2282331148 Apr 23 02:34:46 PM PDT 24 Apr 23 02:34:47 PM PDT 24 40671345 ps
T714 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4003770469 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:52 PM PDT 24 1088185257 ps
T715 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1462754292 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:53 PM PDT 24 194094870 ps
T716 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1810101796 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 44456145 ps
T717 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.515347996 Apr 23 02:34:41 PM PDT 24 Apr 23 02:34:43 PM PDT 24 22549897 ps
T718 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2572666989 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 13996710 ps
T719 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3168454271 Apr 23 02:34:39 PM PDT 24 Apr 23 02:37:29 PM PDT 24 16109477343 ps
T720 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2057861626 Apr 23 02:34:32 PM PDT 24 Apr 23 02:34:33 PM PDT 24 47517026 ps
T721 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.162005490 Apr 23 02:34:52 PM PDT 24 Apr 23 02:34:55 PM PDT 24 376209906 ps
T722 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1205750394 Apr 23 02:34:38 PM PDT 24 Apr 23 02:34:41 PM PDT 24 24840378 ps
T723 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2021116555 Apr 23 02:34:50 PM PDT 24 Apr 23 02:34:53 PM PDT 24 1931713486 ps
T724 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2975010144 Apr 23 02:34:59 PM PDT 24 Apr 23 02:35:01 PM PDT 24 14668396 ps
T725 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1205387309 Apr 23 02:35:00 PM PDT 24 Apr 23 02:35:01 PM PDT 24 15279428 ps
T726 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1581166883 Apr 23 02:34:49 PM PDT 24 Apr 23 02:34:50 PM PDT 24 44702984 ps
T727 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4222824916 Apr 23 02:34:47 PM PDT 24 Apr 23 02:34:51 PM PDT 24 93825540 ps
T728 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1846958903 Apr 23 02:34:51 PM PDT 24 Apr 23 02:34:52 PM PDT 24 15987753 ps
T729 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2632220189 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:07 PM PDT 24 76703161 ps
T730 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1743701400 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:56 PM PDT 24 14873285 ps
T731 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1929540775 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 14065541 ps
T732 /workspace/coverage/cover_reg_top/46.hmac_intr_test.799860874 Apr 23 02:35:00 PM PDT 24 Apr 23 02:35:01 PM PDT 24 12940341 ps
T733 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1032469556 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:56 PM PDT 24 80436342 ps
T734 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3762325173 Apr 23 02:34:54 PM PDT 24 Apr 23 02:34:55 PM PDT 24 49672472 ps
T735 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1187880232 Apr 23 02:34:58 PM PDT 24 Apr 23 02:34:59 PM PDT 24 16125938 ps
T736 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2875667876 Apr 23 02:34:34 PM PDT 24 Apr 23 02:34:38 PM PDT 24 98546723 ps
T737 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1223101547 Apr 23 02:34:58 PM PDT 24 Apr 23 02:35:00 PM PDT 24 13824768 ps
T738 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3460525758 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:57 PM PDT 24 740087889 ps
T739 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3109081427 Apr 23 02:34:53 PM PDT 24 Apr 23 02:34:55 PM PDT 24 59051592 ps
T740 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.35891881 Apr 23 02:34:34 PM PDT 24 Apr 23 02:34:36 PM PDT 24 56535648 ps
T741 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2727633498 Apr 23 02:35:04 PM PDT 24 Apr 23 02:35:06 PM PDT 24 22039898 ps

Test location /workspace/coverage/default/8.hmac_burst_wr.385703067
Short name T17
Test name
Test status
Simulation time 1345114666 ps
CPU time 66.42 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:42:01 PM PDT 24
Peak memory 199616 kb
Host smart-a1419e54-67a9-4097-b2a6-7615cd1f4ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385703067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.385703067
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.1523655916
Short name T6
Test name
Test status
Simulation time 91921848260 ps
CPU time 2532.86 seconds
Started Apr 23 02:43:57 PM PDT 24
Finished Apr 23 03:26:10 PM PDT 24
Peak memory 244472 kb
Host smart-df8d3a9f-3da4-448f-8bf4-15de18c33039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523655916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.1523655916
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3362281649
Short name T24
Test name
Test status
Simulation time 395314446 ps
CPU time 0.96 seconds
Started Apr 23 02:40:40 PM PDT 24
Finished Apr 23 02:40:41 PM PDT 24
Peak memory 218148 kb
Host smart-56294f17-8b0a-4683-b2eb-6c02247d0c96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362281649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3362281649
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3563688344
Short name T15
Test name
Test status
Simulation time 12247626348 ps
CPU time 693.5 seconds
Started Apr 23 02:41:06 PM PDT 24
Finished Apr 23 02:52:40 PM PDT 24
Peak memory 216084 kb
Host smart-958c9481-0721-4895-a829-ba578ac978a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563688344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3563688344
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4093611891
Short name T60
Test name
Test status
Simulation time 199890514 ps
CPU time 3.15 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 199076 kb
Host smart-e48c3320-5b91-4fdf-98d1-aa0712f07104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093611891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4093611891
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.1292427972
Short name T8
Test name
Test status
Simulation time 47401778008 ps
CPU time 2615.76 seconds
Started Apr 23 02:42:50 PM PDT 24
Finished Apr 23 03:26:27 PM PDT 24
Peak memory 245064 kb
Host smart-0a723f9c-de02-4a40-8586-afc976a6b0a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292427972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.1292427972
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2916898423
Short name T22
Test name
Test status
Simulation time 43439972 ps
CPU time 0.65 seconds
Started Apr 23 02:42:28 PM PDT 24
Finished Apr 23 02:42:29 PM PDT 24
Peak memory 195240 kb
Host smart-900e8998-7c68-4189-b4b2-4b515a25af72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916898423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2916898423
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3538765425
Short name T37
Test name
Test status
Simulation time 64858419 ps
CPU time 3.17 seconds
Started Apr 23 02:41:42 PM PDT 24
Finished Apr 23 02:41:45 PM PDT 24
Peak memory 199604 kb
Host smart-e8d7e6e4-15bd-4168-bfb1-206e189785cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538765425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3538765425
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_error.13181811
Short name T54
Test name
Test status
Simulation time 13133406648 ps
CPU time 152.38 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:43:04 PM PDT 24
Peak memory 199724 kb
Host smart-822c6e26-f293-4af1-83bd-216c598c23b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.13181811
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2651644030
Short name T61
Test name
Test status
Simulation time 1220001565 ps
CPU time 4.13 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 199064 kb
Host smart-3a965e40-4a7a-4d92-a884-0df3b4d0f730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651644030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2651644030
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.208845239
Short name T103
Test name
Test status
Simulation time 184846669 ps
CPU time 3.29 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:42 PM PDT 24
Peak memory 198060 kb
Host smart-1d117675-4af5-40f8-957f-2f4fae40a91a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208845239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.208845239
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3696083232
Short name T117
Test name
Test status
Simulation time 196972326 ps
CPU time 3.11 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 199076 kb
Host smart-4a2c7790-4b13-49d4-862f-7b0b903a066e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696083232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3696083232
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.3188544560
Short name T66
Test name
Test status
Simulation time 98977589305 ps
CPU time 851.3 seconds
Started Apr 23 02:41:01 PM PDT 24
Finished Apr 23 02:55:13 PM PDT 24
Peak memory 216128 kb
Host smart-1beaf269-06bf-4b17-9d7b-a613fd802ffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188544560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.3188544560
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_error.3709531252
Short name T528
Test name
Test status
Simulation time 27057555828 ps
CPU time 98.36 seconds
Started Apr 23 02:41:49 PM PDT 24
Finished Apr 23 02:43:28 PM PDT 24
Peak memory 199756 kb
Host smart-ad07f16c-c8d9-4849-85e1-0cbc8939d6bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709531252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3709531252
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3612826779
Short name T50
Test name
Test status
Simulation time 20327172300 ps
CPU time 278.53 seconds
Started Apr 23 02:43:26 PM PDT 24
Finished Apr 23 02:48:05 PM PDT 24
Peak memory 215244 kb
Host smart-f0bdf189-c995-4b3d-b899-a27d54b7bc7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612826779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.3612826779
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3191821525
Short name T695
Test name
Test status
Simulation time 2100016647 ps
CPU time 11.77 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 198024 kb
Host smart-942d07e8-c20a-447f-ab94-175fd9fa3da5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191821525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3191821525
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3944690702
Short name T687
Test name
Test status
Simulation time 37766437 ps
CPU time 0.93 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:34 PM PDT 24
Peak memory 198004 kb
Host smart-82141e23-1d6d-414f-b038-72e3431d5b55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944690702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3944690702
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1205750394
Short name T722
Test name
Test status
Simulation time 24840378 ps
CPU time 1.55 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 199112 kb
Host smart-2314a78d-6883-4953-99d5-db4718cd227a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205750394 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1205750394
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.35891881
Short name T740
Test name
Test status
Simulation time 56535648 ps
CPU time 0.66 seconds
Started Apr 23 02:34:34 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 196452 kb
Host smart-5482f19b-3103-4809-b19d-0c1827c6976e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.35891881
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1166720740
Short name T607
Test name
Test status
Simulation time 24888700 ps
CPU time 0.59 seconds
Started Apr 23 02:34:33 PM PDT 24
Finished Apr 23 02:34:35 PM PDT 24
Peak memory 193688 kb
Host smart-f86e4f5c-e9ec-49c4-ab7c-6bd4d32608f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166720740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1166720740
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3753020932
Short name T632
Test name
Test status
Simulation time 67531103 ps
CPU time 2.14 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:42 PM PDT 24
Peak memory 199036 kb
Host smart-20bf2142-a49d-4796-bd43-98ec39fc6191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753020932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3753020932
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.947063117
Short name T609
Test name
Test status
Simulation time 205271701 ps
CPU time 3.81 seconds
Started Apr 23 02:34:35 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 199120 kb
Host smart-3d9310ca-9df1-4beb-bcde-f44a7fc827f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947063117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.947063117
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.948638924
Short name T704
Test name
Test status
Simulation time 841808176 ps
CPU time 3.62 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 197816 kb
Host smart-b3144fbf-cc30-4f17-ac18-8cecf841fb82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948638924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.948638924
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1000069981
Short name T672
Test name
Test status
Simulation time 4052111107 ps
CPU time 5.84 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 197992 kb
Host smart-2a9d96ce-def2-44f9-a89f-b1de996d8ac8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000069981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1000069981
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2057861626
Short name T720
Test name
Test status
Simulation time 47517026 ps
CPU time 0.82 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:33 PM PDT 24
Peak memory 198148 kb
Host smart-93cedef9-0a7a-4faa-86e2-2fce382e0dbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057861626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2057861626
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2875667876
Short name T736
Test name
Test status
Simulation time 98546723 ps
CPU time 2.05 seconds
Started Apr 23 02:34:34 PM PDT 24
Finished Apr 23 02:34:38 PM PDT 24
Peak memory 199144 kb
Host smart-036f36ac-f925-4067-957d-22221d0256f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875667876 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2875667876
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.589944490
Short name T669
Test name
Test status
Simulation time 50517514 ps
CPU time 0.91 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:35 PM PDT 24
Peak memory 198272 kb
Host smart-e2ede065-a947-4648-b52f-115169763435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589944490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.589944490
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.896784984
Short name T621
Test name
Test status
Simulation time 27424082 ps
CPU time 0.57 seconds
Started Apr 23 02:34:36 PM PDT 24
Finished Apr 23 02:34:38 PM PDT 24
Peak memory 193644 kb
Host smart-6c79e824-f373-43c8-8f8d-e93c9a81c08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896784984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.896784984
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.515347996
Short name T717
Test name
Test status
Simulation time 22549897 ps
CPU time 1.07 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 197208 kb
Host smart-a1331fb3-1792-4164-b769-c5257908341a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515347996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.515347996
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1960870465
Short name T605
Test name
Test status
Simulation time 170381304 ps
CPU time 3.19 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:37 PM PDT 24
Peak memory 199036 kb
Host smart-e51925aa-b94a-4fd6-b2ce-29eb8e60771a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960870465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1960870465
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2670252422
Short name T680
Test name
Test status
Simulation time 452165593 ps
CPU time 1.12 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:51 PM PDT 24
Peak memory 198988 kb
Host smart-c89f1c23-ec70-4dfe-9a38-850e100b5cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670252422 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2670252422
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1581166883
Short name T726
Test name
Test status
Simulation time 44702984 ps
CPU time 0.68 seconds
Started Apr 23 02:34:49 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 197064 kb
Host smart-7d75cc53-da28-4494-ba3d-0f7f3b1e1797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581166883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1581166883
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3289148244
Short name T660
Test name
Test status
Simulation time 20353671 ps
CPU time 0.55 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 193936 kb
Host smart-62effcfd-becc-46b4-a9fa-f8e9a8398add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289148244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3289148244
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.990738420
Short name T690
Test name
Test status
Simulation time 353295528 ps
CPU time 1.28 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 198964 kb
Host smart-d1c582df-93a4-40a2-a75f-f47250f0cf79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990738420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.990738420
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3400719950
Short name T665
Test name
Test status
Simulation time 92969356 ps
CPU time 2.2 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:51 PM PDT 24
Peak memory 199064 kb
Host smart-e20ea6ee-bfda-4467-be3f-260894462ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400719950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3400719950
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1631929845
Short name T116
Test name
Test status
Simulation time 1597868759 ps
CPU time 5.09 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 199012 kb
Host smart-67d85e4a-686f-4775-a02e-8d5a56258490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631929845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1631929845
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2253414983
Short name T662
Test name
Test status
Simulation time 98678051 ps
CPU time 1.7 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 199076 kb
Host smart-d298644c-a0fa-4251-abbf-7f1f25fe2e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253414983 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2253414983
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1991508714
Short name T107
Test name
Test status
Simulation time 413067220 ps
CPU time 0.79 seconds
Started Apr 23 02:34:46 PM PDT 24
Finished Apr 23 02:34:48 PM PDT 24
Peak memory 198036 kb
Host smart-5ee295ac-4d38-4d43-8e8a-61047d555fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991508714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1991508714
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.243844057
Short name T670
Test name
Test status
Simulation time 14557163 ps
CPU time 0.62 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193832 kb
Host smart-a8700ff4-30e3-4a35-9780-2bba6e02da86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243844057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.243844057
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.921865428
Short name T63
Test name
Test status
Simulation time 117470976 ps
CPU time 2.52 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:08 PM PDT 24
Peak memory 198524 kb
Host smart-2d1a5ef5-aec0-42ce-b928-685cf7cc4073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921865428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.921865428
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1773797762
Short name T644
Test name
Test status
Simulation time 206439275 ps
CPU time 3.56 seconds
Started Apr 23 02:34:49 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 199176 kb
Host smart-684abc7c-5c69-4b20-94bc-7facc0a5cc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773797762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1773797762
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3838516436
Short name T59
Test name
Test status
Simulation time 119710141 ps
CPU time 3.9 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 199052 kb
Host smart-f241c757-13ea-45cf-b323-c254cecf0257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838516436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3838516436
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2632220189
Short name T729
Test name
Test status
Simulation time 76703161 ps
CPU time 2.04 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:07 PM PDT 24
Peak memory 199056 kb
Host smart-5c3e0524-a189-4981-8c23-140c9e7692c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632220189 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2632220189
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3596935882
Short name T703
Test name
Test status
Simulation time 32019384 ps
CPU time 0.86 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 197728 kb
Host smart-41745637-eee3-4548-b2fd-6c1e4479b66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596935882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3596935882
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1584261475
Short name T693
Test name
Test status
Simulation time 23386685 ps
CPU time 0.62 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193616 kb
Host smart-ae070ff5-ee55-4256-b903-13f47ebf27cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584261475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1584261475
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4222824916
Short name T727
Test name
Test status
Simulation time 93825540 ps
CPU time 2.14 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:51 PM PDT 24
Peak memory 198988 kb
Host smart-f06640e7-2af1-4c44-88f1-d55a2c3c6eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222824916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4222824916
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2284785606
Short name T652
Test name
Test status
Simulation time 74581419 ps
CPU time 1.76 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 199064 kb
Host smart-55b961cc-2f6b-4255-865f-e26cc0f60f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284785606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2284785606
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2773796099
Short name T114
Test name
Test status
Simulation time 312165361 ps
CPU time 3.16 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 199084 kb
Host smart-30da867a-3ad3-47a7-a648-34797807e764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773796099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2773796099
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3210045086
Short name T625
Test name
Test status
Simulation time 396705964 ps
CPU time 2.51 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:59 PM PDT 24
Peak memory 199160 kb
Host smart-b2bff6ad-ab18-4cfd-af1f-719530db1a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210045086 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3210045086
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1255316575
Short name T110
Test name
Test status
Simulation time 26183676 ps
CPU time 0.69 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 196344 kb
Host smart-ebcb50a9-e496-478c-a7d3-5be80da2f0a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255316575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1255316575
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2727633498
Short name T741
Test name
Test status
Simulation time 22039898 ps
CPU time 0.59 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193652 kb
Host smart-b80bbc40-9a7c-4997-b442-d1642208479a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727633498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2727633498
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1987703398
Short name T682
Test name
Test status
Simulation time 88839500 ps
CPU time 1.16 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 199064 kb
Host smart-68dbdf72-f835-4288-8a05-1dfa821dc3eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987703398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1987703398
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3418497258
Short name T710
Test name
Test status
Simulation time 165580895 ps
CPU time 1.64 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 199144 kb
Host smart-7228e042-3c62-4de8-b15c-dc3c7652d7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418497258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3418497258
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2636027028
Short name T694
Test name
Test status
Simulation time 313458170 ps
CPU time 3.08 seconds
Started Apr 23 02:34:47 PM PDT 24
Finished Apr 23 02:34:52 PM PDT 24
Peak memory 199056 kb
Host smart-5f454f6c-285f-49d6-9735-f41f4bc3313b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636027028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2636027028
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1210309404
Short name T654
Test name
Test status
Simulation time 159170863082 ps
CPU time 208.53 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 214708 kb
Host smart-1e802391-1c14-4ec4-b66d-9aa1366d19bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210309404 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1210309404
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1462754292
Short name T715
Test name
Test status
Simulation time 194094870 ps
CPU time 0.93 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 198508 kb
Host smart-9b4588d6-434e-42da-9fb2-1a9b71c14ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462754292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1462754292
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1743701400
Short name T730
Test name
Test status
Simulation time 14873285 ps
CPU time 0.66 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:56 PM PDT 24
Peak memory 193836 kb
Host smart-5d4878ff-6792-472e-a343-4ae1a9ca22a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743701400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1743701400
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1032469556
Short name T733
Test name
Test status
Simulation time 80436342 ps
CPU time 1.14 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:56 PM PDT 24
Peak memory 198348 kb
Host smart-01e1e67e-cbbf-4d41-85ef-13db060c7316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032469556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1032469556
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2617041234
Short name T630
Test name
Test status
Simulation time 46653549 ps
CPU time 2.15 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 199092 kb
Host smart-bf288860-98d5-4137-a403-341f7f3a22de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617041234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2617041234
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3430854978
Short name T708
Test name
Test status
Simulation time 228441378 ps
CPU time 4.07 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 199072 kb
Host smart-dd244f4c-91ad-45fd-8594-5fbf23a2c155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430854978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3430854978
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3196395528
Short name T659
Test name
Test status
Simulation time 71376106 ps
CPU time 1.8 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 199060 kb
Host smart-15ae4ae5-51c3-44df-8d44-89865b5c5047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196395528 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3196395528
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.837401732
Short name T102
Test name
Test status
Simulation time 22106521 ps
CPU time 0.87 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 198124 kb
Host smart-0f70bc0f-4379-470b-82c9-dc25327d908f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837401732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.837401732
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1846958903
Short name T728
Test name
Test status
Simulation time 15987753 ps
CPU time 0.59 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:52 PM PDT 24
Peak memory 193724 kb
Host smart-ff6d7a56-39ca-464a-aafb-e19ce6ef6e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846958903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1846958903
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.316761238
Short name T681
Test name
Test status
Simulation time 318409448 ps
CPU time 1.05 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 197276 kb
Host smart-653dd1d3-9ebe-47cf-adcc-8757c8535179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316761238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.316761238
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1321049068
Short name T613
Test name
Test status
Simulation time 279244173 ps
CPU time 2.97 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 199068 kb
Host smart-b36a84f6-58ec-45c1-98da-22eba259c47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321049068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1321049068
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.162005490
Short name T721
Test name
Test status
Simulation time 376209906 ps
CPU time 2.47 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 199100 kb
Host smart-e800057c-fe43-4168-961c-5eb0ab5d1fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162005490 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.162005490
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.568970131
Short name T111
Test name
Test status
Simulation time 25364649 ps
CPU time 0.77 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 198236 kb
Host smart-528bdbb6-9ce2-4698-a399-4035969734a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568970131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.568970131
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.614762731
Short name T639
Test name
Test status
Simulation time 31186320 ps
CPU time 0.58 seconds
Started Apr 23 02:34:49 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 193700 kb
Host smart-0463c1f4-21d7-45a8-bd67-9b69214ab7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614762731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.614762731
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3305228004
Short name T614
Test name
Test status
Simulation time 318857317 ps
CPU time 1.16 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 198956 kb
Host smart-089035cd-a747-45c2-8993-7a62daa4ab83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305228004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3305228004
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2021116555
Short name T723
Test name
Test status
Simulation time 1931713486 ps
CPU time 2.42 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 199192 kb
Host smart-daf895f2-8eca-4ca0-be4a-447c199c5628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021116555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2021116555
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2742446596
Short name T119
Test name
Test status
Simulation time 193307379 ps
CPU time 1.91 seconds
Started Apr 23 02:34:50 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 199080 kb
Host smart-ffa348e0-7980-4ae1-b1f4-662160fa9c71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742446596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2742446596
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2483570381
Short name T706
Test name
Test status
Simulation time 66648544 ps
CPU time 2.11 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:56 PM PDT 24
Peak memory 199092 kb
Host smart-812bf5e2-a60c-49bc-a5fb-8c0cb8633938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483570381 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2483570381
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3812205496
Short name T645
Test name
Test status
Simulation time 27197945 ps
CPU time 0.7 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 196848 kb
Host smart-11173df1-09fb-4489-9aff-da584b61c81e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812205496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3812205496
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2135099765
Short name T667
Test name
Test status
Simulation time 15062890 ps
CPU time 0.57 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 193632 kb
Host smart-57c7cda2-8ef5-4a14-83b4-c8f395522ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135099765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2135099765
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3881859554
Short name T80
Test name
Test status
Simulation time 243630579 ps
CPU time 1.21 seconds
Started Apr 23 02:34:51 PM PDT 24
Finished Apr 23 02:34:53 PM PDT 24
Peak memory 197288 kb
Host smart-d7260463-98e0-4749-b70d-78a3721e2c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881859554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3881859554
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2331247649
Short name T647
Test name
Test status
Simulation time 343497398 ps
CPU time 3.22 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 199088 kb
Host smart-9dd46381-a7ca-4305-8047-8057e61a9a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331247649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2331247649
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3460525758
Short name T738
Test name
Test status
Simulation time 740087889 ps
CPU time 3.23 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 199020 kb
Host smart-2ebda0cc-77b2-455e-9f7b-449fd2312b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460525758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3460525758
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3299665422
Short name T712
Test name
Test status
Simulation time 424747925 ps
CPU time 2.36 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 199144 kb
Host smart-a3f58dca-71ab-447d-bd61-ccfd87603496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299665422 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3299665422
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.159115566
Short name T705
Test name
Test status
Simulation time 34644347 ps
CPU time 0.97 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 197928 kb
Host smart-b99082ad-9bb7-4abe-89f6-ea90137a632b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159115566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.159115566
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3109081427
Short name T739
Test name
Test status
Simulation time 59051592 ps
CPU time 0.57 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193744 kb
Host smart-46acf2ac-6b28-4c61-bed7-26cd1db95b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109081427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3109081427
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1376548225
Short name T624
Test name
Test status
Simulation time 1638360183 ps
CPU time 2.15 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 199048 kb
Host smart-15669fe1-03e3-44a7-a8af-5289504b6fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376548225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1376548225
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1151629971
Short name T610
Test name
Test status
Simulation time 127181590 ps
CPU time 3.19 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 199176 kb
Host smart-e493bde2-7cec-412e-9c22-6e055a4e3e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151629971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1151629971
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4048071273
Short name T648
Test name
Test status
Simulation time 250804471 ps
CPU time 4.26 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 199064 kb
Host smart-fb63d081-bb7d-4766-a758-4209fdcf417d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048071273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4048071273
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3660182734
Short name T616
Test name
Test status
Simulation time 88626501 ps
CPU time 3.79 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 199140 kb
Host smart-f48144b9-e1b2-4754-a3d3-9881fe00203f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660182734 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3660182734
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1790339135
Short name T709
Test name
Test status
Simulation time 44731492 ps
CPU time 0.85 seconds
Started Apr 23 02:34:56 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 198788 kb
Host smart-70cb2368-1c29-4bf8-b539-72fd0e2ebe31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790339135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1790339135
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2298084609
Short name T674
Test name
Test status
Simulation time 10644471 ps
CPU time 0.57 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193656 kb
Host smart-61a5f233-735e-4aa0-99d1-f027ee8e4e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298084609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2298084609
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3628020107
Short name T623
Test name
Test status
Simulation time 446235204 ps
CPU time 2.33 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 199084 kb
Host smart-903bca03-9fae-482d-af2d-9394efc81396
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628020107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3628020107
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.456301817
Short name T636
Test name
Test status
Simulation time 545935009 ps
CPU time 3.72 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:59 PM PDT 24
Peak memory 199116 kb
Host smart-bb365caa-c5ac-4f54-98a2-c0b8b650f68d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456301817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.456301817
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3544120993
Short name T707
Test name
Test status
Simulation time 158761569 ps
CPU time 3.06 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 199080 kb
Host smart-13d5ee0d-0c94-40b5-8704-813da57cc761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544120993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3544120993
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3293947432
Short name T108
Test name
Test status
Simulation time 159072252 ps
CPU time 7.97 seconds
Started Apr 23 02:34:34 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 198644 kb
Host smart-d8e07604-3a5e-4998-b1fa-0418353b5288
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293947432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3293947432
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4003770469
Short name T714
Test name
Test status
Simulation time 1088185257 ps
CPU time 9.97 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:52 PM PDT 24
Peak memory 198984 kb
Host smart-d025bf9e-3a44-4306-bc70-75ecc1e3bccb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003770469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4003770469
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3382662181
Short name T112
Test name
Test status
Simulation time 27939663 ps
CPU time 0.72 seconds
Started Apr 23 02:34:35 PM PDT 24
Finished Apr 23 02:34:37 PM PDT 24
Peak memory 196444 kb
Host smart-53ca6d25-22c3-4693-9bcc-c79183aec4c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382662181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3382662181
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.845880749
Short name T653
Test name
Test status
Simulation time 82866972 ps
CPU time 1.27 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 199136 kb
Host smart-0b338dcb-ec76-4cce-8bfb-ae1ebd6dcacb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845880749 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.845880749
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3702321911
Short name T661
Test name
Test status
Simulation time 17573387 ps
CPU time 0.7 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:38 PM PDT 24
Peak memory 196540 kb
Host smart-ad778e92-7a32-4315-81b7-aa8c04afb788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702321911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3702321911
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4209205347
Short name T637
Test name
Test status
Simulation time 18917350 ps
CPU time 0.54 seconds
Started Apr 23 02:34:35 PM PDT 24
Finished Apr 23 02:34:37 PM PDT 24
Peak memory 193604 kb
Host smart-92560516-16c0-47c0-b9d6-842ea00cefa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209205347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4209205347
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3112007086
Short name T684
Test name
Test status
Simulation time 199158708 ps
CPU time 1.13 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:39 PM PDT 24
Peak memory 198508 kb
Host smart-0dcd6752-d03b-4f66-8775-023d939805e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112007086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3112007086
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1459899148
Short name T602
Test name
Test status
Simulation time 273005516 ps
CPU time 4.57 seconds
Started Apr 23 02:34:35 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 199124 kb
Host smart-5abd0ee1-14c6-405b-bbee-a9c4cb890022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459899148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1459899148
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.432086928
Short name T118
Test name
Test status
Simulation time 689155162 ps
CPU time 3.12 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 199124 kb
Host smart-a0eaf586-c51c-42f9-832e-3d45d54e328c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432086928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.432086928
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2627649975
Short name T663
Test name
Test status
Simulation time 18749611 ps
CPU time 0.59 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193912 kb
Host smart-54ab4e3f-77be-4af6-a38c-611b2c1bfaee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627649975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2627649975
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3762325173
Short name T734
Test name
Test status
Simulation time 49672472 ps
CPU time 0.62 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193912 kb
Host smart-34743a14-0f52-4a93-b2f8-4fd206a729e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762325173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3762325173
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2572666989
Short name T718
Test name
Test status
Simulation time 13996710 ps
CPU time 0.61 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193896 kb
Host smart-b010bd48-284e-4558-ad5e-30658ae47d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572666989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2572666989
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.31317194
Short name T675
Test name
Test status
Simulation time 110100379 ps
CPU time 0.55 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 193624 kb
Host smart-0080bcea-b252-46ad-8baa-75c909f10d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31317194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.31317194
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1929540775
Short name T731
Test name
Test status
Simulation time 14065541 ps
CPU time 0.56 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193708 kb
Host smart-2641cc5c-6131-4647-b4d2-0ab86a53243d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929540775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1929540775
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.781752710
Short name T626
Test name
Test status
Simulation time 14856810 ps
CPU time 0.56 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 193520 kb
Host smart-3afed902-4030-40bd-9490-eea14f01ea9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781752710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.781752710
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1366634768
Short name T697
Test name
Test status
Simulation time 55015775 ps
CPU time 0.63 seconds
Started Apr 23 02:34:56 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 193912 kb
Host smart-4549193d-9319-48e2-925b-664e96e3cc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366634768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1366634768
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.569947881
Short name T691
Test name
Test status
Simulation time 20111879 ps
CPU time 0.58 seconds
Started Apr 23 02:34:56 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 193676 kb
Host smart-840d34bb-d41f-4d69-be5d-d2085e3a5992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569947881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.569947881
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3793053183
Short name T606
Test name
Test status
Simulation time 13929425 ps
CPU time 0.58 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 193772 kb
Host smart-7cb1d93d-2777-4248-84d7-b095e5521343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793053183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3793053183
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1358055470
Short name T603
Test name
Test status
Simulation time 123670833 ps
CPU time 0.6 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193564 kb
Host smart-b7ebeacf-49ae-4586-830a-716baaac1432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358055470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1358055470
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1976960026
Short name T109
Test name
Test status
Simulation time 216838257 ps
CPU time 2.93 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 197940 kb
Host smart-d0e4da6c-c4ad-4dfc-9bc8-81b502d62538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976960026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1976960026
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2914906658
Short name T678
Test name
Test status
Simulation time 709032767 ps
CPU time 10.55 seconds
Started Apr 23 02:34:37 PM PDT 24
Finished Apr 23 02:34:49 PM PDT 24
Peak memory 198944 kb
Host smart-aefd9551-4be1-4455-8f72-1ce1f1e810de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914906658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2914906658
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1711277181
Short name T62
Test name
Test status
Simulation time 60271946 ps
CPU time 0.71 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 196312 kb
Host smart-9fc76191-6c54-4abe-93fb-b84be7e365e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711277181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1711277181
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2901604724
Short name T699
Test name
Test status
Simulation time 313518719 ps
CPU time 2.3 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 199076 kb
Host smart-22462791-69cf-469a-b20e-63292ccbee21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901604724 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2901604724
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3479780817
Short name T617
Test name
Test status
Simulation time 27001221 ps
CPU time 0.9 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 198776 kb
Host smart-2300c9a2-72b1-40ac-878c-bf724f519947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479780817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3479780817
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2649956280
Short name T656
Test name
Test status
Simulation time 13152562 ps
CPU time 0.6 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 193660 kb
Host smart-187d1f06-0685-4b0a-b267-966e522897f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649956280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2649956280
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1106322217
Short name T688
Test name
Test status
Simulation time 45775246 ps
CPU time 1.1 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 198680 kb
Host smart-58f5401a-13ad-4cb3-9dd3-f63ca6f70737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106322217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1106322217
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2751133799
Short name T673
Test name
Test status
Simulation time 77074265 ps
CPU time 4.01 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 199100 kb
Host smart-ff17ee17-d24c-407a-9422-ccde2a19ae2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751133799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2751133799
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3775571469
Short name T113
Test name
Test status
Simulation time 238709908 ps
CPU time 4.16 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 199108 kb
Host smart-b32d2d1c-31ef-4a6f-a647-7df1fc1484c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775571469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3775571469
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.302384092
Short name T79
Test name
Test status
Simulation time 166468808 ps
CPU time 0.59 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193728 kb
Host smart-c9a9fee3-492d-43d1-8f02-a792e454f0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302384092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.302384092
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.379037766
Short name T676
Test name
Test status
Simulation time 12905695 ps
CPU time 0.59 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 193656 kb
Host smart-e86bbfca-85a5-41fb-8fe7-67177cd7a117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379037766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.379037766
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3785970006
Short name T638
Test name
Test status
Simulation time 14389405 ps
CPU time 0.6 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 193600 kb
Host smart-e8781a75-ac64-41ff-9fca-d065781c9b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785970006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3785970006
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3029120376
Short name T628
Test name
Test status
Simulation time 12932958 ps
CPU time 0.55 seconds
Started Apr 23 02:34:56 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 193672 kb
Host smart-4d332720-1769-454f-a93e-2a2b1c535c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029120376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3029120376
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.435688642
Short name T642
Test name
Test status
Simulation time 29216270 ps
CPU time 0.59 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:01 PM PDT 24
Peak memory 193552 kb
Host smart-f1fd6811-4240-49c4-be36-ed12be6fc096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435688642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.435688642
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3731952711
Short name T692
Test name
Test status
Simulation time 59257317 ps
CPU time 0.62 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193916 kb
Host smart-b2126ee6-4bd1-4e33-b986-7d7d40303f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731952711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3731952711
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1187880232
Short name T735
Test name
Test status
Simulation time 16125938 ps
CPU time 0.57 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:34:59 PM PDT 24
Peak memory 193876 kb
Host smart-6e0cb73e-e639-41a2-956d-36c1ea4cabea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187880232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1187880232
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1783663598
Short name T643
Test name
Test status
Simulation time 92492514 ps
CPU time 0.55 seconds
Started Apr 23 02:34:54 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 193916 kb
Host smart-bd564d78-c401-4b61-8d9c-84ec5bbe11d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783663598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1783663598
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1630125504
Short name T635
Test name
Test status
Simulation time 20082039 ps
CPU time 0.56 seconds
Started Apr 23 02:34:55 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 193668 kb
Host smart-6ae3d621-e720-4b83-a286-a1f6fdcd84e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630125504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1630125504
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2287727295
Short name T698
Test name
Test status
Simulation time 16013452 ps
CPU time 0.61 seconds
Started Apr 23 02:34:57 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 193884 kb
Host smart-baf127d9-925e-4b81-abc4-627974b3202a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287727295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2287727295
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3472727391
Short name T634
Test name
Test status
Simulation time 652813361 ps
CPU time 3.36 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 198972 kb
Host smart-6bbdc506-aa44-4bcd-a69a-29e47be3890c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472727391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3472727391
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.972867252
Short name T106
Test name
Test status
Simulation time 111505847 ps
CPU time 5.22 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:48 PM PDT 24
Peak memory 197884 kb
Host smart-4a6cc1cd-f0f7-4cfc-a5bf-8d9a19b48999
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972867252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.972867252
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.517769238
Short name T104
Test name
Test status
Simulation time 39266377 ps
CPU time 0.7 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 196812 kb
Host smart-4e0be327-48f7-4b36-810e-cc640918d42f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517769238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.517769238
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3168454271
Short name T719
Test name
Test status
Simulation time 16109477343 ps
CPU time 168.04 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:37:29 PM PDT 24
Peak memory 214932 kb
Host smart-f729f17f-c875-49bb-a59f-89963f7f99c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168454271 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3168454271
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.666198733
Short name T655
Test name
Test status
Simulation time 17460241 ps
CPU time 0.77 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:41 PM PDT 24
Peak memory 198228 kb
Host smart-2def7a59-733b-4d80-9ace-8b94d32f55b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666198733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.666198733
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2517343970
Short name T640
Test name
Test status
Simulation time 33421820 ps
CPU time 0.55 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:42 PM PDT 24
Peak memory 193636 kb
Host smart-b5e48480-8f61-4f9d-9915-9c30a879e46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517343970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2517343970
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4005623750
Short name T683
Test name
Test status
Simulation time 315633139 ps
CPU time 1.76 seconds
Started Apr 23 02:34:38 PM PDT 24
Finished Apr 23 02:34:42 PM PDT 24
Peak memory 198744 kb
Host smart-f8287f94-e8df-400c-a760-385a1d5bca06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005623750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4005623750
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3175694743
Short name T633
Test name
Test status
Simulation time 124297176 ps
CPU time 2.55 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 199080 kb
Host smart-d128f39c-5514-48c9-8de3-1994eef9e0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175694743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3175694743
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.973950496
Short name T666
Test name
Test status
Simulation time 84117064 ps
CPU time 1.89 seconds
Started Apr 23 02:34:39 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 199044 kb
Host smart-f93493ec-384d-47ea-aa89-2ddb66e1e772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973950496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.973950496
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1810101796
Short name T716
Test name
Test status
Simulation time 44456145 ps
CPU time 0.65 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193720 kb
Host smart-815a624f-b8b3-4262-b492-c9c759f558fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810101796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1810101796
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3837042604
Short name T677
Test name
Test status
Simulation time 56870407 ps
CPU time 0.62 seconds
Started Apr 23 02:35:00 PM PDT 24
Finished Apr 23 02:35:02 PM PDT 24
Peak memory 193920 kb
Host smart-3fdb112f-c87a-4684-994a-ba13900351b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837042604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3837042604
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1060000455
Short name T618
Test name
Test status
Simulation time 42029655 ps
CPU time 0.58 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 193892 kb
Host smart-adb6aa09-f283-4e1b-8844-4584d8085719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060000455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1060000455
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1223101547
Short name T737
Test name
Test status
Simulation time 13824768 ps
CPU time 0.56 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 193664 kb
Host smart-8b34d214-0628-4a3e-969a-76e1e35368ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223101547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1223101547
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2975010144
Short name T724
Test name
Test status
Simulation time 14668396 ps
CPU time 0.59 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:01 PM PDT 24
Peak memory 193552 kb
Host smart-05f7f826-a66e-4c06-9830-cc3640f772aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975010144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2975010144
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2840278684
Short name T612
Test name
Test status
Simulation time 25665819 ps
CPU time 0.6 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 193720 kb
Host smart-25e403f9-4ab1-445f-b088-16a7a62dcbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840278684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2840278684
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.799860874
Short name T732
Test name
Test status
Simulation time 12940341 ps
CPU time 0.58 seconds
Started Apr 23 02:35:00 PM PDT 24
Finished Apr 23 02:35:01 PM PDT 24
Peak memory 193620 kb
Host smart-51af98d7-ffe2-4b3f-b2e0-458dd0a092c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799860874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.799860874
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3536207888
Short name T611
Test name
Test status
Simulation time 32044716 ps
CPU time 0.62 seconds
Started Apr 23 02:35:05 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 193664 kb
Host smart-fd41b13a-e233-4c25-a576-88dccbc5b592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536207888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3536207888
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3756516397
Short name T631
Test name
Test status
Simulation time 14349947 ps
CPU time 0.61 seconds
Started Apr 23 02:35:01 PM PDT 24
Finished Apr 23 02:35:03 PM PDT 24
Peak memory 193672 kb
Host smart-a0c19ce7-5d1a-4a29-87f0-f6be9760afeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756516397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3756516397
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1205387309
Short name T725
Test name
Test status
Simulation time 15279428 ps
CPU time 0.59 seconds
Started Apr 23 02:35:00 PM PDT 24
Finished Apr 23 02:35:01 PM PDT 24
Peak memory 193640 kb
Host smart-3c6767b0-e306-4310-b3af-f63928b2dd65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205387309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1205387309
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3197153817
Short name T619
Test name
Test status
Simulation time 303784614 ps
CPU time 2.38 seconds
Started Apr 23 02:34:43 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 199132 kb
Host smart-d85b2289-2952-4fa4-adce-262ddd9fb280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197153817 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3197153817
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4080358747
Short name T668
Test name
Test status
Simulation time 403983448 ps
CPU time 0.79 seconds
Started Apr 23 02:34:43 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 197988 kb
Host smart-b3680e7e-62c8-43bd-b5fb-0a58ed1c6b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080358747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4080358747
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1611588829
Short name T702
Test name
Test status
Simulation time 96267101 ps
CPU time 0.64 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 193580 kb
Host smart-40bf9634-6237-48ac-a1f4-819221677364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611588829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1611588829
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3797110640
Short name T620
Test name
Test status
Simulation time 163936826 ps
CPU time 1.1 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 199040 kb
Host smart-8847354b-c479-49fe-b441-703f681ada83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797110640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3797110640
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.514248632
Short name T627
Test name
Test status
Simulation time 178693188 ps
CPU time 3.42 seconds
Started Apr 23 02:34:42 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 199120 kb
Host smart-0ac41c09-171a-49f1-9c02-9f39756f9220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514248632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.514248632
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2529126587
Short name T115
Test name
Test status
Simulation time 559050528 ps
CPU time 1.76 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 199012 kb
Host smart-93be3e42-f4dc-4ef4-bdf3-c5ff60f75f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529126587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2529126587
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.396936381
Short name T629
Test name
Test status
Simulation time 155387897 ps
CPU time 1.3 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 199124 kb
Host smart-50ae787a-07e1-46f5-85d8-d76c0c5964fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396936381 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.396936381
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3620807499
Short name T679
Test name
Test status
Simulation time 42675854 ps
CPU time 0.78 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:43 PM PDT 24
Peak memory 198796 kb
Host smart-f497c75c-0b85-426c-a09d-6d465e764e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620807499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3620807499
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3184983534
Short name T649
Test name
Test status
Simulation time 63676959 ps
CPU time 0.61 seconds
Started Apr 23 02:34:42 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 193720 kb
Host smart-91b2f94b-ec04-4c86-aec4-4d29c6bf55cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184983534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3184983534
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.577953074
Short name T646
Test name
Test status
Simulation time 172100025 ps
CPU time 1.13 seconds
Started Apr 23 02:34:43 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 198048 kb
Host smart-b06aec3d-10b4-4545-b3cb-06621e2f0870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577953074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.577953074
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.448217976
Short name T641
Test name
Test status
Simulation time 31875972 ps
CPU time 1.66 seconds
Started Apr 23 02:34:43 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 199140 kb
Host smart-6204e343-6f9e-420c-91c3-1f12e059616d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448217976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.448217976
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3773918518
Short name T696
Test name
Test status
Simulation time 308387031 ps
CPU time 2.94 seconds
Started Apr 23 02:34:42 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 199040 kb
Host smart-25b35129-69d2-4200-a8ff-ca48ff8b6e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773918518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3773918518
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.270856069
Short name T615
Test name
Test status
Simulation time 74598042 ps
CPU time 1.08 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 198992 kb
Host smart-1ecd7a3a-d8a4-4542-b36f-e308cd5876b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270856069 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.270856069
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2444642292
Short name T689
Test name
Test status
Simulation time 29826634 ps
CPU time 0.91 seconds
Started Apr 23 02:34:45 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 198808 kb
Host smart-3052c65e-6ab4-4528-93d7-127d33dcfe76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444642292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2444642292
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4269185763
Short name T711
Test name
Test status
Simulation time 48978707 ps
CPU time 0.58 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 193728 kb
Host smart-d6cd58ff-5bd4-407e-9e64-fa4059e5bc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269185763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4269185763
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.26256551
Short name T651
Test name
Test status
Simulation time 94596536 ps
CPU time 2.2 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:47 PM PDT 24
Peak memory 198728 kb
Host smart-e90c51fe-22f9-4ccf-9243-b0df48929918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26256551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_o
utstanding.26256551
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1563219601
Short name T664
Test name
Test status
Simulation time 159785485 ps
CPU time 1.25 seconds
Started Apr 23 02:34:41 PM PDT 24
Finished Apr 23 02:34:44 PM PDT 24
Peak memory 199168 kb
Host smart-43df749e-43cc-41bd-a2cd-be8bdf5f69bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563219601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1563219601
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1660894242
Short name T685
Test name
Test status
Simulation time 230936695 ps
CPU time 4.15 seconds
Started Apr 23 02:34:40 PM PDT 24
Finished Apr 23 02:34:45 PM PDT 24
Peak memory 199080 kb
Host smart-75557af4-fb96-49a0-9cbe-e0744989b3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660894242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1660894242
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2507761116
Short name T608
Test name
Test status
Simulation time 35829447 ps
CPU time 1.14 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:06 PM PDT 24
Peak memory 198884 kb
Host smart-3adf82c1-2bca-4fed-bf10-9f0d695a4074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507761116 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2507761116
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2126079852
Short name T105
Test name
Test status
Simulation time 180971945 ps
CPU time 0.94 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 198424 kb
Host smart-827ceffd-58a3-49b1-a886-eb02766a0785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126079852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2126079852
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2282331148
Short name T713
Test name
Test status
Simulation time 40671345 ps
CPU time 0.54 seconds
Started Apr 23 02:34:46 PM PDT 24
Finished Apr 23 02:34:47 PM PDT 24
Peak memory 193680 kb
Host smart-f0eddfbc-eda5-4184-aa86-53a98dc8fc63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282331148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2282331148
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1257493158
Short name T657
Test name
Test status
Simulation time 60843226 ps
CPU time 1.2 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 198012 kb
Host smart-41569f7b-1af4-4be2-9f6d-94dfa675a7ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257493158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1257493158
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.402099162
Short name T622
Test name
Test status
Simulation time 251914057 ps
CPU time 3.13 seconds
Started Apr 23 02:34:45 PM PDT 24
Finished Apr 23 02:34:49 PM PDT 24
Peak memory 199184 kb
Host smart-4ed64f5a-e614-470b-9c13-604f3c77cee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402099162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.402099162
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1992037828
Short name T701
Test name
Test status
Simulation time 772045546 ps
CPU time 4.47 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:49 PM PDT 24
Peak memory 199060 kb
Host smart-6afe7767-fe1f-43ad-9833-85c339eb3010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992037828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1992037828
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2909933714
Short name T650
Test name
Test status
Simulation time 439390235 ps
CPU time 2.38 seconds
Started Apr 23 02:34:53 PM PDT 24
Finished Apr 23 02:34:56 PM PDT 24
Peak memory 199100 kb
Host smart-97184157-0877-42c2-9eb4-6bc279f8a289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909933714 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2909933714
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1304905312
Short name T604
Test name
Test status
Simulation time 14935503 ps
CPU time 0.79 seconds
Started Apr 23 02:34:45 PM PDT 24
Finished Apr 23 02:34:47 PM PDT 24
Peak memory 198080 kb
Host smart-54058716-51d5-4c61-bc42-75a9194ea4a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304905312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1304905312
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2307230048
Short name T658
Test name
Test status
Simulation time 15300203 ps
CPU time 0.61 seconds
Started Apr 23 02:34:45 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 193864 kb
Host smart-e12f7bc9-8c90-4ad8-8b31-4f2292a85ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307230048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2307230048
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2491526872
Short name T671
Test name
Test status
Simulation time 33787071 ps
CPU time 1.63 seconds
Started Apr 23 02:34:52 PM PDT 24
Finished Apr 23 02:34:55 PM PDT 24
Peak memory 199024 kb
Host smart-8fd5321e-cbb4-463d-b6d5-7bc39725665f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491526872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2491526872
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3338043260
Short name T686
Test name
Test status
Simulation time 181083746 ps
CPU time 1.37 seconds
Started Apr 23 02:34:44 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 199136 kb
Host smart-5b1848e9-abc7-4ad1-a6bf-eda158add464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338043260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3338043260
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3369011191
Short name T700
Test name
Test status
Simulation time 316629808 ps
CPU time 2.81 seconds
Started Apr 23 02:34:43 PM PDT 24
Finished Apr 23 02:34:47 PM PDT 24
Peak memory 199128 kb
Host smart-e8dbef03-75c1-4d2b-9b08-ac01a72a5190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369011191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3369011191
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3346496470
Short name T274
Test name
Test status
Simulation time 14699499 ps
CPU time 0.55 seconds
Started Apr 23 02:40:28 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 195136 kb
Host smart-0f12a72b-80a7-470f-8fc9-a9578838d2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346496470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3346496470
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3758474466
Short name T56
Test name
Test status
Simulation time 5236163152 ps
CPU time 47.95 seconds
Started Apr 23 02:40:19 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 222240 kb
Host smart-2bf4f568-a84c-4790-9560-f501e681bf42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758474466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3758474466
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.184165756
Short name T83
Test name
Test status
Simulation time 414490873 ps
CPU time 21.37 seconds
Started Apr 23 02:40:23 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 199616 kb
Host smart-3fb2d577-72e0-4ace-9dfd-d76c9b7bee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184165756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.184165756
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.695060991
Short name T138
Test name
Test status
Simulation time 1344748239 ps
CPU time 78 seconds
Started Apr 23 02:40:19 PM PDT 24
Finished Apr 23 02:41:37 PM PDT 24
Peak memory 199616 kb
Host smart-4936e3ca-bab5-4d03-b315-631fb5e696ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695060991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.695060991
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1804775619
Short name T525
Test name
Test status
Simulation time 28765984595 ps
CPU time 82.74 seconds
Started Apr 23 02:40:20 PM PDT 24
Finished Apr 23 02:41:43 PM PDT 24
Peak memory 199700 kb
Host smart-5cbf23a7-9d6e-4263-9ad4-bb04e5f1d61c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804775619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1804775619
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2725061548
Short name T45
Test name
Test status
Simulation time 406199515 ps
CPU time 4.14 seconds
Started Apr 23 02:40:19 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 199608 kb
Host smart-f228452f-50f4-455a-9031-b5b4cb041f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725061548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2725061548
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3396359803
Short name T42
Test name
Test status
Simulation time 211118705 ps
CPU time 0.81 seconds
Started Apr 23 02:40:24 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 218164 kb
Host smart-a710812f-4a96-45ef-aba2-1061700c26b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396359803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3396359803
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3868521135
Short name T184
Test name
Test status
Simulation time 211105358 ps
CPU time 3.46 seconds
Started Apr 23 02:40:19 PM PDT 24
Finished Apr 23 02:40:23 PM PDT 24
Peak memory 199560 kb
Host smart-410ce161-4cd6-40b8-b3b3-c02a974ced86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868521135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3868521135
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2259259957
Short name T444
Test name
Test status
Simulation time 12657947826 ps
CPU time 179.11 seconds
Started Apr 23 02:40:23 PM PDT 24
Finished Apr 23 02:43:22 PM PDT 24
Peak memory 199716 kb
Host smart-7e1a9525-f7eb-4c07-83c1-4393d9f87f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259259957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2259259957
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1924390819
Short name T539
Test name
Test status
Simulation time 43129528 ps
CPU time 1 seconds
Started Apr 23 02:40:21 PM PDT 24
Finished Apr 23 02:40:23 PM PDT 24
Peak memory 199188 kb
Host smart-f2b15f36-bae4-413d-b60b-a5081b3db0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924390819 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1924390819
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3965213254
Short name T16
Test name
Test status
Simulation time 728783899462 ps
CPU time 578.92 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:50:06 PM PDT 24
Peak memory 199744 kb
Host smart-e61a5fad-9bdb-4cf0-b247-442116b4593f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965213254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3965213254
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1410565147
Short name T449
Test name
Test status
Simulation time 2431478620 ps
CPU time 11.58 seconds
Started Apr 23 02:40:21 PM PDT 24
Finished Apr 23 02:40:33 PM PDT 24
Peak memory 199696 kb
Host smart-0035dfd4-19fe-4ee2-909f-c352054ba2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410565147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1410565147
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3076656575
Short name T135
Test name
Test status
Simulation time 33521957 ps
CPU time 0.55 seconds
Started Apr 23 02:40:28 PM PDT 24
Finished Apr 23 02:40:28 PM PDT 24
Peak memory 195124 kb
Host smart-22fb41b4-697e-4903-8eb7-bc7e71035434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076656575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3076656575
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1188494836
Short name T200
Test name
Test status
Simulation time 3513337914 ps
CPU time 18.73 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 224268 kb
Host smart-80e52fd5-5e5f-4fa8-9748-a91c4777fc43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188494836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1188494836
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.201542788
Short name T456
Test name
Test status
Simulation time 3401205195 ps
CPU time 16.83 seconds
Started Apr 23 02:40:27 PM PDT 24
Finished Apr 23 02:40:44 PM PDT 24
Peak memory 199716 kb
Host smart-f18c152f-cd3f-459b-8ded-d09ef252a396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201542788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.201542788
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3878191002
Short name T67
Test name
Test status
Simulation time 1589378908 ps
CPU time 90.24 seconds
Started Apr 23 02:40:27 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 199612 kb
Host smart-532b9e14-bf28-4a45-b454-10ba3994e73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878191002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3878191002
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1163811406
Short name T401
Test name
Test status
Simulation time 28700903831 ps
CPU time 251.89 seconds
Started Apr 23 02:40:25 PM PDT 24
Finished Apr 23 02:44:37 PM PDT 24
Peak memory 199756 kb
Host smart-3ec014f5-d2a5-4c5c-bdfc-ce43b71f8447
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163811406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1163811406
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1223577406
Short name T527
Test name
Test status
Simulation time 819986432 ps
CPU time 46.51 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:41:13 PM PDT 24
Peak memory 199576 kb
Host smart-c64bee1a-0c27-4a8a-a21b-0080c3ef89c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223577406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1223577406
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.591541689
Short name T39
Test name
Test status
Simulation time 35122177 ps
CPU time 0.83 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 218128 kb
Host smart-d5e3dd75-4eb3-42e5-b9c9-7fcc9240487d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591541689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.591541689
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2192566109
Short name T363
Test name
Test status
Simulation time 673872889 ps
CPU time 6.96 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:40:34 PM PDT 24
Peak memory 199640 kb
Host smart-5d77d5ec-e2c0-41c1-8170-c6b90de3ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192566109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2192566109
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1345167246
Short name T555
Test name
Test status
Simulation time 101515344114 ps
CPU time 1958.92 seconds
Started Apr 23 02:40:29 PM PDT 24
Finished Apr 23 03:13:09 PM PDT 24
Peak memory 207916 kb
Host smart-593143cc-98ef-476e-ba47-33780174b4b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345167246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1345167246
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.721972230
Short name T86
Test name
Test status
Simulation time 34885665 ps
CPU time 1.27 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 199556 kb
Host smart-e041bba2-4237-46ba-88cf-b69b83751baa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721972230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.721972230
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2424409209
Short name T467
Test name
Test status
Simulation time 7452505028 ps
CPU time 401.29 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:47:08 PM PDT 24
Peak memory 199696 kb
Host smart-c0199db3-0203-4d60-8440-cd31f6b08bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424409209 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2424409209
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4236551775
Short name T210
Test name
Test status
Simulation time 5984305471 ps
CPU time 39.14 seconds
Started Apr 23 02:40:26 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 199688 kb
Host smart-6af99c6f-44fd-4673-b048-84acd8da0d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236551775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4236551775
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1047227925
Short name T23
Test name
Test status
Simulation time 23512774 ps
CPU time 0.57 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:40:56 PM PDT 24
Peak memory 195172 kb
Host smart-4f3c7f55-bd10-4147-bdda-9e305c78a724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047227925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1047227925
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3457083977
Short name T241
Test name
Test status
Simulation time 2959095562 ps
CPU time 51.08 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:41:48 PM PDT 24
Peak memory 215240 kb
Host smart-88660924-5a66-49ac-b4ee-6b646ac5da2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457083977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3457083977
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3418701905
Short name T485
Test name
Test status
Simulation time 2727193967 ps
CPU time 18.65 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:41:14 PM PDT 24
Peak memory 199664 kb
Host smart-dded8281-1399-4a84-bc81-42336710d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418701905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3418701905
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3428105998
Short name T315
Test name
Test status
Simulation time 425388109 ps
CPU time 11.68 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:41:08 PM PDT 24
Peak memory 199556 kb
Host smart-bfa1ffe7-23a7-4666-8257-ff727ccd43fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428105998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3428105998
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3401384552
Short name T378
Test name
Test status
Simulation time 348222332 ps
CPU time 8.88 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 199532 kb
Host smart-84cd3c1c-ec63-4f67-95b6-ce575aba17d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401384552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3401384552
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.824861657
Short name T420
Test name
Test status
Simulation time 8792802080 ps
CPU time 78.96 seconds
Started Apr 23 02:40:58 PM PDT 24
Finished Apr 23 02:42:17 PM PDT 24
Peak memory 199652 kb
Host smart-a51ef9e1-725d-4b09-99e6-b0d17bce4dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824861657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.824861657
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.947645827
Short name T344
Test name
Test status
Simulation time 89357320 ps
CPU time 1.4 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:40:56 PM PDT 24
Peak memory 199612 kb
Host smart-0435b74d-34d4-453f-ab88-9aef883533b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947645827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.947645827
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2501659824
Short name T78
Test name
Test status
Simulation time 502099125640 ps
CPU time 1811.79 seconds
Started Apr 23 02:40:59 PM PDT 24
Finished Apr 23 03:11:11 PM PDT 24
Peak memory 231608 kb
Host smart-43226dff-ea39-4f8e-ab1b-837ff8e09ec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501659824 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2501659824
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3498296237
Short name T546
Test name
Test status
Simulation time 54628902 ps
CPU time 1.05 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:40:56 PM PDT 24
Peak memory 199220 kb
Host smart-82f8bf5b-3aad-40a8-b12a-47f9f4efea9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498296237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3498296237
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3123217475
Short name T547
Test name
Test status
Simulation time 30827811506 ps
CPU time 429.45 seconds
Started Apr 23 02:40:57 PM PDT 24
Finished Apr 23 02:48:07 PM PDT 24
Peak memory 199676 kb
Host smart-9a6e0ee3-4f22-4f24-8b5b-fb175b612e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123217475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3123217475
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3904188245
Short name T383
Test name
Test status
Simulation time 27979855740 ps
CPU time 90.62 seconds
Started Apr 23 02:40:57 PM PDT 24
Finished Apr 23 02:42:28 PM PDT 24
Peak memory 199656 kb
Host smart-df3362f7-bb60-4bbb-bb6b-080b0e4b79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904188245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3904188245
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1446895074
Short name T227
Test name
Test status
Simulation time 86786440 ps
CPU time 0.58 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 02:41:01 PM PDT 24
Peak memory 194960 kb
Host smart-9ab4aa95-f102-4330-b75f-1436c1061d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446895074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1446895074
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2919237854
Short name T548
Test name
Test status
Simulation time 4685242988 ps
CPU time 38.62 seconds
Started Apr 23 02:40:58 PM PDT 24
Finished Apr 23 02:41:37 PM PDT 24
Peak memory 215860 kb
Host smart-2e58259a-2767-4879-a040-8a85657e81fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919237854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2919237854
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3729726229
Short name T462
Test name
Test status
Simulation time 3448428135 ps
CPU time 17.26 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 199676 kb
Host smart-8ae3f508-edb9-45a0-b864-329a1d9c9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729726229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3729726229
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.653755082
Short name T259
Test name
Test status
Simulation time 6152059620 ps
CPU time 192.94 seconds
Started Apr 23 02:41:01 PM PDT 24
Finished Apr 23 02:44:14 PM PDT 24
Peak memory 199692 kb
Host smart-2112e495-c466-4b7d-ad1e-9becc42eb6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653755082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.653755082
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2443591813
Short name T317
Test name
Test status
Simulation time 736695118 ps
CPU time 10 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 02:41:10 PM PDT 24
Peak memory 199568 kb
Host smart-8e9c27e0-bbab-4bec-9749-98081ced06a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443591813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2443591813
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.129745100
Short name T44
Test name
Test status
Simulation time 8649402786 ps
CPU time 134.54 seconds
Started Apr 23 02:40:59 PM PDT 24
Finished Apr 23 02:43:14 PM PDT 24
Peak memory 199676 kb
Host smart-30544c76-07b0-418a-9e71-0e9d362a048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129745100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.129745100
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2768700544
Short name T338
Test name
Test status
Simulation time 1973935579 ps
CPU time 6.41 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:41:03 PM PDT 24
Peak memory 199612 kb
Host smart-07a54f22-ae0a-4c7a-87b4-36cf884f9efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768700544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2768700544
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3249773731
Short name T461
Test name
Test status
Simulation time 60655278 ps
CPU time 1.86 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:41:05 PM PDT 24
Peak memory 199604 kb
Host smart-128d781c-e479-4312-8a53-170e21439aa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249773731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3249773731
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2158038683
Short name T124
Test name
Test status
Simulation time 32197947 ps
CPU time 1.14 seconds
Started Apr 23 02:40:58 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 199528 kb
Host smart-4b1628a3-348d-4948-bf71-0640abc4dabb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158038683 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2158038683
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3932430058
Short name T132
Test name
Test status
Simulation time 126751459475 ps
CPU time 502.35 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 02:49:23 PM PDT 24
Peak memory 199696 kb
Host smart-1439d32a-04cf-46b5-b3c9-1aa2be71d724
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932430058 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3932430058
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2720664892
Short name T267
Test name
Test status
Simulation time 5938357059 ps
CPU time 55.35 seconds
Started Apr 23 02:40:59 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 199736 kb
Host smart-e7ad5d6e-16c3-461e-88ad-d6619be7bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720664892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2720664892
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.3872999872
Short name T20
Test name
Test status
Simulation time 68065188729 ps
CPU time 2058.72 seconds
Started Apr 23 02:43:33 PM PDT 24
Finished Apr 23 03:17:53 PM PDT 24
Peak memory 244672 kb
Host smart-4b3923fb-af53-416b-b41a-f9d19b7d58d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872999872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.3872999872
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2935969785
Short name T360
Test name
Test status
Simulation time 38999959 ps
CPU time 0.55 seconds
Started Apr 23 02:40:58 PM PDT 24
Finished Apr 23 02:40:59 PM PDT 24
Peak memory 194884 kb
Host smart-e069378d-cad8-403a-8fc1-ec4ffee880ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935969785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2935969785
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1957509539
Short name T398
Test name
Test status
Simulation time 1768858329 ps
CPU time 66.68 seconds
Started Apr 23 02:40:58 PM PDT 24
Finished Apr 23 02:42:06 PM PDT 24
Peak memory 222112 kb
Host smart-59322cdd-798d-4b53-909d-d02fe741bff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957509539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1957509539
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3508387326
Short name T537
Test name
Test status
Simulation time 12119476455 ps
CPU time 27.77 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 02:41:28 PM PDT 24
Peak memory 199672 kb
Host smart-514a3789-92ee-4def-b5a7-30169e1e1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508387326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3508387326
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1924750423
Short name T450
Test name
Test status
Simulation time 5522672455 ps
CPU time 149.31 seconds
Started Apr 23 02:40:57 PM PDT 24
Finished Apr 23 02:43:27 PM PDT 24
Peak memory 199740 kb
Host smart-8f1d2350-dc4d-47f4-b084-b286b7f01043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924750423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1924750423
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1793750075
Short name T213
Test name
Test status
Simulation time 9446183024 ps
CPU time 129.97 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:43:13 PM PDT 24
Peak memory 199656 kb
Host smart-72ee6f40-d7ad-4245-bd68-787f371fce2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793750075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1793750075
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.525529488
Short name T556
Test name
Test status
Simulation time 16496703396 ps
CPU time 67.29 seconds
Started Apr 23 02:40:59 PM PDT 24
Finished Apr 23 02:42:07 PM PDT 24
Peak memory 199720 kb
Host smart-e5d905a6-0335-4203-b00e-c3d87ad9c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525529488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.525529488
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3826941239
Short name T357
Test name
Test status
Simulation time 382883836 ps
CPU time 4.59 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 199544 kb
Host smart-24913dd2-9c7f-449b-8fed-7ecadf77f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826941239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3826941239
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3637643066
Short name T577
Test name
Test status
Simulation time 108644177685 ps
CPU time 1915.09 seconds
Started Apr 23 02:41:00 PM PDT 24
Finished Apr 23 03:12:55 PM PDT 24
Peak memory 207924 kb
Host smart-9d1171d5-5e76-4365-83ee-b6a04f0208fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637643066 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3637643066
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1218147582
Short name T342
Test name
Test status
Simulation time 178052515 ps
CPU time 1.06 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:41:04 PM PDT 24
Peak memory 198852 kb
Host smart-1344fc46-f848-4b1f-924f-26c0b186f122
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218147582 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1218147582
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.4276536201
Short name T538
Test name
Test status
Simulation time 7774575567 ps
CPU time 406.44 seconds
Started Apr 23 02:40:59 PM PDT 24
Finished Apr 23 02:47:46 PM PDT 24
Peak memory 199656 kb
Host smart-a4c0e755-169a-43d4-be1c-3c8fcbef7488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276536201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.4276536201
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1935885526
Short name T418
Test name
Test status
Simulation time 5798153708 ps
CPU time 82.36 seconds
Started Apr 23 02:41:01 PM PDT 24
Finished Apr 23 02:42:24 PM PDT 24
Peak memory 199672 kb
Host smart-27b9dddc-1b1d-4b1a-b07b-14ee6feaac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935885526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1935885526
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.2918622887
Short name T455
Test name
Test status
Simulation time 125259117682 ps
CPU time 1111.69 seconds
Started Apr 23 02:43:38 PM PDT 24
Finished Apr 23 03:02:10 PM PDT 24
Peak memory 241796 kb
Host smart-b5a436cd-9902-40a9-bfce-d8c4be9a1ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918622887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.2918622887
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1361637636
Short name T326
Test name
Test status
Simulation time 35726300 ps
CPU time 0.56 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:41:02 PM PDT 24
Peak memory 195212 kb
Host smart-89f88c4b-3619-4594-9914-54e263bb1761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361637636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1361637636
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.4178111637
Short name T214
Test name
Test status
Simulation time 1623556517 ps
CPU time 41.79 seconds
Started Apr 23 02:41:06 PM PDT 24
Finished Apr 23 02:41:49 PM PDT 24
Peak memory 215416 kb
Host smart-3f0efdcb-a349-4815-bdd8-9a8339e0e069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178111637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4178111637
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.966915077
Short name T278
Test name
Test status
Simulation time 657077586 ps
CPU time 3.08 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 199532 kb
Host smart-cc6482b7-146d-444e-b934-f2013b5c6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966915077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.966915077
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1112060280
Short name T511
Test name
Test status
Simulation time 886965417 ps
CPU time 51.62 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 199584 kb
Host smart-f36d1c49-4d13-4cdf-a424-4397251e62e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112060280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1112060280
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.823417370
Short name T310
Test name
Test status
Simulation time 7562839851 ps
CPU time 106.62 seconds
Started Apr 23 02:41:01 PM PDT 24
Finished Apr 23 02:42:48 PM PDT 24
Peak memory 199720 kb
Host smart-c9118397-eb7a-4d17-98bd-5d4d16b09d66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823417370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.823417370
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.799995894
Short name T148
Test name
Test status
Simulation time 27505729232 ps
CPU time 93.41 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:42:36 PM PDT 24
Peak memory 199672 kb
Host smart-c5e40878-3b8f-4660-b3e5-9a1272d20a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799995894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.799995894
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2438895727
Short name T468
Test name
Test status
Simulation time 277120293 ps
CPU time 2.15 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 199592 kb
Host smart-974bf07a-7ca7-43c4-9410-80d23d04a883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438895727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2438895727
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.853114270
Short name T584
Test name
Test status
Simulation time 83424948 ps
CPU time 1.05 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:41:03 PM PDT 24
Peak memory 198788 kb
Host smart-2570f704-bf44-4581-96b3-5bce172c8da5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853114270 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.853114270
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3776581372
Short name T72
Test name
Test status
Simulation time 18229584692 ps
CPU time 431.99 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:48:16 PM PDT 24
Peak memory 199728 kb
Host smart-12904f8a-661f-4de1-97f1-ae3560f316f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776581372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3776581372
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2986124928
Short name T130
Test name
Test status
Simulation time 1957879323 ps
CPU time 24.43 seconds
Started Apr 23 02:41:04 PM PDT 24
Finished Apr 23 02:41:29 PM PDT 24
Peak memory 199556 kb
Host smart-4078ce5a-5484-4662-8091-5047c2329edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986124928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2986124928
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4139091516
Short name T266
Test name
Test status
Simulation time 36273515 ps
CPU time 0.65 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 194972 kb
Host smart-2d79bc45-3073-47f8-a4b0-edf7822b6c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139091516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4139091516
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.222234072
Short name T586
Test name
Test status
Simulation time 964376399 ps
CPU time 33.37 seconds
Started Apr 23 02:41:04 PM PDT 24
Finished Apr 23 02:41:38 PM PDT 24
Peak memory 215972 kb
Host smart-faea2e19-b153-4f87-b0c4-c11b33e5f07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222234072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.222234072
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3732090894
Short name T47
Test name
Test status
Simulation time 807142387 ps
CPU time 11.28 seconds
Started Apr 23 02:41:07 PM PDT 24
Finished Apr 23 02:41:19 PM PDT 24
Peak memory 199536 kb
Host smart-070657ab-d5c3-43d7-8069-320a9ec59673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732090894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3732090894
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1641587340
Short name T258
Test name
Test status
Simulation time 1124868572 ps
CPU time 5.67 seconds
Started Apr 23 02:41:02 PM PDT 24
Finished Apr 23 02:41:08 PM PDT 24
Peak memory 199536 kb
Host smart-88125ffe-aba7-4112-9de0-c17402517441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641587340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1641587340
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1511284361
Short name T500
Test name
Test status
Simulation time 3197039971 ps
CPU time 16.31 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 02:41:22 PM PDT 24
Peak memory 199736 kb
Host smart-c9cdf122-d7a1-44f9-b6ec-eb3e821eebd3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511284361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1511284361
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2090216311
Short name T89
Test name
Test status
Simulation time 5714489175 ps
CPU time 87.1 seconds
Started Apr 23 02:41:04 PM PDT 24
Finished Apr 23 02:42:32 PM PDT 24
Peak memory 199728 kb
Host smart-fc3c3d76-2353-429c-b587-b391f405a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090216311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2090216311
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2736185496
Short name T440
Test name
Test status
Simulation time 1380622911 ps
CPU time 1.76 seconds
Started Apr 23 02:41:03 PM PDT 24
Finished Apr 23 02:41:05 PM PDT 24
Peak memory 199592 kb
Host smart-16a146d8-833f-4dff-9a71-715a0422b0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736185496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2736185496
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3293752425
Short name T490
Test name
Test status
Simulation time 129291261779 ps
CPU time 1144.55 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 03:00:11 PM PDT 24
Peak memory 199708 kb
Host smart-ec1bfe9a-9f97-45a8-a855-587d38e97a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293752425 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3293752425
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2711490643
Short name T170
Test name
Test status
Simulation time 44166447 ps
CPU time 0.99 seconds
Started Apr 23 02:41:06 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 197956 kb
Host smart-1d64cd4f-bf5d-4f35-bf08-e3d747b699f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711490643 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2711490643
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1668266036
Short name T550
Test name
Test status
Simulation time 17140212187 ps
CPU time 472.67 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 199608 kb
Host smart-18c8ab17-0a08-48d4-be21-653b8bd1d992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668266036 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1668266036
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4290554229
Short name T177
Test name
Test status
Simulation time 4628744071 ps
CPU time 68.6 seconds
Started Apr 23 02:41:06 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199732 kb
Host smart-6db32b6b-03d0-4af2-b739-58d99ae33c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290554229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4290554229
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.1570636651
Short name T301
Test name
Test status
Simulation time 28696108017 ps
CPU time 231.59 seconds
Started Apr 23 02:43:45 PM PDT 24
Finished Apr 23 02:47:38 PM PDT 24
Peak memory 248188 kb
Host smart-99e1a9cc-3bf3-4648-8fba-fd65ff156a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570636651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.1570636651
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2371279835
Short name T470
Test name
Test status
Simulation time 123912653 ps
CPU time 0.59 seconds
Started Apr 23 02:41:09 PM PDT 24
Finished Apr 23 02:41:10 PM PDT 24
Peak memory 194888 kb
Host smart-9c64749a-683b-45f4-8272-6362ccc0a6ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371279835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2371279835
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.837290265
Short name T459
Test name
Test status
Simulation time 2134214809 ps
CPU time 19.32 seconds
Started Apr 23 02:41:05 PM PDT 24
Finished Apr 23 02:41:24 PM PDT 24
Peak memory 223096 kb
Host smart-8edc5ffe-80da-4410-bd51-0fade55e1e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837290265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.837290265
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3047223393
Short name T551
Test name
Test status
Simulation time 1377204722 ps
CPU time 64.88 seconds
Started Apr 23 02:41:10 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199564 kb
Host smart-de6c6605-7bae-41e2-9175-0358de6d0c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047223393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3047223393
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1332678921
Short name T141
Test name
Test status
Simulation time 229419227 ps
CPU time 11.21 seconds
Started Apr 23 02:41:09 PM PDT 24
Finished Apr 23 02:41:21 PM PDT 24
Peak memory 199604 kb
Host smart-9bff017a-744d-4946-9f72-e2fabd25b67d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332678921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1332678921
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.553275552
Short name T343
Test name
Test status
Simulation time 761457955 ps
CPU time 39.74 seconds
Started Apr 23 02:41:09 PM PDT 24
Finished Apr 23 02:41:49 PM PDT 24
Peak memory 199616 kb
Host smart-1dc7d2e6-901d-436f-8fdf-b386669f1336
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553275552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.553275552
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.16581648
Short name T549
Test name
Test status
Simulation time 405381190 ps
CPU time 22.48 seconds
Started Apr 23 02:41:06 PM PDT 24
Finished Apr 23 02:41:29 PM PDT 24
Peak memory 199600 kb
Host smart-e94803ae-6d27-45cd-a451-81ebdd5d5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16581648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.16581648
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.917738618
Short name T598
Test name
Test status
Simulation time 260129899 ps
CPU time 4.03 seconds
Started Apr 23 02:41:09 PM PDT 24
Finished Apr 23 02:41:14 PM PDT 24
Peak memory 199612 kb
Host smart-0af9b778-678b-43e3-b31e-0a3d60f4633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917738618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.917738618
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.310650937
Short name T324
Test name
Test status
Simulation time 13889358197 ps
CPU time 706.46 seconds
Started Apr 23 02:41:10 PM PDT 24
Finished Apr 23 02:52:57 PM PDT 24
Peak memory 199724 kb
Host smart-48b96c56-0e23-48de-9278-b2f957c76e8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310650937 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.310650937
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2468941531
Short name T218
Test name
Test status
Simulation time 134245928 ps
CPU time 1.3 seconds
Started Apr 23 02:41:09 PM PDT 24
Finished Apr 23 02:41:11 PM PDT 24
Peak memory 199636 kb
Host smart-09915091-892e-4d7f-a36d-2696267494ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468941531 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2468941531
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.476237443
Short name T348
Test name
Test status
Simulation time 7150383736 ps
CPU time 396.33 seconds
Started Apr 23 02:41:08 PM PDT 24
Finished Apr 23 02:47:45 PM PDT 24
Peak memory 199616 kb
Host smart-daa26587-ff25-4832-8ed3-c5471f0ec655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476237443 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.476237443
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1333879083
Short name T173
Test name
Test status
Simulation time 9695134737 ps
CPU time 42 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:41:53 PM PDT 24
Peak memory 199748 kb
Host smart-ce088fda-b893-4992-9c77-6138d804452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333879083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1333879083
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1635550051
Short name T49
Test name
Test status
Simulation time 12992044492 ps
CPU time 610.81 seconds
Started Apr 23 02:43:49 PM PDT 24
Finished Apr 23 02:54:00 PM PDT 24
Peak memory 224380 kb
Host smart-6db07c53-bef8-476d-a41e-a8f8aa16fcc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635550051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.1635550051
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.2554316201
Short name T4
Test name
Test status
Simulation time 86714270177 ps
CPU time 1033.28 seconds
Started Apr 23 02:43:53 PM PDT 24
Finished Apr 23 03:01:07 PM PDT 24
Peak memory 248284 kb
Host smart-012d7df7-308c-4fb5-93d9-096532d28f7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554316201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.2554316201
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2604176169
Short name T186
Test name
Test status
Simulation time 56030327 ps
CPU time 0.53 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:41:12 PM PDT 24
Peak memory 194272 kb
Host smart-5bc4ea7a-dedb-4468-b1ae-b1f63559ffb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604176169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2604176169
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2071859952
Short name T3
Test name
Test status
Simulation time 4042548935 ps
CPU time 72.13 seconds
Started Apr 23 02:41:07 PM PDT 24
Finished Apr 23 02:42:19 PM PDT 24
Peak memory 224324 kb
Host smart-23df9b51-727b-4d1d-a04e-37a1fd7639e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071859952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2071859952
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2454834399
Short name T279
Test name
Test status
Simulation time 3621865310 ps
CPU time 51.91 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:42:04 PM PDT 24
Peak memory 199700 kb
Host smart-8a80c3ba-8d81-4042-848a-3725d476b3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454834399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2454834399
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.890504098
Short name T370
Test name
Test status
Simulation time 3292077864 ps
CPU time 48.74 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 199712 kb
Host smart-61667877-f0b3-4a59-95c5-2e192274e382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890504098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.890504098
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.230222331
Short name T486
Test name
Test status
Simulation time 23918914334 ps
CPU time 75.2 seconds
Started Apr 23 02:41:13 PM PDT 24
Finished Apr 23 02:42:28 PM PDT 24
Peak memory 199672 kb
Host smart-78b0c618-2abb-433f-a23b-5719b8630f3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230222331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.230222331
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.191526445
Short name T386
Test name
Test status
Simulation time 802534470 ps
CPU time 3.73 seconds
Started Apr 23 02:41:10 PM PDT 24
Finished Apr 23 02:41:14 PM PDT 24
Peak memory 199556 kb
Host smart-9c9dac63-f5c1-4ad8-809a-1c45194f9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191526445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.191526445
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1663024169
Short name T453
Test name
Test status
Simulation time 312324898 ps
CPU time 4 seconds
Started Apr 23 02:41:10 PM PDT 24
Finished Apr 23 02:41:14 PM PDT 24
Peak memory 199568 kb
Host smart-ed9cc4d0-d0a8-4eda-89b6-6c67fd42d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663024169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1663024169
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2638258601
Short name T233
Test name
Test status
Simulation time 333808438941 ps
CPU time 1461.81 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 03:05:36 PM PDT 24
Peak memory 206856 kb
Host smart-27ad9ae4-f2fc-4de0-acab-1cd244dfc163
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638258601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2638258601
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2136217289
Short name T411
Test name
Test status
Simulation time 822313201 ps
CPU time 1.05 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:41:15 PM PDT 24
Peak memory 199176 kb
Host smart-7dc7aa22-7d2b-4de7-a910-b9ec9c887c27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136217289 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2136217289
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2359667601
Short name T1
Test name
Test status
Simulation time 17650800347 ps
CPU time 475.23 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:49:07 PM PDT 24
Peak memory 199620 kb
Host smart-fa3a6aab-e0b3-49f8-a0dd-92b794fe3e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359667601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2359667601
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.509125691
Short name T366
Test name
Test status
Simulation time 27403562547 ps
CPU time 82.13 seconds
Started Apr 23 02:41:11 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 199680 kb
Host smart-348d14bd-d4b6-412a-9d9a-61028a66f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509125691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.509125691
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1151393027
Short name T9
Test name
Test status
Simulation time 7271256277 ps
CPU time 200.65 seconds
Started Apr 23 02:43:53 PM PDT 24
Finished Apr 23 02:47:14 PM PDT 24
Peak memory 243976 kb
Host smart-caf31826-f194-4a62-a5d1-e39f897aa9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151393027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1151393027
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1232356731
Short name T414
Test name
Test status
Simulation time 15085808 ps
CPU time 0.64 seconds
Started Apr 23 02:41:17 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 195344 kb
Host smart-4ee26e6c-660a-49b4-9899-61e5fd29d74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232356731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1232356731
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2737093646
Short name T443
Test name
Test status
Simulation time 1704608768 ps
CPU time 12.34 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:41:27 PM PDT 24
Peak memory 225220 kb
Host smart-8339b248-2c4d-4cf5-83f8-a85401fd0044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737093646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2737093646
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2764553632
Short name T518
Test name
Test status
Simulation time 2236409084 ps
CPU time 54.75 seconds
Started Apr 23 02:41:13 PM PDT 24
Finished Apr 23 02:42:09 PM PDT 24
Peak memory 199640 kb
Host smart-719fc8af-7917-45c5-8f88-215d631008d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764553632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2764553632
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.878777628
Short name T38
Test name
Test status
Simulation time 5038588787 ps
CPU time 151.33 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:43:46 PM PDT 24
Peak memory 199704 kb
Host smart-7d9dcfc0-3481-4da5-881c-86b0bf9f6486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878777628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.878777628
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3042616369
Short name T316
Test name
Test status
Simulation time 9614264933 ps
CPU time 92.68 seconds
Started Apr 23 02:41:13 PM PDT 24
Finished Apr 23 02:42:47 PM PDT 24
Peak memory 199728 kb
Host smart-95ff032d-3cdd-497e-8bfa-cc5ea4f233f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042616369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3042616369
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.893020348
Short name T347
Test name
Test status
Simulation time 1159298065 ps
CPU time 66.84 seconds
Started Apr 23 02:41:15 PM PDT 24
Finished Apr 23 02:42:22 PM PDT 24
Peak memory 199584 kb
Host smart-302997f9-231c-4456-b7d6-43cb9ce046f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893020348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.893020348
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2674794913
Short name T247
Test name
Test status
Simulation time 1028320261 ps
CPU time 4.04 seconds
Started Apr 23 02:41:12 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 199544 kb
Host smart-bd04b0ce-a60e-4a24-a5d4-4e7634722eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674794913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2674794913
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2364946255
Short name T435
Test name
Test status
Simulation time 172571584760 ps
CPU time 868.05 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:55:42 PM PDT 24
Peak memory 207904 kb
Host smart-e5942ce5-8ff3-4199-9ad8-b2adff3878a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364946255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2364946255
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2191623526
Short name T492
Test name
Test status
Simulation time 119441174 ps
CPU time 1.28 seconds
Started Apr 23 02:41:15 PM PDT 24
Finished Apr 23 02:41:17 PM PDT 24
Peak memory 199496 kb
Host smart-49cf3187-4d36-410b-b4f0-d44c40cc53b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191623526 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2191623526
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.317523437
Short name T340
Test name
Test status
Simulation time 34949312330 ps
CPU time 460.69 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:48:55 PM PDT 24
Peak memory 198684 kb
Host smart-cf72fce0-e89a-4d9a-b966-8ca8a4c0ebc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317523437 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.317523437
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3137938823
Short name T88
Test name
Test status
Simulation time 16226162991 ps
CPU time 76.66 seconds
Started Apr 23 02:41:14 PM PDT 24
Finished Apr 23 02:42:31 PM PDT 24
Peak memory 199700 kb
Host smart-ae82130a-64b2-4e30-81f1-a13ecbe23670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137938823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3137938823
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1776752194
Short name T87
Test name
Test status
Simulation time 28356644 ps
CPU time 0.58 seconds
Started Apr 23 02:41:18 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 195232 kb
Host smart-42302dd6-ebca-466e-b0b4-29ce7148b37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776752194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1776752194
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.201263304
Short name T515
Test name
Test status
Simulation time 588426127 ps
CPU time 21.52 seconds
Started Apr 23 02:41:15 PM PDT 24
Finished Apr 23 02:41:37 PM PDT 24
Peak memory 218004 kb
Host smart-0cd29d93-c861-4f5b-8d47-6129cbe61cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201263304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.201263304
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2615220647
Short name T143
Test name
Test status
Simulation time 4765678495 ps
CPU time 47.73 seconds
Started Apr 23 02:41:16 PM PDT 24
Finished Apr 23 02:42:04 PM PDT 24
Peak memory 199652 kb
Host smart-2e1dd9e0-0150-4b18-8b84-7b4b88063ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615220647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2615220647
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3049027929
Short name T319
Test name
Test status
Simulation time 4212118971 ps
CPU time 108.45 seconds
Started Apr 23 02:41:16 PM PDT 24
Finished Apr 23 02:43:04 PM PDT 24
Peak memory 199728 kb
Host smart-9e472a78-b21d-4c98-bc8d-3f5f7749b54f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049027929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3049027929
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.326851712
Short name T483
Test name
Test status
Simulation time 6965179782 ps
CPU time 122.2 seconds
Started Apr 23 02:41:18 PM PDT 24
Finished Apr 23 02:43:21 PM PDT 24
Peak memory 199736 kb
Host smart-eda80745-6867-4c39-aa6a-b74463a87902
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326851712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.326851712
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1778926799
Short name T26
Test name
Test status
Simulation time 8899906940 ps
CPU time 67.07 seconds
Started Apr 23 02:41:16 PM PDT 24
Finished Apr 23 02:42:24 PM PDT 24
Peak memory 199688 kb
Host smart-d8ac4796-106c-4b00-9cd7-46a8e9ed2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778926799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1778926799
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1090824781
Short name T331
Test name
Test status
Simulation time 590668482 ps
CPU time 4.39 seconds
Started Apr 23 02:41:19 PM PDT 24
Finished Apr 23 02:41:24 PM PDT 24
Peak memory 199616 kb
Host smart-a4beecb7-a5a7-4dfa-93ba-8f59c001a54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090824781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1090824781
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3301211064
Short name T313
Test name
Test status
Simulation time 22527531326 ps
CPU time 597.75 seconds
Started Apr 23 02:41:16 PM PDT 24
Finished Apr 23 02:51:14 PM PDT 24
Peak memory 233996 kb
Host smart-6b098d43-35d4-4595-b01e-32d600b459e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301211064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3301211064
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.219134664
Short name T585
Test name
Test status
Simulation time 749623745 ps
CPU time 1.43 seconds
Started Apr 23 02:41:16 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 199492 kb
Host smart-43e048a0-3687-42a5-920e-224035e3c68d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219134664 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.219134664
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1647257040
Short name T70
Test name
Test status
Simulation time 73069634428 ps
CPU time 468.37 seconds
Started Apr 23 02:41:19 PM PDT 24
Finished Apr 23 02:49:07 PM PDT 24
Peak memory 199724 kb
Host smart-01da3f3e-0cd6-4c47-9222-e4cd00f92760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647257040 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1647257040
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.448243748
Short name T451
Test name
Test status
Simulation time 7826433355 ps
CPU time 69.66 seconds
Started Apr 23 02:41:15 PM PDT 24
Finished Apr 23 02:42:25 PM PDT 24
Peak memory 199700 kb
Host smart-4b237c11-0262-4878-ac3d-70040e05e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448243748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.448243748
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.3934198578
Short name T100
Test name
Test status
Simulation time 31720535110 ps
CPU time 1451.73 seconds
Started Apr 23 02:44:02 PM PDT 24
Finished Apr 23 03:08:14 PM PDT 24
Peak memory 241740 kb
Host smart-d7d3e0b7-7eff-42b1-a0eb-f5aa2095dd53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3934198578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.3934198578
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3132251282
Short name T592
Test name
Test status
Simulation time 31964200 ps
CPU time 0.57 seconds
Started Apr 23 02:41:23 PM PDT 24
Finished Apr 23 02:41:23 PM PDT 24
Peak memory 195264 kb
Host smart-df6412e9-e7a8-4cbf-b07f-67aa992123e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132251282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3132251282
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.962434497
Short name T365
Test name
Test status
Simulation time 1585112050 ps
CPU time 27.76 seconds
Started Apr 23 02:41:21 PM PDT 24
Finished Apr 23 02:41:49 PM PDT 24
Peak memory 199624 kb
Host smart-1b6eb1dc-36f8-4db8-9885-36ac753cbb0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962434497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.962434497
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3500237084
Short name T328
Test name
Test status
Simulation time 3716201991 ps
CPU time 27.58 seconds
Started Apr 23 02:41:18 PM PDT 24
Finished Apr 23 02:41:46 PM PDT 24
Peak memory 199636 kb
Host smart-fe5da4c6-718d-4769-a81c-9f03c85ad812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500237084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3500237084
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2753501866
Short name T283
Test name
Test status
Simulation time 6537069806 ps
CPU time 83.52 seconds
Started Apr 23 02:41:19 PM PDT 24
Finished Apr 23 02:42:43 PM PDT 24
Peak memory 199708 kb
Host smart-c6dbc0a4-33ce-4d02-a9d4-fd664175ef6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753501866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2753501866
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2848525683
Short name T154
Test name
Test status
Simulation time 8833392066 ps
CPU time 122.45 seconds
Started Apr 23 02:41:18 PM PDT 24
Finished Apr 23 02:43:21 PM PDT 24
Peak memory 199704 kb
Host smart-dfcb6c6f-a7f3-4a4e-9cce-4e1732dc8c24
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848525683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2848525683
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1090794095
Short name T240
Test name
Test status
Simulation time 280073247 ps
CPU time 15.6 seconds
Started Apr 23 02:41:20 PM PDT 24
Finished Apr 23 02:41:36 PM PDT 24
Peak memory 199544 kb
Host smart-3db4495a-82d2-4857-98c8-95b2184f7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090794095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1090794095
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3064787599
Short name T234
Test name
Test status
Simulation time 2047707381 ps
CPU time 6.4 seconds
Started Apr 23 02:41:21 PM PDT 24
Finished Apr 23 02:41:28 PM PDT 24
Peak memory 199616 kb
Host smart-a853d46a-9d22-4031-b833-f6616918c100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064787599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3064787599
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1272622302
Short name T436
Test name
Test status
Simulation time 44964982407 ps
CPU time 835.07 seconds
Started Apr 23 02:41:22 PM PDT 24
Finished Apr 23 02:55:18 PM PDT 24
Peak memory 216092 kb
Host smart-3647109d-1b38-43c3-8f91-6d438ae882f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272622302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1272622302
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.465667709
Short name T323
Test name
Test status
Simulation time 145682295 ps
CPU time 1 seconds
Started Apr 23 02:41:21 PM PDT 24
Finished Apr 23 02:41:22 PM PDT 24
Peak memory 198168 kb
Host smart-da886d9f-2368-4b75-903b-21840b49eb28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465667709 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.465667709
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.175094172
Short name T48
Test name
Test status
Simulation time 30526382520 ps
CPU time 434.49 seconds
Started Apr 23 02:41:20 PM PDT 24
Finished Apr 23 02:48:34 PM PDT 24
Peak memory 199688 kb
Host smart-ff72cac6-d7c5-46cf-aa64-f48c464944f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175094172 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.175094172
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2231380406
Short name T589
Test name
Test status
Simulation time 4046562233 ps
CPU time 74.51 seconds
Started Apr 23 02:41:22 PM PDT 24
Finished Apr 23 02:42:37 PM PDT 24
Peak memory 199732 kb
Host smart-f668f0e2-62b1-40b0-8c70-dc37ca262b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231380406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2231380406
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1238453821
Short name T419
Test name
Test status
Simulation time 20031525 ps
CPU time 0.59 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:40:35 PM PDT 24
Peak memory 195196 kb
Host smart-3daf6a40-ac91-4030-8dee-be7975d6f60d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238453821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1238453821
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2008487131
Short name T228
Test name
Test status
Simulation time 2021663545 ps
CPU time 17.13 seconds
Started Apr 23 02:40:29 PM PDT 24
Finished Apr 23 02:40:46 PM PDT 24
Peak memory 207780 kb
Host smart-5276d72c-6668-494e-b0f2-76545d5d1a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008487131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2008487131
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4084416656
Short name T235
Test name
Test status
Simulation time 16397955 ps
CPU time 0.64 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 195648 kb
Host smart-730919bd-3b6a-4461-a693-6e15bc838061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084416656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4084416656
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.917914849
Short name T531
Test name
Test status
Simulation time 328056933 ps
CPU time 9.06 seconds
Started Apr 23 02:40:28 PM PDT 24
Finished Apr 23 02:40:37 PM PDT 24
Peak memory 199524 kb
Host smart-a98a36cb-1c7b-41d7-ace9-bb589f6502e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917914849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.917914849
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3228223685
Short name T446
Test name
Test status
Simulation time 688332522 ps
CPU time 3.02 seconds
Started Apr 23 02:40:29 PM PDT 24
Finished Apr 23 02:40:33 PM PDT 24
Peak memory 199556 kb
Host smart-95158af8-0141-4746-89da-40b7d1a2681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228223685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3228223685
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.413511228
Short name T40
Test name
Test status
Simulation time 139793479 ps
CPU time 0.8 seconds
Started Apr 23 02:40:33 PM PDT 24
Finished Apr 23 02:40:34 PM PDT 24
Peak memory 218136 kb
Host smart-c161d4d4-6799-459b-a8a8-054d34ff9932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413511228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.413511228
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3945971704
Short name T437
Test name
Test status
Simulation time 1259531289 ps
CPU time 2.39 seconds
Started Apr 23 02:40:30 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 199612 kb
Host smart-9eb90462-3e24-48fa-a639-3bc62de414dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945971704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3945971704
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.225674744
Short name T601
Test name
Test status
Simulation time 336542107318 ps
CPU time 1636.09 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 03:07:47 PM PDT 24
Peak memory 235552 kb
Host smart-848efea8-7fa4-485b-8194-3e20278a1f5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225674744 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.225674744
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2100665237
Short name T413
Test name
Test status
Simulation time 30355254 ps
CPU time 1.18 seconds
Started Apr 23 02:40:35 PM PDT 24
Finished Apr 23 02:40:37 PM PDT 24
Peak memory 199508 kb
Host smart-db2348a3-6bee-47e0-9893-69d58f26b4a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100665237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2100665237
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1388245966
Short name T215
Test name
Test status
Simulation time 28843112774 ps
CPU time 412.87 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:47:24 PM PDT 24
Peak memory 199720 kb
Host smart-1139a751-1674-4e86-85b0-f020f5a2d5fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388245966 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1388245966
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1234622786
Short name T570
Test name
Test status
Simulation time 4975591291 ps
CPU time 45.85 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:41:17 PM PDT 24
Peak memory 199632 kb
Host smart-46ddf433-1d8f-434b-b1e9-8891726f66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234622786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1234622786
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4024780851
Short name T495
Test name
Test status
Simulation time 13172875 ps
CPU time 0.58 seconds
Started Apr 23 02:41:25 PM PDT 24
Finished Apr 23 02:41:26 PM PDT 24
Peak memory 194176 kb
Host smart-c96f1d34-25ef-474b-b890-c1c1f0f26b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024780851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4024780851
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4142607904
Short name T393
Test name
Test status
Simulation time 701750868 ps
CPU time 11.59 seconds
Started Apr 23 02:41:23 PM PDT 24
Finished Apr 23 02:41:35 PM PDT 24
Peak memory 207756 kb
Host smart-bb586825-5073-4ebe-832e-07864a610e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142607904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4142607904
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.39670315
Short name T463
Test name
Test status
Simulation time 894336256 ps
CPU time 6.22 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:41:34 PM PDT 24
Peak memory 199588 kb
Host smart-9aee2a7b-e2f6-4084-9739-055b0cc8ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39670315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.39670315
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3856536798
Short name T164
Test name
Test status
Simulation time 1677827266 ps
CPU time 92.3 seconds
Started Apr 23 02:41:28 PM PDT 24
Finished Apr 23 02:43:01 PM PDT 24
Peak memory 199616 kb
Host smart-a43ea12a-c3b0-4e8c-af8c-1316bec0bb5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856536798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3856536798
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3841561658
Short name T522
Test name
Test status
Simulation time 649089884 ps
CPU time 34.32 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:42:01 PM PDT 24
Peak memory 199584 kb
Host smart-9edbee7d-b9e3-418e-82d1-afe51452bda7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841561658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3841561658
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3788873606
Short name T351
Test name
Test status
Simulation time 32569735884 ps
CPU time 118.27 seconds
Started Apr 23 02:41:22 PM PDT 24
Finished Apr 23 02:43:21 PM PDT 24
Peak memory 199708 kb
Host smart-52bb28ed-5599-437b-85e3-685d22599fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788873606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3788873606
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.394262405
Short name T212
Test name
Test status
Simulation time 10077632808 ps
CPU time 6.77 seconds
Started Apr 23 02:41:21 PM PDT 24
Finished Apr 23 02:41:28 PM PDT 24
Peak memory 199756 kb
Host smart-f5dd78d3-2709-4e17-9d3c-15445392236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394262405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.394262405
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3528780395
Short name T197
Test name
Test status
Simulation time 107369415870 ps
CPU time 956.74 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:57:24 PM PDT 24
Peak memory 199736 kb
Host smart-5cb3173f-03b4-4e42-8179-89868cc00967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528780395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3528780395
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1060065084
Short name T158
Test name
Test status
Simulation time 122740350 ps
CPU time 1.33 seconds
Started Apr 23 02:41:29 PM PDT 24
Finished Apr 23 02:41:31 PM PDT 24
Peak memory 199596 kb
Host smart-984bea2b-d26b-44d3-86b7-17fdeac9be58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060065084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1060065084
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3866213111
Short name T345
Test name
Test status
Simulation time 54844111218 ps
CPU time 434.22 seconds
Started Apr 23 02:41:28 PM PDT 24
Finished Apr 23 02:48:42 PM PDT 24
Peak memory 199724 kb
Host smart-3220a529-b637-4937-bee6-0c30d41b30b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866213111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3866213111
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2230119250
Short name T28
Test name
Test status
Simulation time 288172429 ps
CPU time 10.13 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:41:38 PM PDT 24
Peak memory 199608 kb
Host smart-19030e63-e668-4b7e-8cca-dc549d23f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230119250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2230119250
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1810852840
Short name T496
Test name
Test status
Simulation time 27124042 ps
CPU time 0.56 seconds
Started Apr 23 02:41:33 PM PDT 24
Finished Apr 23 02:41:34 PM PDT 24
Peak memory 194308 kb
Host smart-941cafa9-af03-4f3b-8dd7-fa02ebdecd52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810852840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1810852840
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3083086320
Short name T95
Test name
Test status
Simulation time 881663223 ps
CPU time 27.52 seconds
Started Apr 23 02:41:26 PM PDT 24
Finished Apr 23 02:41:53 PM PDT 24
Peak memory 207816 kb
Host smart-d868d576-f744-4e55-8bd3-b45bdb37ef33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083086320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3083086320
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3449769711
Short name T126
Test name
Test status
Simulation time 1041316686 ps
CPU time 20.76 seconds
Started Apr 23 02:41:26 PM PDT 24
Finished Apr 23 02:41:47 PM PDT 24
Peak memory 199520 kb
Host smart-085b2f44-518a-4960-9b97-ecf45391a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449769711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3449769711
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2744333415
Short name T190
Test name
Test status
Simulation time 30467144747 ps
CPU time 142.47 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:43:50 PM PDT 24
Peak memory 199648 kb
Host smart-9042794a-bef1-450e-821d-2cf1906cb9b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744333415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2744333415
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1797754930
Short name T12
Test name
Test status
Simulation time 6865255933 ps
CPU time 75.42 seconds
Started Apr 23 02:41:30 PM PDT 24
Finished Apr 23 02:42:46 PM PDT 24
Peak memory 199728 kb
Host smart-9ea9a5cd-cda2-4b3a-b0d7-786c478af584
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797754930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1797754930
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3614443779
Short name T299
Test name
Test status
Simulation time 3233372996 ps
CPU time 16 seconds
Started Apr 23 02:41:28 PM PDT 24
Finished Apr 23 02:41:44 PM PDT 24
Peak memory 199672 kb
Host smart-4265a929-ed6f-474e-a784-b0d4cacf8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614443779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3614443779
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3882184556
Short name T300
Test name
Test status
Simulation time 5912074178 ps
CPU time 5.32 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:41:33 PM PDT 24
Peak memory 199644 kb
Host smart-3b360bf3-e0ee-45b0-9cfc-0f224e543b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882184556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3882184556
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3992510358
Short name T332
Test name
Test status
Simulation time 40763248912 ps
CPU time 507.29 seconds
Started Apr 23 02:41:31 PM PDT 24
Finished Apr 23 02:49:59 PM PDT 24
Peak memory 199732 kb
Host smart-7fa33737-84c4-45ed-a3fb-f1c8c1239c51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992510358 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3992510358
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.556778734
Short name T157
Test name
Test status
Simulation time 109594350 ps
CPU time 1.29 seconds
Started Apr 23 02:41:31 PM PDT 24
Finished Apr 23 02:41:33 PM PDT 24
Peak memory 199608 kb
Host smart-42844a4b-423a-4347-b1d3-2b67e71f62ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556778734 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.556778734
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.856268295
Short name T92
Test name
Test status
Simulation time 153976569659 ps
CPU time 473.88 seconds
Started Apr 23 02:41:30 PM PDT 24
Finished Apr 23 02:49:25 PM PDT 24
Peak memory 199696 kb
Host smart-92b715a8-1296-45ec-95d0-20d0fced15b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856268295 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.856268295
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2526416238
Short name T409
Test name
Test status
Simulation time 1874440165 ps
CPU time 34.36 seconds
Started Apr 23 02:41:27 PM PDT 24
Finished Apr 23 02:42:02 PM PDT 24
Peak memory 199572 kb
Host smart-0edac587-216a-4dab-8af1-6196386661d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526416238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2526416238
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.645729200
Short name T382
Test name
Test status
Simulation time 18392225 ps
CPU time 0.59 seconds
Started Apr 23 02:41:37 PM PDT 24
Finished Apr 23 02:41:38 PM PDT 24
Peak memory 195208 kb
Host smart-433a5573-41ab-4777-9676-b321ea1633b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645729200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.645729200
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3440386341
Short name T458
Test name
Test status
Simulation time 5534303099 ps
CPU time 55.06 seconds
Started Apr 23 02:41:31 PM PDT 24
Finished Apr 23 02:42:26 PM PDT 24
Peak memory 234548 kb
Host smart-4aed6137-9593-4737-a367-0bff26e95239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440386341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3440386341
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.9158465
Short name T381
Test name
Test status
Simulation time 2320698006 ps
CPU time 35.9 seconds
Started Apr 23 02:41:33 PM PDT 24
Finished Apr 23 02:42:09 PM PDT 24
Peak memory 199720 kb
Host smart-18cee9e3-08a1-4086-9540-1267da172abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9158465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.9158465
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2274041754
Short name T178
Test name
Test status
Simulation time 1740439245 ps
CPU time 25.43 seconds
Started Apr 23 02:41:30 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 199624 kb
Host smart-808853d0-3bf8-4558-a45a-620e82e9dd79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274041754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2274041754
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.404905836
Short name T53
Test name
Test status
Simulation time 5987770593 ps
CPU time 105.58 seconds
Started Apr 23 02:41:29 PM PDT 24
Finished Apr 23 02:43:15 PM PDT 24
Peak memory 199776 kb
Host smart-e8844a17-f097-4eec-9781-d617a4d62ce8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404905836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.404905836
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2810632248
Short name T594
Test name
Test status
Simulation time 6127011408 ps
CPU time 117.76 seconds
Started Apr 23 02:41:31 PM PDT 24
Finished Apr 23 02:43:29 PM PDT 24
Peak memory 199700 kb
Host smart-fcb8ef96-4c84-477d-ab11-fa71400a50f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810632248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2810632248
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1578892326
Short name T194
Test name
Test status
Simulation time 1542074454 ps
CPU time 5.49 seconds
Started Apr 23 02:41:30 PM PDT 24
Finished Apr 23 02:41:36 PM PDT 24
Peak memory 199600 kb
Host smart-40457beb-b548-4bea-8bc1-f84d4e439355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578892326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1578892326
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3919843876
Short name T520
Test name
Test status
Simulation time 65109605309 ps
CPU time 1198.75 seconds
Started Apr 23 02:41:35 PM PDT 24
Finished Apr 23 03:01:35 PM PDT 24
Peak memory 199728 kb
Host smart-f86fd55c-37ac-4fcf-96da-ad437e642385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919843876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3919843876
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2385529111
Short name T477
Test name
Test status
Simulation time 320594128 ps
CPU time 1.28 seconds
Started Apr 23 02:41:29 PM PDT 24
Finished Apr 23 02:41:31 PM PDT 24
Peak memory 199544 kb
Host smart-0fdc5636-8947-480e-8afb-60576968de21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385529111 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2385529111
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.676717753
Short name T85
Test name
Test status
Simulation time 31578852864 ps
CPU time 425.42 seconds
Started Apr 23 02:41:31 PM PDT 24
Finished Apr 23 02:48:37 PM PDT 24
Peak memory 199652 kb
Host smart-bb316152-0481-41c4-86de-a8a4677f6f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676717753 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.676717753
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1745067535
Short name T373
Test name
Test status
Simulation time 3235738525 ps
CPU time 55.93 seconds
Started Apr 23 02:41:30 PM PDT 24
Finished Apr 23 02:42:26 PM PDT 24
Peak memory 199736 kb
Host smart-ab47463d-3dfb-40bc-ac29-066161da507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745067535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1745067535
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2931848778
Short name T403
Test name
Test status
Simulation time 14739850 ps
CPU time 0.57 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:41:41 PM PDT 24
Peak memory 195164 kb
Host smart-077b0452-f616-4f34-9661-d21e0d97c3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931848778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2931848778
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1820183880
Short name T271
Test name
Test status
Simulation time 921080231 ps
CPU time 33.98 seconds
Started Apr 23 02:41:34 PM PDT 24
Finished Apr 23 02:42:08 PM PDT 24
Peak memory 215380 kb
Host smart-79661004-626b-4f29-bf86-5f4c019547a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820183880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1820183880
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.229997208
Short name T329
Test name
Test status
Simulation time 5139602518 ps
CPU time 63.88 seconds
Started Apr 23 02:41:34 PM PDT 24
Finished Apr 23 02:42:38 PM PDT 24
Peak memory 199716 kb
Host smart-910c6014-3aed-4e00-adae-8dbaf41a5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229997208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.229997208
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.815586415
Short name T199
Test name
Test status
Simulation time 6428772000 ps
CPU time 58.65 seconds
Started Apr 23 02:41:34 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 199688 kb
Host smart-9b63322c-98a8-441d-bfb6-b2d7cc89c02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815586415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.815586415
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3416969898
Short name T13
Test name
Test status
Simulation time 34617223109 ps
CPU time 220.24 seconds
Started Apr 23 02:41:33 PM PDT 24
Finished Apr 23 02:45:13 PM PDT 24
Peak memory 199764 kb
Host smart-f79bf9c2-ea13-48ac-8045-851434130889
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416969898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3416969898
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.173130742
Short name T275
Test name
Test status
Simulation time 7683784035 ps
CPU time 50.07 seconds
Started Apr 23 02:41:33 PM PDT 24
Finished Apr 23 02:42:24 PM PDT 24
Peak memory 199676 kb
Host smart-d82a17e9-4218-4981-ac84-e67ce3b4e316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173130742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.173130742
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2369706399
Short name T171
Test name
Test status
Simulation time 246345144 ps
CPU time 4.12 seconds
Started Apr 23 02:41:32 PM PDT 24
Finished Apr 23 02:41:37 PM PDT 24
Peak memory 199512 kb
Host smart-62a15395-7755-48e1-9767-e936306220ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369706399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2369706399
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.574739633
Short name T358
Test name
Test status
Simulation time 76156563858 ps
CPU time 285.22 seconds
Started Apr 23 02:41:35 PM PDT 24
Finished Apr 23 02:46:21 PM PDT 24
Peak memory 207972 kb
Host smart-4af5e52d-0aef-4e52-b68d-e74c987781aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574739633 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.574739633
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.950056025
Short name T291
Test name
Test status
Simulation time 180563231 ps
CPU time 1.06 seconds
Started Apr 23 02:41:35 PM PDT 24
Finished Apr 23 02:41:37 PM PDT 24
Peak memory 199208 kb
Host smart-8b13b0d7-a8bd-4466-bf7d-2a74c58b088f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950056025 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.950056025
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.150114056
Short name T596
Test name
Test status
Simulation time 258114232578 ps
CPU time 462.07 seconds
Started Apr 23 02:41:36 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 199652 kb
Host smart-a409e6a3-1b63-4519-a264-dc312183f009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150114056 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.150114056
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2115146034
Short name T196
Test name
Test status
Simulation time 812852783 ps
CPU time 42.45 seconds
Started Apr 23 02:41:32 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199608 kb
Host smart-351756b2-64fe-430b-86c6-fed2f6b93bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115146034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2115146034
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3219319724
Short name T220
Test name
Test status
Simulation time 22125974 ps
CPU time 0.58 seconds
Started Apr 23 02:41:41 PM PDT 24
Finished Apr 23 02:41:42 PM PDT 24
Peak memory 195196 kb
Host smart-f7f12bea-4fe1-46b0-bdd1-04e5691b9bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219319724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3219319724
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.772345485
Short name T427
Test name
Test status
Simulation time 1434917775 ps
CPU time 16.72 seconds
Started Apr 23 02:41:37 PM PDT 24
Finished Apr 23 02:41:54 PM PDT 24
Peak memory 240340 kb
Host smart-6d269091-ddbc-427d-9de8-f245a1695ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772345485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.772345485
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2843077257
Short name T268
Test name
Test status
Simulation time 783685796 ps
CPU time 39.38 seconds
Started Apr 23 02:41:41 PM PDT 24
Finished Apr 23 02:42:21 PM PDT 24
Peak memory 199548 kb
Host smart-c1c3d288-d907-462a-a0e6-d1c3e79be8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843077257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2843077257
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4123516070
Short name T353
Test name
Test status
Simulation time 1008328069 ps
CPU time 14.35 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:41:59 PM PDT 24
Peak memory 199568 kb
Host smart-530d71cb-290f-4dd3-b851-82dfeaecc12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123516070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4123516070
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2296327014
Short name T448
Test name
Test status
Simulation time 594251939 ps
CPU time 13.63 seconds
Started Apr 23 02:41:42 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 199540 kb
Host smart-70ed1227-0a60-4dbd-b934-03514727b2f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296327014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2296327014
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1091929468
Short name T560
Test name
Test status
Simulation time 2128755740 ps
CPU time 32.8 seconds
Started Apr 23 02:41:38 PM PDT 24
Finished Apr 23 02:42:11 PM PDT 24
Peak memory 199600 kb
Host smart-c27edc13-313a-4820-b755-7de20145aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091929468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1091929468
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1154245969
Short name T517
Test name
Test status
Simulation time 60345028 ps
CPU time 0.67 seconds
Started Apr 23 02:41:39 PM PDT 24
Finished Apr 23 02:41:40 PM PDT 24
Peak memory 196540 kb
Host smart-e48ba970-ab1c-4b19-aa86-b787711afd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154245969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1154245969
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3910628584
Short name T330
Test name
Test status
Simulation time 51401633590 ps
CPU time 350.52 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:47:31 PM PDT 24
Peak memory 216132 kb
Host smart-2786c67b-b848-4b76-9ca9-b405cc8a062e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910628584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3910628584
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2858347349
Short name T65
Test name
Test status
Simulation time 264477546431 ps
CPU time 1950.78 seconds
Started Apr 23 02:41:41 PM PDT 24
Finished Apr 23 03:14:13 PM PDT 24
Peak memory 232552 kb
Host smart-04c04167-7dfe-4c2e-b588-039ea377a963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858347349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2858347349
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3932187790
Short name T262
Test name
Test status
Simulation time 55370854 ps
CPU time 0.98 seconds
Started Apr 23 02:41:37 PM PDT 24
Finished Apr 23 02:41:39 PM PDT 24
Peak memory 198992 kb
Host smart-511a8a14-a11d-4680-b9a2-3fa1230c7eee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932187790 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3932187790
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.4088079042
Short name T387
Test name
Test status
Simulation time 34963288592 ps
CPU time 511.53 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:50:12 PM PDT 24
Peak memory 199676 kb
Host smart-25074ecf-a8b1-4ee8-9486-bba12149a5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088079042 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.4088079042
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2211575772
Short name T129
Test name
Test status
Simulation time 4506204754 ps
CPU time 49.41 seconds
Started Apr 23 02:41:39 PM PDT 24
Finished Apr 23 02:42:29 PM PDT 24
Peak memory 199680 kb
Host smart-6909d01f-49b1-4b60-9eb9-c9df99e624d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211575772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2211575772
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3215030942
Short name T481
Test name
Test status
Simulation time 13180643 ps
CPU time 0.59 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:41:41 PM PDT 24
Peak memory 195192 kb
Host smart-e806e380-e496-41b0-9602-3cae3067d84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215030942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3215030942
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2856698264
Short name T508
Test name
Test status
Simulation time 2402164187 ps
CPU time 17.46 seconds
Started Apr 23 02:41:42 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 216136 kb
Host smart-e42ed39b-1755-4d22-be04-130729897dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856698264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2856698264
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1724056117
Short name T410
Test name
Test status
Simulation time 1119819595 ps
CPU time 11.08 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 199572 kb
Host smart-db8d7ed4-a40a-4cbe-a008-f6ea5e63d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724056117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1724056117
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.313761371
Short name T429
Test name
Test status
Simulation time 26298371707 ps
CPU time 78.33 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:43:03 PM PDT 24
Peak memory 199696 kb
Host smart-809a4897-3ad7-4ee3-8a16-d042ee4ff7de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313761371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.313761371
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3271606030
Short name T374
Test name
Test status
Simulation time 3207319602 ps
CPU time 54.24 seconds
Started Apr 23 02:41:41 PM PDT 24
Finished Apr 23 02:42:35 PM PDT 24
Peak memory 199704 kb
Host smart-f6e39ce0-0dfc-4ec4-8f75-13bf97de0fc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271606030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3271606030
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.330876987
Short name T160
Test name
Test status
Simulation time 5110112847 ps
CPU time 65.53 seconds
Started Apr 23 02:41:41 PM PDT 24
Finished Apr 23 02:42:47 PM PDT 24
Peak memory 199676 kb
Host smart-17b68d31-ddc1-486e-a261-06dfd7d0ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330876987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.330876987
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.987165821
Short name T430
Test name
Test status
Simulation time 381747052 ps
CPU time 3.08 seconds
Started Apr 23 02:41:38 PM PDT 24
Finished Apr 23 02:41:41 PM PDT 24
Peak memory 199592 kb
Host smart-25b6c8ce-3735-4992-8b8d-f61b411e8768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987165821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.987165821
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1792242672
Short name T395
Test name
Test status
Simulation time 150917779216 ps
CPU time 708.84 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:53:33 PM PDT 24
Peak memory 232472 kb
Host smart-19f16174-25f0-49f5-af81-9500a4a0beb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792242672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1792242672
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4267298499
Short name T390
Test name
Test status
Simulation time 155217844 ps
CPU time 1.19 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:41:45 PM PDT 24
Peak memory 199572 kb
Host smart-744850fb-5836-4a59-9b9e-c4243d4860f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267298499 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4267298499
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1749357360
Short name T253
Test name
Test status
Simulation time 18508143779 ps
CPU time 436.39 seconds
Started Apr 23 02:41:43 PM PDT 24
Finished Apr 23 02:48:59 PM PDT 24
Peak memory 199672 kb
Host smart-ec6f909a-0456-48ea-8b84-78c5f13d41fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749357360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1749357360
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3646009452
Short name T545
Test name
Test status
Simulation time 5435987974 ps
CPU time 19.95 seconds
Started Apr 23 02:41:37 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 199728 kb
Host smart-5e3c06d6-ff49-4c13-8ef1-288a8cc6eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646009452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3646009452
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2079025919
Short name T568
Test name
Test status
Simulation time 11915536 ps
CPU time 0.56 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:41:46 PM PDT 24
Peak memory 194884 kb
Host smart-35d0398e-558b-4b99-af91-d52b949a96fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079025919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2079025919
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.723853143
Short name T57
Test name
Test status
Simulation time 592905851 ps
CPU time 19.31 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:41:59 PM PDT 24
Peak memory 215276 kb
Host smart-9f030b22-6601-4ded-9244-461f10edc9b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723853143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.723853143
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3168192938
Short name T379
Test name
Test status
Simulation time 1688763925 ps
CPU time 25.07 seconds
Started Apr 23 02:41:42 PM PDT 24
Finished Apr 23 02:42:08 PM PDT 24
Peak memory 199552 kb
Host smart-fca76901-e29c-4c95-ae18-20a4447d7a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168192938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3168192938
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2700174242
Short name T416
Test name
Test status
Simulation time 735134516 ps
CPU time 10.43 seconds
Started Apr 23 02:41:40 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 199620 kb
Host smart-059c0a1c-2bdc-4c83-8874-b2c41a43b424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700174242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2700174242
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1031334531
Short name T475
Test name
Test status
Simulation time 88249229182 ps
CPU time 87.26 seconds
Started Apr 23 02:41:42 PM PDT 24
Finished Apr 23 02:43:10 PM PDT 24
Peak memory 199696 kb
Host smart-d5c8d053-86d7-4bdc-8089-130efea50a62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031334531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1031334531
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_smoke.2851027596
Short name T140
Test name
Test status
Simulation time 662184488 ps
CPU time 5.31 seconds
Started Apr 23 02:41:43 PM PDT 24
Finished Apr 23 02:41:49 PM PDT 24
Peak memory 199564 kb
Host smart-bc754a6b-e35b-4d4d-9e2a-87b0cabde37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851027596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2851027596
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2188690756
Short name T31
Test name
Test status
Simulation time 195953538859 ps
CPU time 1323.81 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 03:03:48 PM PDT 24
Peak memory 235956 kb
Host smart-4f064d90-18ad-405b-a49c-c39d9737c640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188690756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2188690756
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1058710206
Short name T588
Test name
Test status
Simulation time 62967289 ps
CPU time 1.26 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:41:47 PM PDT 24
Peak memory 199584 kb
Host smart-56b0e565-a2d4-454a-af74-1caeaf984933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058710206 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1058710206
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.130173430
Short name T231
Test name
Test status
Simulation time 6974155430 ps
CPU time 375.01 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:48:00 PM PDT 24
Peak memory 199700 kb
Host smart-09dcdc75-6f1a-4e4e-9b76-782f05108593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130173430 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.130173430
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2869683121
Short name T296
Test name
Test status
Simulation time 2909496030 ps
CPU time 48.54 seconds
Started Apr 23 02:41:44 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 199732 kb
Host smart-b5dfdcb6-e863-4a00-b7d5-d0ec2cec4a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869683121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2869683121
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2563275887
Short name T221
Test name
Test status
Simulation time 23102067 ps
CPU time 0.56 seconds
Started Apr 23 02:41:49 PM PDT 24
Finished Apr 23 02:41:50 PM PDT 24
Peak memory 195160 kb
Host smart-ae73f6b1-e164-4150-8261-661b49da3c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563275887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2563275887
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1213012407
Short name T18
Test name
Test status
Simulation time 1614023934 ps
CPU time 17.46 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:42:03 PM PDT 24
Peak memory 221104 kb
Host smart-33ea0437-6613-4aa3-99ff-05ded66cfc7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213012407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1213012407
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2536223336
Short name T232
Test name
Test status
Simulation time 3092369701 ps
CPU time 9.53 seconds
Started Apr 23 02:41:43 PM PDT 24
Finished Apr 23 02:41:53 PM PDT 24
Peak memory 199660 kb
Host smart-8aec22e1-2dab-4414-8dbe-1d664b88396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536223336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2536223336
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.792650981
Short name T509
Test name
Test status
Simulation time 4806415589 ps
CPU time 169.53 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:44:35 PM PDT 24
Peak memory 199728 kb
Host smart-fa7f6433-50be-4e11-9d27-80560e65a12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792650981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.792650981
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.365228687
Short name T532
Test name
Test status
Simulation time 8160301842 ps
CPU time 218.15 seconds
Started Apr 23 02:41:46 PM PDT 24
Finished Apr 23 02:45:25 PM PDT 24
Peak memory 199728 kb
Host smart-99aa7e40-cd13-46fb-93d2-5bc43d2c5100
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365228687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.365228687
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.804198284
Short name T134
Test name
Test status
Simulation time 21910923813 ps
CPU time 82.78 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:43:08 PM PDT 24
Peak memory 199796 kb
Host smart-63e188ab-54e3-4250-bcae-c51dffbd03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804198284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.804198284
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1737828060
Short name T593
Test name
Test status
Simulation time 188783283 ps
CPU time 1.2 seconds
Started Apr 23 02:41:45 PM PDT 24
Finished Apr 23 02:41:47 PM PDT 24
Peak memory 199592 kb
Host smart-3ae88982-445f-49ca-b7b2-09f4a00a4d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737828060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1737828060
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2175514533
Short name T507
Test name
Test status
Simulation time 372999188033 ps
CPU time 1455.65 seconds
Started Apr 23 02:41:51 PM PDT 24
Finished Apr 23 03:06:08 PM PDT 24
Peak memory 216072 kb
Host smart-e0330625-29e9-4794-b20a-8f18041accdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175514533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2175514533
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.930487527
Short name T471
Test name
Test status
Simulation time 107443746 ps
CPU time 1.05 seconds
Started Apr 23 02:41:47 PM PDT 24
Finished Apr 23 02:41:48 PM PDT 24
Peak memory 199256 kb
Host smart-0d651c54-87d7-477f-a18b-f146539e128c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930487527 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.930487527
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2871497729
Short name T412
Test name
Test status
Simulation time 57728461061 ps
CPU time 484.4 seconds
Started Apr 23 02:41:50 PM PDT 24
Finished Apr 23 02:49:54 PM PDT 24
Peak memory 199728 kb
Host smart-3e67fe2e-c445-4fe5-b885-b7825125fe19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871497729 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2871497729
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3085336423
Short name T152
Test name
Test status
Simulation time 442683431 ps
CPU time 6.74 seconds
Started Apr 23 02:41:49 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 199608 kb
Host smart-d3f2bb65-4e45-401f-991c-49442936460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085336423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3085336423
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1378305542
Short name T498
Test name
Test status
Simulation time 14649223 ps
CPU time 0.66 seconds
Started Apr 23 02:41:53 PM PDT 24
Finished Apr 23 02:41:54 PM PDT 24
Peak memory 195312 kb
Host smart-b3e35e19-abbb-43b8-8fb4-8c5416e10e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378305542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1378305542
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3963766652
Short name T58
Test name
Test status
Simulation time 2115902462 ps
CPU time 42.13 seconds
Started Apr 23 02:41:49 PM PDT 24
Finished Apr 23 02:42:31 PM PDT 24
Peak memory 207772 kb
Host smart-7656fcbe-2d4d-4e24-b83e-494c0ec16d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963766652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3963766652
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2820111613
Short name T371
Test name
Test status
Simulation time 471713134 ps
CPU time 6.03 seconds
Started Apr 23 02:41:51 PM PDT 24
Finished Apr 23 02:41:58 PM PDT 24
Peak memory 199500 kb
Host smart-cc14c42b-4d13-402f-8cf6-a2a6f7cc92d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820111613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2820111613
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4262913678
Short name T202
Test name
Test status
Simulation time 138454355 ps
CPU time 3.68 seconds
Started Apr 23 02:41:48 PM PDT 24
Finished Apr 23 02:41:52 PM PDT 24
Peak memory 199612 kb
Host smart-f1ef6d02-f5af-4183-b73c-ea56049af816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262913678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4262913678
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1665064514
Short name T91
Test name
Test status
Simulation time 2938995838 ps
CPU time 42.77 seconds
Started Apr 23 02:41:50 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 199740 kb
Host smart-2c7961ce-6a0d-4d48-927f-8eda5a890d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665064514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1665064514
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3009118769
Short name T125
Test name
Test status
Simulation time 755169529 ps
CPU time 5.04 seconds
Started Apr 23 02:41:50 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 199596 kb
Host smart-13fb4cf0-268e-4f7a-9c95-606f60d50ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009118769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3009118769
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3567820667
Short name T76
Test name
Test status
Simulation time 1604721286978 ps
CPU time 2087.04 seconds
Started Apr 23 02:41:51 PM PDT 24
Finished Apr 23 03:16:39 PM PDT 24
Peak memory 207880 kb
Host smart-6103a65a-5aaa-43a0-b610-4eca658aeec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567820667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3567820667
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.455640263
Short name T64
Test name
Test status
Simulation time 49024723191 ps
CPU time 1859.75 seconds
Started Apr 23 02:41:54 PM PDT 24
Finished Apr 23 03:12:54 PM PDT 24
Peak memory 258152 kb
Host smart-909a4000-7300-4937-a9de-338f70abbfcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455640263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.455640263
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4131640383
Short name T263
Test name
Test status
Simulation time 29437557 ps
CPU time 1.08 seconds
Started Apr 23 02:41:50 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 199556 kb
Host smart-fa4c3272-6efd-4711-b848-5fd3defe76f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131640383 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4131640383
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.106733030
Short name T298
Test name
Test status
Simulation time 95472364787 ps
CPU time 547.77 seconds
Started Apr 23 02:41:48 PM PDT 24
Finished Apr 23 02:50:56 PM PDT 24
Peak memory 199684 kb
Host smart-254d6caf-b3cb-4a1c-9cd4-304ae4d9b57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106733030 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.106733030
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1084251636
Short name T595
Test name
Test status
Simulation time 29690208459 ps
CPU time 97.6 seconds
Started Apr 23 02:41:51 PM PDT 24
Finished Apr 23 02:43:29 PM PDT 24
Peak memory 199676 kb
Host smart-0585c32b-a71b-4506-8864-e7be3290d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084251636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1084251636
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4104128809
Short name T523
Test name
Test status
Simulation time 13717598 ps
CPU time 0.59 seconds
Started Apr 23 02:41:57 PM PDT 24
Finished Apr 23 02:41:58 PM PDT 24
Peak memory 195092 kb
Host smart-e9bdcc86-45e4-4edd-bfd8-521e80bcab76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104128809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4104128809
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3964726067
Short name T149
Test name
Test status
Simulation time 1376882445 ps
CPU time 57.04 seconds
Started Apr 23 02:41:53 PM PDT 24
Finished Apr 23 02:42:51 PM PDT 24
Peak memory 235440 kb
Host smart-1489a67d-ec45-4844-9de2-96171f1d44bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964726067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3964726067
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1996591411
Short name T191
Test name
Test status
Simulation time 457316118 ps
CPU time 1.58 seconds
Started Apr 23 02:41:51 PM PDT 24
Finished Apr 23 02:41:53 PM PDT 24
Peak memory 199576 kb
Host smart-4ef2df81-8769-40ad-93b2-fce11ac6b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996591411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1996591411
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4289793990
Short name T392
Test name
Test status
Simulation time 2775951712 ps
CPU time 29.43 seconds
Started Apr 23 02:41:53 PM PDT 24
Finished Apr 23 02:42:23 PM PDT 24
Peak memory 199648 kb
Host smart-124ff885-f57e-489e-b9d3-c8719102fe19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289793990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4289793990
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3984856796
Short name T576
Test name
Test status
Simulation time 2656748004 ps
CPU time 74.73 seconds
Started Apr 23 02:41:50 PM PDT 24
Finished Apr 23 02:43:06 PM PDT 24
Peak memory 199716 kb
Host smart-600b2300-36df-4cda-a7bd-b532df636fd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984856796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3984856796
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3849568233
Short name T136
Test name
Test status
Simulation time 6668252568 ps
CPU time 102.33 seconds
Started Apr 23 02:41:53 PM PDT 24
Finished Apr 23 02:43:35 PM PDT 24
Peak memory 199624 kb
Host smart-bae217c1-1035-439a-aa36-294711a744b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849568233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3849568233
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1763065892
Short name T425
Test name
Test status
Simulation time 150758734 ps
CPU time 2.5 seconds
Started Apr 23 02:41:52 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 199532 kb
Host smart-49a542d3-0a3d-49de-896e-633b0b67ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763065892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1763065892
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2311690610
Short name T34
Test name
Test status
Simulation time 19529931444 ps
CPU time 1055.28 seconds
Started Apr 23 02:41:56 PM PDT 24
Finished Apr 23 02:59:32 PM PDT 24
Peak memory 199704 kb
Host smart-4c4095a0-2230-4d2f-88f9-f938f5655458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311690610 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2311690610
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1086895336
Short name T172
Test name
Test status
Simulation time 125461127 ps
CPU time 1.26 seconds
Started Apr 23 02:41:55 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 199636 kb
Host smart-a2a7ea71-cb18-4b0b-89fd-8f583ce63e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086895336 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1086895336
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.59256283
Short name T217
Test name
Test status
Simulation time 42800192207 ps
CPU time 437.25 seconds
Started Apr 23 02:41:56 PM PDT 24
Finished Apr 23 02:49:13 PM PDT 24
Peak memory 199732 kb
Host smart-6aa9103f-2c7c-4b02-b36b-772616cbe012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59256283 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.59256283
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1044331329
Short name T216
Test name
Test status
Simulation time 3940179217 ps
CPU time 19.04 seconds
Started Apr 23 02:41:56 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199712 kb
Host smart-97f90b4e-89d6-4d0b-a4a5-36ed19a757a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044331329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1044331329
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2649259460
Short name T81
Test name
Test status
Simulation time 38071767 ps
CPU time 0.58 seconds
Started Apr 23 02:40:37 PM PDT 24
Finished Apr 23 02:40:38 PM PDT 24
Peak memory 195160 kb
Host smart-0800268d-6fde-4b00-b803-ae7ff3273a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649259460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2649259460
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1219114762
Short name T529
Test name
Test status
Simulation time 13799894549 ps
CPU time 40.79 seconds
Started Apr 23 02:40:37 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 216008 kb
Host smart-5ae49c49-96f2-4204-97f2-e23c261ab375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219114762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1219114762
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.830438964
Short name T19
Test name
Test status
Simulation time 74178842 ps
CPU time 1.1 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 199552 kb
Host smart-6c8faf64-7463-436e-af82-723794ef1474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830438964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.830438964
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2864959759
Short name T320
Test name
Test status
Simulation time 1529321460 ps
CPU time 85.6 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 199556 kb
Host smart-5761c42a-4680-4c97-a8f7-c63b55c8f0a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864959759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2864959759
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2094528039
Short name T52
Test name
Test status
Simulation time 72037938313 ps
CPU time 200.02 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:43:54 PM PDT 24
Peak memory 199776 kb
Host smart-463187b2-44dd-429f-97c9-c2795a30d5fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094528039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2094528039
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2150831521
Short name T179
Test name
Test status
Simulation time 15136132481 ps
CPU time 36.81 seconds
Started Apr 23 02:40:31 PM PDT 24
Finished Apr 23 02:41:08 PM PDT 24
Peak memory 199752 kb
Host smart-8f4d0071-f617-4199-9e0a-31c22ea3d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150831521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2150831521
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3804578469
Short name T41
Test name
Test status
Simulation time 89516833 ps
CPU time 1.02 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:40:36 PM PDT 24
Peak memory 219200 kb
Host smart-d46514f5-ebbf-43ec-9f4c-1441a89cbc42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804578469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3804578469
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3000182555
Short name T260
Test name
Test status
Simulation time 171579414 ps
CPU time 5.24 seconds
Started Apr 23 02:40:36 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 199592 kb
Host smart-9cd2c512-40a1-4219-a649-59fd4b3d2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000182555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3000182555
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3951269419
Short name T308
Test name
Test status
Simulation time 103243193708 ps
CPU time 1961.6 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 03:13:16 PM PDT 24
Peak memory 199696 kb
Host smart-5d99d8ad-db12-4b52-869f-d5cdc5fe1009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951269419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3951269419
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1923083074
Short name T533
Test name
Test status
Simulation time 106243844 ps
CPU time 1.2 seconds
Started Apr 23 02:40:32 PM PDT 24
Finished Apr 23 02:40:34 PM PDT 24
Peak memory 199500 kb
Host smart-d1112faa-5683-475a-a01a-85c929e9ac48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923083074 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1923083074
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1163347550
Short name T120
Test name
Test status
Simulation time 174529148259 ps
CPU time 461.39 seconds
Started Apr 23 02:40:33 PM PDT 24
Finished Apr 23 02:48:15 PM PDT 24
Peak memory 199668 kb
Host smart-b30cda99-400c-4db1-a69b-313571f3161e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163347550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1163347550
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1362023417
Short name T368
Test name
Test status
Simulation time 8132198464 ps
CPU time 53.63 seconds
Started Apr 23 02:40:36 PM PDT 24
Finished Apr 23 02:41:30 PM PDT 24
Peak memory 199688 kb
Host smart-72cbe6d5-634f-4be0-a6bc-3ea669f872ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362023417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1362023417
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2009200433
Short name T294
Test name
Test status
Simulation time 40090091 ps
CPU time 0.57 seconds
Started Apr 23 02:42:01 PM PDT 24
Finished Apr 23 02:42:02 PM PDT 24
Peak memory 195204 kb
Host smart-b6e2b95d-5b69-42ff-b389-c40484d2c2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009200433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2009200433
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.923395253
Short name T334
Test name
Test status
Simulation time 3152364333 ps
CPU time 31.24 seconds
Started Apr 23 02:41:59 PM PDT 24
Finished Apr 23 02:42:30 PM PDT 24
Peak memory 230056 kb
Host smart-09a248d6-684e-4e17-8a32-5f51f2232649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923395253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.923395253
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.784320800
Short name T127
Test name
Test status
Simulation time 6956034990 ps
CPU time 79.99 seconds
Started Apr 23 02:41:58 PM PDT 24
Finished Apr 23 02:43:18 PM PDT 24
Peak memory 199744 kb
Host smart-ee428e4f-5571-498e-8052-24a2f58ab463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784320800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.784320800
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2102909456
Short name T318
Test name
Test status
Simulation time 1460431912 ps
CPU time 38.13 seconds
Started Apr 23 02:41:58 PM PDT 24
Finished Apr 23 02:42:36 PM PDT 24
Peak memory 199572 kb
Host smart-6712d0b0-87c0-4247-9972-ba90ade96a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102909456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2102909456
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1894607959
Short name T55
Test name
Test status
Simulation time 5014601351 ps
CPU time 67.98 seconds
Started Apr 23 02:41:59 PM PDT 24
Finished Apr 23 02:43:07 PM PDT 24
Peak memory 199720 kb
Host smart-b82cf722-abe5-4bf2-9df8-cc220ba86907
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894607959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1894607959
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.20959385
Short name T128
Test name
Test status
Simulation time 20444296553 ps
CPU time 76.09 seconds
Started Apr 23 02:41:57 PM PDT 24
Finished Apr 23 02:43:13 PM PDT 24
Peak memory 199700 kb
Host smart-5cb356f3-919c-41c2-9f44-8d08d1759036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20959385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.20959385
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2765133223
Short name T565
Test name
Test status
Simulation time 116296410 ps
CPU time 1.18 seconds
Started Apr 23 02:41:55 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 199576 kb
Host smart-8aaf596f-db6a-4853-ad37-a9d4c50f2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765133223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2765133223
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.256745446
Short name T512
Test name
Test status
Simulation time 2054410528 ps
CPU time 43.63 seconds
Started Apr 23 02:41:57 PM PDT 24
Finished Apr 23 02:42:41 PM PDT 24
Peak memory 207776 kb
Host smart-0b4430fb-8460-4c39-b92a-8444851a762e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256745446 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.256745446
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1501570713
Short name T264
Test name
Test status
Simulation time 81290904 ps
CPU time 1.54 seconds
Started Apr 23 02:41:59 PM PDT 24
Finished Apr 23 02:42:01 PM PDT 24
Peak memory 199536 kb
Host smart-615bf54a-73d8-41a7-a8ff-64c39add6ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501570713 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1501570713
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.4121873045
Short name T404
Test name
Test status
Simulation time 7857431718 ps
CPU time 432.58 seconds
Started Apr 23 02:41:57 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 199732 kb
Host smart-41b43bc3-30bc-4d41-9cbe-fa0a5b975988
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121873045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.4121873045
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.269302692
Short name T185
Test name
Test status
Simulation time 7664882845 ps
CPU time 57.51 seconds
Started Apr 23 02:41:58 PM PDT 24
Finished Apr 23 02:42:56 PM PDT 24
Peak memory 199736 kb
Host smart-cd305fa0-55bf-44e3-bbe5-21eb112f19c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269302692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.269302692
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1574380411
Short name T356
Test name
Test status
Simulation time 27953617 ps
CPU time 0.58 seconds
Started Apr 23 02:42:06 PM PDT 24
Finished Apr 23 02:42:07 PM PDT 24
Peak memory 195076 kb
Host smart-d54825ea-6da6-4ab7-99b6-4c362222272d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574380411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1574380411
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.212528434
Short name T415
Test name
Test status
Simulation time 1372090589 ps
CPU time 24.8 seconds
Started Apr 23 02:42:01 PM PDT 24
Finished Apr 23 02:42:26 PM PDT 24
Peak memory 199596 kb
Host smart-9f98508a-580b-497a-8214-5bbdc4948191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212528434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.212528434
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2515430670
Short name T165
Test name
Test status
Simulation time 18975473134 ps
CPU time 43.24 seconds
Started Apr 23 02:42:03 PM PDT 24
Finished Apr 23 02:42:46 PM PDT 24
Peak memory 199692 kb
Host smart-fbf2fd1d-73c7-4224-9db0-3a3378a0725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515430670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2515430670
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.615573972
Short name T569
Test name
Test status
Simulation time 22491605 ps
CPU time 0.64 seconds
Started Apr 23 02:42:04 PM PDT 24
Finished Apr 23 02:42:05 PM PDT 24
Peak memory 196756 kb
Host smart-2ebc0fbe-5cf0-43b2-a5e4-6aeda3181158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615573972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.615573972
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2732153640
Short name T513
Test name
Test status
Simulation time 5926786808 ps
CPU time 78.4 seconds
Started Apr 23 02:42:02 PM PDT 24
Finished Apr 23 02:43:20 PM PDT 24
Peak memory 199680 kb
Host smart-c48fc0c7-2f95-445a-8946-167c74772f14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732153640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2732153640
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1843646996
Short name T321
Test name
Test status
Simulation time 2800924237 ps
CPU time 35.89 seconds
Started Apr 23 02:42:01 PM PDT 24
Finished Apr 23 02:42:37 PM PDT 24
Peak memory 199792 kb
Host smart-b92d582f-3739-4e9d-94fd-e3ca8a579a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843646996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1843646996
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2839420852
Short name T97
Test name
Test status
Simulation time 370479418 ps
CPU time 3.16 seconds
Started Apr 23 02:42:02 PM PDT 24
Finished Apr 23 02:42:06 PM PDT 24
Peak memory 199564 kb
Host smart-714f2a44-384e-4f06-ab62-41437b122010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839420852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2839420852
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2937339756
Short name T489
Test name
Test status
Simulation time 14086568612 ps
CPU time 548.16 seconds
Started Apr 23 02:42:03 PM PDT 24
Finished Apr 23 02:51:12 PM PDT 24
Peak memory 240628 kb
Host smart-0491b190-446a-4656-bd4b-73d5668b0857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937339756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2937339756
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3416919897
Short name T530
Test name
Test status
Simulation time 52627556 ps
CPU time 1.04 seconds
Started Apr 23 02:42:07 PM PDT 24
Finished Apr 23 02:42:09 PM PDT 24
Peak memory 198872 kb
Host smart-89e1cd56-70b0-4bcd-a020-ae844149b746
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416919897 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3416919897
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4113412406
Short name T131
Test name
Test status
Simulation time 33037024805 ps
CPU time 445.01 seconds
Started Apr 23 02:42:06 PM PDT 24
Finished Apr 23 02:49:32 PM PDT 24
Peak memory 199724 kb
Host smart-b38c9bd7-8bde-41b2-af44-31be365a5f16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113412406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.4113412406
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1943959620
Short name T163
Test name
Test status
Simulation time 1089878180 ps
CPU time 54.25 seconds
Started Apr 23 02:42:01 PM PDT 24
Finished Apr 23 02:42:56 PM PDT 24
Peak memory 199528 kb
Host smart-008ede1a-5f56-445a-ad8d-5066b4269c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943959620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1943959620
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4031830598
Short name T246
Test name
Test status
Simulation time 24609587 ps
CPU time 0.59 seconds
Started Apr 23 02:42:09 PM PDT 24
Finished Apr 23 02:42:10 PM PDT 24
Peak memory 195156 kb
Host smart-389e1c21-6990-4325-9bdb-1600be385fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031830598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4031830598
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1375384154
Short name T239
Test name
Test status
Simulation time 5548422727 ps
CPU time 49.19 seconds
Started Apr 23 02:42:05 PM PDT 24
Finished Apr 23 02:42:54 PM PDT 24
Peak memory 216120 kb
Host smart-7e10fad4-dedf-4b53-a3d0-dc9a62cb5e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375384154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1375384154
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1107411356
Short name T562
Test name
Test status
Simulation time 766311261 ps
CPU time 38.93 seconds
Started Apr 23 02:42:05 PM PDT 24
Finished Apr 23 02:42:45 PM PDT 24
Peak memory 199592 kb
Host smart-416f3751-fe32-4193-a952-783157a30b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107411356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1107411356
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3234420434
Short name T187
Test name
Test status
Simulation time 4156794975 ps
CPU time 62.4 seconds
Started Apr 23 02:42:04 PM PDT 24
Finished Apr 23 02:43:07 PM PDT 24
Peak memory 199748 kb
Host smart-06cac8ea-08eb-4b65-84ba-f0d2f3107dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234420434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3234420434
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.149162742
Short name T559
Test name
Test status
Simulation time 18616002059 ps
CPU time 84.15 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:43:37 PM PDT 24
Peak memory 199680 kb
Host smart-8a745438-9e1d-4a93-8d57-a3b27981e51e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149162742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.149162742
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2273816093
Short name T68
Test name
Test status
Simulation time 4796757788 ps
CPU time 61.93 seconds
Started Apr 23 02:42:05 PM PDT 24
Finished Apr 23 02:43:07 PM PDT 24
Peak memory 199700 kb
Host smart-cac2621a-238c-466d-88e7-b1681dc46dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273816093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2273816093
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2914722758
Short name T466
Test name
Test status
Simulation time 2980030379 ps
CPU time 6.75 seconds
Started Apr 23 02:42:07 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199612 kb
Host smart-914f300c-ecc0-4e52-b930-7bb4b9f9a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914722758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2914722758
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2380804156
Short name T564
Test name
Test status
Simulation time 108638567760 ps
CPU time 726.3 seconds
Started Apr 23 02:42:08 PM PDT 24
Finished Apr 23 02:54:15 PM PDT 24
Peak memory 199688 kb
Host smart-dbd3d210-1fb8-4d26-a8a3-03056aba73d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380804156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2380804156
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1048709105
Short name T252
Test name
Test status
Simulation time 67765872 ps
CPU time 0.94 seconds
Started Apr 23 02:42:10 PM PDT 24
Finished Apr 23 02:42:11 PM PDT 24
Peak memory 197792 kb
Host smart-2c6f7f6e-10b7-4306-9859-2fc89a4c3d79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048709105 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1048709105
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.105788189
Short name T303
Test name
Test status
Simulation time 8136335345 ps
CPU time 428.42 seconds
Started Apr 23 02:42:09 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 199732 kb
Host smart-a466a13f-5f48-4471-931b-0b4e5d072945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105788189 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.105788189
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.809719972
Short name T137
Test name
Test status
Simulation time 14266920367 ps
CPU time 83.13 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:43:35 PM PDT 24
Peak memory 199688 kb
Host smart-24803474-5156-411b-8443-c30065798c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809719972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.809719972
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1064654587
Short name T442
Test name
Test status
Simulation time 18317408 ps
CPU time 0.55 seconds
Started Apr 23 02:42:11 PM PDT 24
Finished Apr 23 02:42:12 PM PDT 24
Peak memory 195144 kb
Host smart-d29b5723-696a-4c3b-9470-107a4284b656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064654587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1064654587
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4159050219
Short name T43
Test name
Test status
Simulation time 915321120 ps
CPU time 8.66 seconds
Started Apr 23 02:42:09 PM PDT 24
Finished Apr 23 02:42:18 PM PDT 24
Peak memory 215924 kb
Host smart-dc649c05-b21c-47e7-b9ca-9a43f8d735d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159050219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4159050219
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1202010641
Short name T248
Test name
Test status
Simulation time 2734316711 ps
CPU time 20.12 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 199708 kb
Host smart-10169225-cf7c-45cb-a1e7-4fc30068e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202010641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1202010641
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.992213639
Short name T276
Test name
Test status
Simulation time 3503436573 ps
CPU time 93.22 seconds
Started Apr 23 02:42:07 PM PDT 24
Finished Apr 23 02:43:41 PM PDT 24
Peak memory 199740 kb
Host smart-dcd8d81e-ba72-47a9-8177-bd85a1f9c243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992213639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.992213639
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4093166174
Short name T333
Test name
Test status
Simulation time 3105302213 ps
CPU time 43.33 seconds
Started Apr 23 02:42:07 PM PDT 24
Finished Apr 23 02:42:51 PM PDT 24
Peak memory 199740 kb
Host smart-21c58cba-80e7-46a2-8c2b-4d099db59ecc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093166174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4093166174
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1694714204
Short name T36
Test name
Test status
Simulation time 3140044072 ps
CPU time 94.67 seconds
Started Apr 23 02:42:08 PM PDT 24
Finished Apr 23 02:43:44 PM PDT 24
Peak memory 199756 kb
Host smart-58352b16-8583-4498-a7f4-fd266b0f40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694714204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1694714204
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1514714857
Short name T526
Test name
Test status
Simulation time 191527207 ps
CPU time 5.71 seconds
Started Apr 23 02:42:07 PM PDT 24
Finished Apr 23 02:42:13 PM PDT 24
Peak memory 199568 kb
Host smart-9d106c84-f1c0-40a8-be3b-8dbd4ddb8a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514714857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1514714857
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2441216784
Short name T361
Test name
Test status
Simulation time 1019593343 ps
CPU time 51.18 seconds
Started Apr 23 02:42:14 PM PDT 24
Finished Apr 23 02:43:06 PM PDT 24
Peak memory 199604 kb
Host smart-44f60405-719a-4ed1-b6fa-fcbd8e40a91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441216784 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2441216784
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1159448242
Short name T10
Test name
Test status
Simulation time 54886102621 ps
CPU time 1495.69 seconds
Started Apr 23 02:42:10 PM PDT 24
Finished Apr 23 03:07:07 PM PDT 24
Peak memory 248900 kb
Host smart-860e2ee7-a9b9-4b12-a7f9-900c243a2c13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159448242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1159448242
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.4191737133
Short name T599
Test name
Test status
Simulation time 57582177 ps
CPU time 1.31 seconds
Started Apr 23 02:42:14 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 199616 kb
Host smart-b1a3c9cb-bc09-4aef-9c97-bc82fdbaa7c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191737133 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.4191737133
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3103695830
Short name T502
Test name
Test status
Simulation time 263606372475 ps
CPU time 514.37 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:50:47 PM PDT 24
Peak memory 199704 kb
Host smart-caab149c-13bb-4750-90f4-26d262480119
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103695830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3103695830
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2915969852
Short name T167
Test name
Test status
Simulation time 12525756466 ps
CPU time 94.44 seconds
Started Apr 23 02:42:10 PM PDT 24
Finished Apr 23 02:43:45 PM PDT 24
Peak memory 199744 kb
Host smart-83df8514-116e-4ade-8962-a9670e24f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915969852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2915969852
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1672896190
Short name T488
Test name
Test status
Simulation time 15811193 ps
CPU time 0.56 seconds
Started Apr 23 02:42:15 PM PDT 24
Finished Apr 23 02:42:16 PM PDT 24
Peak memory 194332 kb
Host smart-70e12172-c0c7-417b-97e9-2e320d788cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672896190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1672896190
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.834861445
Short name T309
Test name
Test status
Simulation time 1276998039 ps
CPU time 51.14 seconds
Started Apr 23 02:42:13 PM PDT 24
Finished Apr 23 02:43:05 PM PDT 24
Peak memory 229284 kb
Host smart-78c42fd7-07a1-4f95-9152-2737285b5027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834861445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.834861445
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1193327173
Short name T400
Test name
Test status
Simulation time 8797616188 ps
CPU time 26.31 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:42:39 PM PDT 24
Peak memory 199564 kb
Host smart-b2f3daf5-5dde-4180-831c-39e4c5ed3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193327173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1193327173
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4044778421
Short name T553
Test name
Test status
Simulation time 372684360 ps
CPU time 4.6 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:42:17 PM PDT 24
Peak memory 199612 kb
Host smart-a6aa30b9-26eb-4f35-b798-7794cc50d92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044778421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4044778421
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1944017734
Short name T29
Test name
Test status
Simulation time 8514179452 ps
CPU time 148.52 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:44:41 PM PDT 24
Peak memory 199748 kb
Host smart-165cdeef-c185-48ef-9b59-c865e5cd9243
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944017734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1944017734
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.749587756
Short name T273
Test name
Test status
Simulation time 2139510664 ps
CPU time 42.25 seconds
Started Apr 23 02:42:11 PM PDT 24
Finished Apr 23 02:42:54 PM PDT 24
Peak memory 199560 kb
Host smart-4da76bc9-b020-4a1b-a25d-ebd3bfeb573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749587756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.749587756
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3841472637
Short name T71
Test name
Test status
Simulation time 650030829 ps
CPU time 5.05 seconds
Started Apr 23 02:42:10 PM PDT 24
Finished Apr 23 02:42:16 PM PDT 24
Peak memory 199600 kb
Host smart-6cc56786-b7bf-4ec1-9e54-a7330b466480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841472637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3841472637
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1508625721
Short name T372
Test name
Test status
Simulation time 3594110479 ps
CPU time 9.02 seconds
Started Apr 23 02:42:13 PM PDT 24
Finished Apr 23 02:42:22 PM PDT 24
Peak memory 199716 kb
Host smart-469f5019-046d-44a1-9166-1c1979088ab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508625721 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1508625721
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1971660520
Short name T169
Test name
Test status
Simulation time 402302909 ps
CPU time 1.32 seconds
Started Apr 23 02:42:14 PM PDT 24
Finished Apr 23 02:42:16 PM PDT 24
Peak memory 199552 kb
Host smart-4985647e-b8b0-46dc-a337-f2136d6d8545
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971660520 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1971660520
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3416835111
Short name T161
Test name
Test status
Simulation time 7817374472 ps
CPU time 415.96 seconds
Started Apr 23 02:42:14 PM PDT 24
Finished Apr 23 02:49:10 PM PDT 24
Peak memory 199640 kb
Host smart-7b3f2b72-6201-4fbd-aa43-efd717d23365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416835111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3416835111
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2657817399
Short name T198
Test name
Test status
Simulation time 2246975641 ps
CPU time 11.65 seconds
Started Apr 23 02:42:12 PM PDT 24
Finished Apr 23 02:42:25 PM PDT 24
Peak memory 199688 kb
Host smart-f4fdac88-f8cf-4cd4-a7ae-d2dba18793a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657817399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2657817399
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1041664290
Short name T405
Test name
Test status
Simulation time 43442302 ps
CPU time 0.62 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:42:20 PM PDT 24
Peak memory 194172 kb
Host smart-abe9994f-0ee8-44dc-aa11-974a4f4e4f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041664290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1041664290
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1092767900
Short name T552
Test name
Test status
Simulation time 2360390258 ps
CPU time 28.47 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:42:47 PM PDT 24
Peak memory 240392 kb
Host smart-63a8a66d-7bf9-493e-bf71-56ae1c624e1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092767900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1092767900
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.960347719
Short name T355
Test name
Test status
Simulation time 4632514058 ps
CPU time 46.69 seconds
Started Apr 23 02:42:17 PM PDT 24
Finished Apr 23 02:43:04 PM PDT 24
Peak memory 199708 kb
Host smart-603fe99e-5d13-467f-adc6-09d362b3547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960347719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.960347719
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3261196176
Short name T201
Test name
Test status
Simulation time 6127565714 ps
CPU time 63.36 seconds
Started Apr 23 02:42:16 PM PDT 24
Finished Apr 23 02:43:20 PM PDT 24
Peak memory 199720 kb
Host smart-6fe4c5e8-0fff-4f75-9eb4-c303c365f34c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261196176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3261196176
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.833953283
Short name T33
Test name
Test status
Simulation time 3388723878 ps
CPU time 178.09 seconds
Started Apr 23 02:42:20 PM PDT 24
Finished Apr 23 02:45:19 PM PDT 24
Peak memory 199684 kb
Host smart-65f38304-eb3c-4cb5-86bd-db38eb1537be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833953283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.833953283
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4256720556
Short name T499
Test name
Test status
Simulation time 32448115035 ps
CPU time 126.19 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:44:25 PM PDT 24
Peak memory 199688 kb
Host smart-2cb67c1c-c638-44d5-966f-db95a945aafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256720556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4256720556
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1013882081
Short name T359
Test name
Test status
Simulation time 95872780 ps
CPU time 3.07 seconds
Started Apr 23 02:42:14 PM PDT 24
Finished Apr 23 02:42:17 PM PDT 24
Peak memory 199564 kb
Host smart-50a2fce9-66b6-4610-bdf4-419ec29487a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013882081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1013882081
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.791400467
Short name T566
Test name
Test status
Simulation time 57922598285 ps
CPU time 688.04 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:53:48 PM PDT 24
Peak memory 231944 kb
Host smart-ae793726-ab4e-44f1-ba59-a1ba2c802f3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791400467 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.791400467
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.885721647
Short name T587
Test name
Test status
Simulation time 152448749 ps
CPU time 0.98 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:42:21 PM PDT 24
Peak memory 197676 kb
Host smart-9263d452-0c37-41c2-921e-79612c264448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885721647 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.885721647
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.930293436
Short name T46
Test name
Test status
Simulation time 100677051283 ps
CPU time 422.38 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:49:22 PM PDT 24
Peak memory 199696 kb
Host smart-496b2e6b-addb-4424-a8a1-530362554982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930293436 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.930293436
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1598747768
Short name T493
Test name
Test status
Simulation time 8167928442 ps
CPU time 71.99 seconds
Started Apr 23 02:42:18 PM PDT 24
Finished Apr 23 02:43:30 PM PDT 24
Peak memory 199724 kb
Host smart-8c333132-3451-4f41-b221-8db697b81478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598747768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1598747768
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.872229651
Short name T438
Test name
Test status
Simulation time 18738041 ps
CPU time 0.57 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:42:22 PM PDT 24
Peak memory 194312 kb
Host smart-fab2d9fa-d8b3-40b7-812f-a00e6bb18441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872229651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.872229651
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1518209498
Short name T257
Test name
Test status
Simulation time 1328345149 ps
CPU time 49.9 seconds
Started Apr 23 02:42:17 PM PDT 24
Finished Apr 23 02:43:08 PM PDT 24
Peak memory 229608 kb
Host smart-3c964aaf-8b28-45d8-84af-7f0839662475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518209498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1518209498
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2050208353
Short name T557
Test name
Test status
Simulation time 629761257 ps
CPU time 28.46 seconds
Started Apr 23 02:42:22 PM PDT 24
Finished Apr 23 02:42:51 PM PDT 24
Peak memory 199592 kb
Host smart-a54fc13b-0841-468a-a6cf-9537bc115949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050208353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2050208353
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.69017088
Short name T380
Test name
Test status
Simulation time 3848097764 ps
CPU time 111.29 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:44:11 PM PDT 24
Peak memory 199688 kb
Host smart-df2cae94-3f10-40d6-94a6-5bddd8725cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69017088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.69017088
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1764916628
Short name T35
Test name
Test status
Simulation time 4653665375 ps
CPU time 80.39 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:43:42 PM PDT 24
Peak memory 199732 kb
Host smart-b71489bd-8ef1-46c5-9919-afc115e39811
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764916628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1764916628
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.118228833
Short name T567
Test name
Test status
Simulation time 3190246699 ps
CPU time 64.59 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:43:25 PM PDT 24
Peak memory 199704 kb
Host smart-694dc73e-6440-4e8e-b419-48778f7b51b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118228833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.118228833
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.826160533
Short name T472
Test name
Test status
Simulation time 264319477 ps
CPU time 2.18 seconds
Started Apr 23 02:42:19 PM PDT 24
Finished Apr 23 02:42:21 PM PDT 24
Peak memory 199608 kb
Host smart-f32a2f6c-7696-4800-9b04-a15d7ff8b42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826160533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.826160533
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.226026282
Short name T524
Test name
Test status
Simulation time 767884402673 ps
CPU time 1905.15 seconds
Started Apr 23 02:42:20 PM PDT 24
Finished Apr 23 03:14:06 PM PDT 24
Peak memory 240316 kb
Host smart-c7e9ec2a-58ad-4694-ac46-ccc5afa80497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226026282 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.226026282
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.3336988408
Short name T369
Test name
Test status
Simulation time 45064047955 ps
CPU time 832.71 seconds
Started Apr 23 02:42:23 PM PDT 24
Finished Apr 23 02:56:16 PM PDT 24
Peak memory 245220 kb
Host smart-c2e2fd89-dd2f-48d6-9fc8-01c39401b3a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336988408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.3336988408
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3103804316
Short name T189
Test name
Test status
Simulation time 116956296 ps
CPU time 1.25 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:42:23 PM PDT 24
Peak memory 199620 kb
Host smart-69fb281c-b1ac-4e05-b837-e41ccaa348de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103804316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3103804316
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2522655532
Short name T289
Test name
Test status
Simulation time 13734651198 ps
CPU time 385.15 seconds
Started Apr 23 02:42:22 PM PDT 24
Finished Apr 23 02:48:48 PM PDT 24
Peak memory 199648 kb
Host smart-33f5941b-36a8-4d17-85c9-1e593ab4b1d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522655532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2522655532
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1258063393
Short name T439
Test name
Test status
Simulation time 1038314752 ps
CPU time 48.76 seconds
Started Apr 23 02:42:23 PM PDT 24
Finished Apr 23 02:43:13 PM PDT 24
Peak memory 199588 kb
Host smart-eb9a7ebb-1cfa-410d-8aee-6c379c023012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258063393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1258063393
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2396764604
Short name T575
Test name
Test status
Simulation time 18985175 ps
CPU time 0.54 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:42:27 PM PDT 24
Peak memory 195196 kb
Host smart-0b6a2656-3e65-45f9-b5d1-4b7ff6bbf9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396764604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2396764604
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2728194622
Short name T203
Test name
Test status
Simulation time 4411534787 ps
CPU time 40.43 seconds
Started Apr 23 02:42:23 PM PDT 24
Finished Apr 23 02:43:04 PM PDT 24
Peak memory 214200 kb
Host smart-be7fd359-eab5-4e31-ae97-d4cbe496c677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728194622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2728194622
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3791397872
Short name T591
Test name
Test status
Simulation time 559459280 ps
CPU time 6.45 seconds
Started Apr 23 02:42:25 PM PDT 24
Finished Apr 23 02:42:31 PM PDT 24
Peak memory 199532 kb
Host smart-9e859efd-9162-4db7-9eeb-7d362c165442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791397872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3791397872
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3086559608
Short name T406
Test name
Test status
Simulation time 2766556570 ps
CPU time 52.68 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:43:14 PM PDT 24
Peak memory 199744 kb
Host smart-7668643d-6847-4aef-86ca-92d3146b6777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086559608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3086559608
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3441483912
Short name T491
Test name
Test status
Simulation time 3916195758 ps
CPU time 23.47 seconds
Started Apr 23 02:42:25 PM PDT 24
Finished Apr 23 02:42:49 PM PDT 24
Peak memory 199740 kb
Host smart-613a2f2a-04fc-44d8-8ad0-6a252500be3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441483912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3441483912
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.667266005
Short name T225
Test name
Test status
Simulation time 7437036900 ps
CPU time 39.38 seconds
Started Apr 23 02:42:21 PM PDT 24
Finished Apr 23 02:43:01 PM PDT 24
Peak memory 199692 kb
Host smart-054930fa-cb61-457e-bce9-404e2c65ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667266005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.667266005
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3582895856
Short name T349
Test name
Test status
Simulation time 610046087 ps
CPU time 3.86 seconds
Started Apr 23 02:42:22 PM PDT 24
Finished Apr 23 02:42:26 PM PDT 24
Peak memory 199604 kb
Host smart-b01aa899-0c20-46c8-8a7a-2ed061f7a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582895856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3582895856
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3292006027
Short name T75
Test name
Test status
Simulation time 40402747050 ps
CPU time 516.37 seconds
Started Apr 23 02:42:24 PM PDT 24
Finished Apr 23 02:51:01 PM PDT 24
Peak memory 199740 kb
Host smart-88598864-c1b6-48b0-b079-7977f19d6a89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292006027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3292006027
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3303801165
Short name T236
Test name
Test status
Simulation time 116690113 ps
CPU time 1.34 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:42:28 PM PDT 24
Peak memory 199572 kb
Host smart-36997030-55c1-4d53-a112-1e6f5759620f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303801165 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3303801165
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2116163206
Short name T226
Test name
Test status
Simulation time 118371173112 ps
CPU time 524.05 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:51:11 PM PDT 24
Peak memory 199708 kb
Host smart-29489fa0-8728-471a-9707-42531b768a31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116163206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2116163206
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.366322616
Short name T287
Test name
Test status
Simulation time 2808142625 ps
CPU time 51.82 seconds
Started Apr 23 02:42:28 PM PDT 24
Finished Apr 23 02:43:20 PM PDT 24
Peak memory 199704 kb
Host smart-055042ef-6a1d-4bcb-b8c0-89b2bb386194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366322616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.366322616
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2883074769
Short name T208
Test name
Test status
Simulation time 28255529 ps
CPU time 0.54 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:42:30 PM PDT 24
Peak memory 194832 kb
Host smart-a24cde19-f7be-40f0-938f-42adf78bcc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883074769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2883074769
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3841359840
Short name T341
Test name
Test status
Simulation time 1063628899 ps
CPU time 39.94 seconds
Started Apr 23 02:42:27 PM PDT 24
Finished Apr 23 02:43:07 PM PDT 24
Peak memory 216956 kb
Host smart-16464bd2-cce1-46c4-b70d-e61981ed6243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841359840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3841359840
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.600047134
Short name T286
Test name
Test status
Simulation time 6013195530 ps
CPU time 64.82 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:43:32 PM PDT 24
Peak memory 199736 kb
Host smart-23413785-9957-46c9-8765-f7087bc20709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600047134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.600047134
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.825983015
Short name T195
Test name
Test status
Simulation time 2087581210 ps
CPU time 114.25 seconds
Started Apr 23 02:42:24 PM PDT 24
Finished Apr 23 02:44:19 PM PDT 24
Peak memory 199552 kb
Host smart-345f65bf-9a3f-4d29-8132-992b41e9267f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825983015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.825983015
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3791461202
Short name T193
Test name
Test status
Simulation time 2237949461 ps
CPU time 58.08 seconds
Started Apr 23 02:42:27 PM PDT 24
Finished Apr 23 02:43:25 PM PDT 24
Peak memory 199640 kb
Host smart-efafea98-f086-42c1-90a5-02f7fb5fba9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791461202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3791461202
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3759475084
Short name T282
Test name
Test status
Simulation time 540512681 ps
CPU time 32.04 seconds
Started Apr 23 02:42:24 PM PDT 24
Finished Apr 23 02:42:56 PM PDT 24
Peak memory 199532 kb
Host smart-735712d6-bceb-4b2f-b2ce-987c036dde67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759475084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3759475084
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3194182129
Short name T206
Test name
Test status
Simulation time 454245060 ps
CPU time 5.39 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:42:32 PM PDT 24
Peak memory 199604 kb
Host smart-54d961a7-c156-408c-8b65-3899d42f11a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194182129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3194182129
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.4279551149
Short name T204
Test name
Test status
Simulation time 95833860496 ps
CPU time 487.15 seconds
Started Apr 23 02:42:30 PM PDT 24
Finished Apr 23 02:50:38 PM PDT 24
Peak memory 240724 kb
Host smart-8ee0b1cf-1aef-49bc-a6ef-cda39801eb45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279551149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.4279551149
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2712790256
Short name T122
Test name
Test status
Simulation time 451095378 ps
CPU time 1.37 seconds
Started Apr 23 02:42:26 PM PDT 24
Finished Apr 23 02:42:28 PM PDT 24
Peak memory 199612 kb
Host smart-f474dbdf-9ea2-496f-8558-e51b168bc8c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712790256 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2712790256
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1614646690
Short name T426
Test name
Test status
Simulation time 90593428808 ps
CPU time 555.71 seconds
Started Apr 23 02:42:23 PM PDT 24
Finished Apr 23 02:51:40 PM PDT 24
Peak memory 199692 kb
Host smart-b1d5bbad-f295-4c1c-a3e6-ac46b302a4ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614646690 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1614646690
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3289245728
Short name T27
Test name
Test status
Simulation time 21101420088 ps
CPU time 78.12 seconds
Started Apr 23 02:42:28 PM PDT 24
Finished Apr 23 02:43:46 PM PDT 24
Peak memory 199736 kb
Host smart-7ebc2127-d5e0-4d18-887b-c80d0db13185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289245728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3289245728
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3195114415
Short name T249
Test name
Test status
Simulation time 827223225 ps
CPU time 28.69 seconds
Started Apr 23 02:42:27 PM PDT 24
Finished Apr 23 02:42:56 PM PDT 24
Peak memory 229316 kb
Host smart-ed6362d0-7736-416f-a43b-ee64adfccce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195114415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3195114415
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2660838352
Short name T535
Test name
Test status
Simulation time 3710440109 ps
CPU time 39.45 seconds
Started Apr 23 02:42:27 PM PDT 24
Finished Apr 23 02:43:07 PM PDT 24
Peak memory 199752 kb
Host smart-a3840ae6-6759-47a9-9dad-850ac337dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660838352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2660838352
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1209270006
Short name T182
Test name
Test status
Simulation time 629462472 ps
CPU time 8.57 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 02:42:42 PM PDT 24
Peak memory 199568 kb
Host smart-ee895164-09c9-4606-a49a-b74af0afdbea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1209270006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1209270006
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2335904644
Short name T51
Test name
Test status
Simulation time 2615184134 ps
CPU time 135.18 seconds
Started Apr 23 02:42:28 PM PDT 24
Finished Apr 23 02:44:44 PM PDT 24
Peak memory 199784 kb
Host smart-888b432d-5809-47c2-81bd-7796cb5ab667
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335904644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2335904644
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1543409547
Short name T542
Test name
Test status
Simulation time 22466593531 ps
CPU time 83.54 seconds
Started Apr 23 02:42:32 PM PDT 24
Finished Apr 23 02:43:56 PM PDT 24
Peak memory 199740 kb
Host smart-933c60b5-a5e8-4523-92fb-33fe4f535959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543409547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1543409547
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3042908562
Short name T69
Test name
Test status
Simulation time 205304760 ps
CPU time 1.87 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:42:32 PM PDT 24
Peak memory 199600 kb
Host smart-b4545894-41a0-4b4b-b94e-ca0950a9b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042908562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3042908562
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3805836031
Short name T431
Test name
Test status
Simulation time 6470021297 ps
CPU time 4.88 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 02:42:38 PM PDT 24
Peak memory 199740 kb
Host smart-edfe7e5f-1249-456f-930c-ec006ebe6189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805836031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3805836031
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2579938236
Short name T270
Test name
Test status
Simulation time 29975445 ps
CPU time 0.93 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:42:31 PM PDT 24
Peak memory 198684 kb
Host smart-927294fe-efc1-4c8a-8448-97163502f6e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579938236 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2579938236
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1074901408
Short name T421
Test name
Test status
Simulation time 21982712414 ps
CPU time 435.17 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:49:44 PM PDT 24
Peak memory 199720 kb
Host smart-f403ba8c-7de8-4089-944f-3e5d46ef90ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074901408 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1074901408
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2254833287
Short name T224
Test name
Test status
Simulation time 6122303524 ps
CPU time 20.22 seconds
Started Apr 23 02:42:30 PM PDT 24
Finished Apr 23 02:42:50 PM PDT 24
Peak memory 199676 kb
Host smart-5f63d638-22ea-42f5-aa92-40092c39e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254833287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2254833287
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1557995840
Short name T424
Test name
Test status
Simulation time 21176202 ps
CPU time 0.58 seconds
Started Apr 23 02:40:39 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 195144 kb
Host smart-8f41ba50-5a4a-4718-a27b-114150482f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557995840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1557995840
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1521956838
Short name T597
Test name
Test status
Simulation time 1041967354 ps
CPU time 33.8 seconds
Started Apr 23 02:40:35 PM PDT 24
Finished Apr 23 02:41:09 PM PDT 24
Peak memory 215100 kb
Host smart-e53e798c-b5c5-40f8-9219-fbb213467bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521956838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1521956838
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2037099980
Short name T581
Test name
Test status
Simulation time 876209037 ps
CPU time 12.76 seconds
Started Apr 23 02:40:36 PM PDT 24
Finished Apr 23 02:40:50 PM PDT 24
Peak memory 199620 kb
Host smart-d3132a6d-e709-4b4a-89f5-7aa7c5130335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037099980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2037099980
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.212860509
Short name T297
Test name
Test status
Simulation time 4926999258 ps
CPU time 61.19 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:41:36 PM PDT 24
Peak memory 199728 kb
Host smart-49eba2c5-c10b-4fb0-8185-507a552c4155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212860509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.212860509
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1003563861
Short name T238
Test name
Test status
Simulation time 6509347844 ps
CPU time 50.31 seconds
Started Apr 23 02:40:36 PM PDT 24
Finished Apr 23 02:41:27 PM PDT 24
Peak memory 199728 kb
Host smart-7f5bf33b-a20a-4e70-8fe0-db1f906aefc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003563861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1003563861
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1411583845
Short name T600
Test name
Test status
Simulation time 114448602 ps
CPU time 5.96 seconds
Started Apr 23 02:40:35 PM PDT 24
Finished Apr 23 02:40:41 PM PDT 24
Peak memory 199608 kb
Host smart-570fc44f-b9ba-499b-be5e-d6c6d2783778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411583845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1411583845
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.541269444
Short name T494
Test name
Test status
Simulation time 1435364121 ps
CPU time 5.29 seconds
Started Apr 23 02:40:37 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 199628 kb
Host smart-a4d3d93d-ffc2-4c64-91ea-9bf60c051e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541269444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.541269444
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1588305808
Short name T336
Test name
Test status
Simulation time 208800052724 ps
CPU time 1025.52 seconds
Started Apr 23 02:40:35 PM PDT 24
Finished Apr 23 02:57:41 PM PDT 24
Peak memory 199668 kb
Host smart-14d664b2-d9a0-4e2f-bd5d-4a1c21c48706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588305808 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1588305808
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.168312203
Short name T521
Test name
Test status
Simulation time 324100633 ps
CPU time 1.29 seconds
Started Apr 23 02:40:34 PM PDT 24
Finished Apr 23 02:40:36 PM PDT 24
Peak memory 199476 kb
Host smart-e3c0500a-d62c-4d3e-bf2f-331035c466f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168312203 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.168312203
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2501087267
Short name T244
Test name
Test status
Simulation time 58967447832 ps
CPU time 507.3 seconds
Started Apr 23 02:40:33 PM PDT 24
Finished Apr 23 02:49:01 PM PDT 24
Peak memory 199720 kb
Host smart-2a0407bb-1dc6-4423-84ca-dc557ebe148b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501087267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2501087267
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1990600356
Short name T288
Test name
Test status
Simulation time 2019311418 ps
CPU time 82.99 seconds
Started Apr 23 02:40:36 PM PDT 24
Finished Apr 23 02:41:59 PM PDT 24
Peak memory 199552 kb
Host smart-53e8c96b-c607-4d26-a3fb-9849ba4d02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990600356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1990600356
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.251772363
Short name T21
Test name
Test status
Simulation time 54667135 ps
CPU time 0.57 seconds
Started Apr 23 02:42:31 PM PDT 24
Finished Apr 23 02:42:32 PM PDT 24
Peak memory 194124 kb
Host smart-b46e1a78-11f8-498a-ad69-bd3735768731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251772363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.251772363
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.989209463
Short name T151
Test name
Test status
Simulation time 1210735551 ps
CPU time 29.33 seconds
Started Apr 23 02:42:30 PM PDT 24
Finished Apr 23 02:43:00 PM PDT 24
Peak memory 237432 kb
Host smart-b163d7ac-04e3-4e2f-8815-63fa036e19aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989209463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.989209463
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2505523710
Short name T255
Test name
Test status
Simulation time 1056578851 ps
CPU time 52.48 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 02:43:26 PM PDT 24
Peak memory 199628 kb
Host smart-b33d1fe3-13db-4310-b9fb-db81a5c1e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505523710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2505523710
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3055613789
Short name T207
Test name
Test status
Simulation time 24681667 ps
CPU time 0.67 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 02:42:34 PM PDT 24
Peak memory 196876 kb
Host smart-15a27c0c-6c0a-4527-9ad8-aefb8eb0320b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055613789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3055613789
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2748689749
Short name T30
Test name
Test status
Simulation time 197340510587 ps
CPU time 219.33 seconds
Started Apr 23 02:42:32 PM PDT 24
Finished Apr 23 02:46:12 PM PDT 24
Peak memory 199736 kb
Host smart-e84c2727-73d6-44b4-9c26-0a140de8d7d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748689749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2748689749
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3843544468
Short name T396
Test name
Test status
Simulation time 1644831505 ps
CPU time 49.3 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:43:19 PM PDT 24
Peak memory 199612 kb
Host smart-9dd22398-6580-427d-9faa-e7ebc053b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843544468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3843544468
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2286491542
Short name T145
Test name
Test status
Simulation time 1276327321 ps
CPU time 4.72 seconds
Started Apr 23 02:42:29 PM PDT 24
Finished Apr 23 02:42:34 PM PDT 24
Peak memory 199596 kb
Host smart-13e9ca8d-071f-4fb0-a23e-9d4ac48a411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286491542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2286491542
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1542634025
Short name T541
Test name
Test status
Simulation time 77444737562 ps
CPU time 1432.67 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 03:06:27 PM PDT 24
Peak memory 215912 kb
Host smart-def7e5b6-d570-48df-9522-f851b0e5c664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542634025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1542634025
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.3366698488
Short name T101
Test name
Test status
Simulation time 43584065585 ps
CPU time 666.28 seconds
Started Apr 23 02:42:34 PM PDT 24
Finished Apr 23 02:53:41 PM PDT 24
Peak memory 215800 kb
Host smart-64071d01-c1f0-41f1-8e35-aa945d451a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366698488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.3366698488
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1946985901
Short name T367
Test name
Test status
Simulation time 48812575 ps
CPU time 1.04 seconds
Started Apr 23 02:42:34 PM PDT 24
Finished Apr 23 02:42:36 PM PDT 24
Peak memory 198652 kb
Host smart-d2ab4ad7-87b3-42f4-98cb-26ea37f054d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946985901 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1946985901
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2780770520
Short name T269
Test name
Test status
Simulation time 26315679569 ps
CPU time 423.8 seconds
Started Apr 23 02:42:34 PM PDT 24
Finished Apr 23 02:49:38 PM PDT 24
Peak memory 199668 kb
Host smart-cc6ce453-401a-4aca-a81b-858314e38f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780770520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2780770520
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1288119259
Short name T384
Test name
Test status
Simulation time 9261713102 ps
CPU time 47.04 seconds
Started Apr 23 02:42:33 PM PDT 24
Finished Apr 23 02:43:20 PM PDT 24
Peak memory 199728 kb
Host smart-f09095cc-d7fb-4e9b-a0c3-0154eb538e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288119259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1288119259
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2650318451
Short name T156
Test name
Test status
Simulation time 10810913 ps
CPU time 0.59 seconds
Started Apr 23 02:42:37 PM PDT 24
Finished Apr 23 02:42:38 PM PDT 24
Peak memory 194164 kb
Host smart-bd0dfbe8-2ee4-48b2-beba-0eec5aaea7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650318451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2650318451
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3096495803
Short name T469
Test name
Test status
Simulation time 206845616 ps
CPU time 7.48 seconds
Started Apr 23 02:42:32 PM PDT 24
Finished Apr 23 02:42:40 PM PDT 24
Peak memory 215732 kb
Host smart-72c96d15-5360-4ebc-a478-edb01edb3317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096495803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3096495803
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2010231961
Short name T579
Test name
Test status
Simulation time 2037022064 ps
CPU time 20.37 seconds
Started Apr 23 02:42:35 PM PDT 24
Finished Apr 23 02:42:56 PM PDT 24
Peak memory 199552 kb
Host smart-054458d5-2cf6-442c-b314-f5df32130a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010231961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2010231961
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.107109512
Short name T408
Test name
Test status
Simulation time 1898436751 ps
CPU time 50.45 seconds
Started Apr 23 02:42:36 PM PDT 24
Finished Apr 23 02:43:26 PM PDT 24
Peak memory 199600 kb
Host smart-8979f516-9d4d-4dd0-b25f-6a23a07c07d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107109512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.107109512
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3253825260
Short name T394
Test name
Test status
Simulation time 1561065167 ps
CPU time 81.64 seconds
Started Apr 23 02:42:37 PM PDT 24
Finished Apr 23 02:43:59 PM PDT 24
Peak memory 199592 kb
Host smart-c47090fe-dbf7-4790-b9fb-8bc4ed384c0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253825260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3253825260
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2206850622
Short name T407
Test name
Test status
Simulation time 1081574973 ps
CPU time 14.89 seconds
Started Apr 23 02:42:32 PM PDT 24
Finished Apr 23 02:42:48 PM PDT 24
Peak memory 199524 kb
Host smart-a8bee84c-9bec-497e-9096-9a583413b991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206850622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2206850622
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3014231461
Short name T223
Test name
Test status
Simulation time 1082854884 ps
CPU time 3.91 seconds
Started Apr 23 02:42:34 PM PDT 24
Finished Apr 23 02:42:39 PM PDT 24
Peak memory 199568 kb
Host smart-f8fd04c4-db7b-4c63-aabb-ee96f1b871b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014231461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3014231461
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2083584811
Short name T391
Test name
Test status
Simulation time 15669469754 ps
CPU time 200.12 seconds
Started Apr 23 02:42:36 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 199764 kb
Host smart-2aed33e7-18bd-4180-b0d3-20f8b0fb7deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083584811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2083584811
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2131699141
Short name T166
Test name
Test status
Simulation time 137346481 ps
CPU time 1 seconds
Started Apr 23 02:42:36 PM PDT 24
Finished Apr 23 02:42:38 PM PDT 24
Peak memory 198316 kb
Host smart-abbcc98d-afd7-4f71-9ac0-218724d09ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131699141 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2131699141
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1191084300
Short name T354
Test name
Test status
Simulation time 7558621689 ps
CPU time 402.63 seconds
Started Apr 23 02:42:36 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 199688 kb
Host smart-34d8c2cc-898e-4cba-b310-d2728119c2c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191084300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1191084300
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1900712200
Short name T272
Test name
Test status
Simulation time 19113702405 ps
CPU time 66.22 seconds
Started Apr 23 02:42:34 PM PDT 24
Finished Apr 23 02:43:41 PM PDT 24
Peak memory 199716 kb
Host smart-e9fc2a06-16ee-4471-8ce8-2b5b0a191293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900712200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1900712200
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.144855523
Short name T243
Test name
Test status
Simulation time 42273647 ps
CPU time 0.56 seconds
Started Apr 23 02:42:41 PM PDT 24
Finished Apr 23 02:42:42 PM PDT 24
Peak memory 194876 kb
Host smart-c377321f-c7a4-4a59-a3cc-7ab1259cd84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144855523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.144855523
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3613850049
Short name T292
Test name
Test status
Simulation time 2537833481 ps
CPU time 47.12 seconds
Started Apr 23 02:42:40 PM PDT 24
Finished Apr 23 02:43:28 PM PDT 24
Peak memory 230452 kb
Host smart-76b79374-3a82-4f3a-8892-2ac3533e790c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613850049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3613850049
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1182416299
Short name T188
Test name
Test status
Simulation time 1381707858 ps
CPU time 71.97 seconds
Started Apr 23 02:42:40 PM PDT 24
Finished Apr 23 02:43:53 PM PDT 24
Peak memory 199604 kb
Host smart-013e435e-d0d7-4e5a-aecf-8dd43fbbea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182416299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1182416299
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.130469794
Short name T452
Test name
Test status
Simulation time 94246705 ps
CPU time 0.74 seconds
Started Apr 23 02:42:38 PM PDT 24
Finished Apr 23 02:42:40 PM PDT 24
Peak memory 196852 kb
Host smart-7aecfec2-f304-4b4d-9e41-cbc2a9b6264c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130469794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.130469794
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.543143951
Short name T428
Test name
Test status
Simulation time 2590934059 ps
CPU time 140.01 seconds
Started Apr 23 02:42:39 PM PDT 24
Finished Apr 23 02:44:59 PM PDT 24
Peak memory 199716 kb
Host smart-e6a4f157-7df3-4111-8741-4b1ae55b679a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543143951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.543143951
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2161244167
Short name T327
Test name
Test status
Simulation time 9027887868 ps
CPU time 75 seconds
Started Apr 23 02:42:41 PM PDT 24
Finished Apr 23 02:43:56 PM PDT 24
Peak memory 199704 kb
Host smart-6dbff23b-09ca-4314-bd3c-6a567d458b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161244167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2161244167
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2413944306
Short name T337
Test name
Test status
Simulation time 216139680 ps
CPU time 6.67 seconds
Started Apr 23 02:42:36 PM PDT 24
Finished Apr 23 02:42:44 PM PDT 24
Peak memory 199548 kb
Host smart-ff90dffe-c469-4e52-a8d8-0b6f0b3a092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413944306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2413944306
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1155791493
Short name T578
Test name
Test status
Simulation time 5016302864 ps
CPU time 43.23 seconds
Started Apr 23 02:42:39 PM PDT 24
Finished Apr 23 02:43:23 PM PDT 24
Peak memory 199736 kb
Host smart-058c73d1-07f4-40df-83cc-293e3deab79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155791493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1155791493
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.221203522
Short name T454
Test name
Test status
Simulation time 148609936 ps
CPU time 1 seconds
Started Apr 23 02:42:39 PM PDT 24
Finished Apr 23 02:42:41 PM PDT 24
Peak memory 198876 kb
Host smart-7e1b9895-49d3-4182-86e5-473fced9dc1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221203522 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.221203522
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1924602800
Short name T147
Test name
Test status
Simulation time 77966710692 ps
CPU time 524.89 seconds
Started Apr 23 02:42:38 PM PDT 24
Finished Apr 23 02:51:24 PM PDT 24
Peak memory 199620 kb
Host smart-3991e6e6-fe9a-4161-bd67-e27e68ca90bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924602800 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1924602800
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.288617363
Short name T237
Test name
Test status
Simulation time 1169748746 ps
CPU time 18 seconds
Started Apr 23 02:42:40 PM PDT 24
Finished Apr 23 02:42:59 PM PDT 24
Peak memory 199572 kb
Host smart-7bb82cf8-b327-4145-aa56-d162a7673380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288617363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.288617363
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3150368403
Short name T480
Test name
Test status
Simulation time 17050496 ps
CPU time 0.63 seconds
Started Apr 23 02:42:47 PM PDT 24
Finished Apr 23 02:42:48 PM PDT 24
Peak memory 194848 kb
Host smart-63d77e3d-21fc-45c5-9b01-89d9d46bef27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150368403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3150368403
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3168290486
Short name T175
Test name
Test status
Simulation time 375315363 ps
CPU time 12.04 seconds
Started Apr 23 02:42:43 PM PDT 24
Finished Apr 23 02:42:55 PM PDT 24
Peak memory 205780 kb
Host smart-d30265a2-d7f6-43d9-bb7e-306d6c937470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168290486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3168290486
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2978815970
Short name T402
Test name
Test status
Simulation time 7567846214 ps
CPU time 33.12 seconds
Started Apr 23 02:42:47 PM PDT 24
Finished Apr 23 02:43:21 PM PDT 24
Peak memory 199692 kb
Host smart-628e9022-b394-4717-9bf1-5b0ff44c3da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978815970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2978815970
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1549721436
Short name T561
Test name
Test status
Simulation time 2767704331 ps
CPU time 151.11 seconds
Started Apr 23 02:42:42 PM PDT 24
Finished Apr 23 02:45:14 PM PDT 24
Peak memory 199732 kb
Host smart-a4a14bd1-3aec-4c76-871b-0dbdc9c2d045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549721436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1549721436
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3383718276
Short name T465
Test name
Test status
Simulation time 11806185612 ps
CPU time 155.2 seconds
Started Apr 23 02:42:52 PM PDT 24
Finished Apr 23 02:45:28 PM PDT 24
Peak memory 199696 kb
Host smart-14233086-ff98-4402-8757-17511f9fc01b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383718276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3383718276
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3465692040
Short name T139
Test name
Test status
Simulation time 2659340854 ps
CPU time 13.22 seconds
Started Apr 23 02:42:43 PM PDT 24
Finished Apr 23 02:42:57 PM PDT 24
Peak memory 199688 kb
Host smart-6d98f259-f4b5-4a4d-8130-8eb006a85faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465692040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3465692040
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.158659428
Short name T478
Test name
Test status
Simulation time 133510653 ps
CPU time 3.88 seconds
Started Apr 23 02:42:42 PM PDT 24
Finished Apr 23 02:42:46 PM PDT 24
Peak memory 199616 kb
Host smart-9c50ba2f-bc2a-4774-b301-43d9127ca838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158659428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.158659428
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1731675720
Short name T11
Test name
Test status
Simulation time 50264175792 ps
CPU time 638.24 seconds
Started Apr 23 02:42:48 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 199680 kb
Host smart-9a3f180d-9893-4daa-a929-735a8e316977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731675720 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1731675720
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.948990080
Short name T265
Test name
Test status
Simulation time 73299971 ps
CPU time 1.24 seconds
Started Apr 23 02:42:46 PM PDT 24
Finished Apr 23 02:42:48 PM PDT 24
Peak memory 199556 kb
Host smart-99b0f22f-b111-44ad-abba-0610ca97cc7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948990080 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.948990080
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3241666818
Short name T352
Test name
Test status
Simulation time 132342410038 ps
CPU time 444.9 seconds
Started Apr 23 02:42:49 PM PDT 24
Finished Apr 23 02:50:14 PM PDT 24
Peak memory 199676 kb
Host smart-9565f9fb-93dd-4714-a3d1-a6fa993dd52f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241666818 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3241666818
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3536741377
Short name T543
Test name
Test status
Simulation time 6484766320 ps
CPU time 56.73 seconds
Started Apr 23 02:42:47 PM PDT 24
Finished Apr 23 02:43:44 PM PDT 24
Peak memory 199676 kb
Host smart-e89c5391-fdfe-4a24-8b12-d0f81d4646fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536741377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3536741377
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.350865682
Short name T476
Test name
Test status
Simulation time 41984054 ps
CPU time 0.57 seconds
Started Apr 23 02:42:50 PM PDT 24
Finished Apr 23 02:42:51 PM PDT 24
Peak memory 195272 kb
Host smart-22f30b63-56cc-4f8c-9a60-f9723025171c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350865682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.350865682
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.618540680
Short name T377
Test name
Test status
Simulation time 221640642 ps
CPU time 8.34 seconds
Started Apr 23 02:42:48 PM PDT 24
Finished Apr 23 02:42:57 PM PDT 24
Peak memory 207820 kb
Host smart-04c08085-0e04-48a5-862b-e32d4e40347f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618540680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.618540680
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4022108113
Short name T397
Test name
Test status
Simulation time 1657073376 ps
CPU time 6.64 seconds
Started Apr 23 02:42:47 PM PDT 24
Finished Apr 23 02:42:54 PM PDT 24
Peak memory 199580 kb
Host smart-42f4a3f2-5db9-4cde-8b1f-0fdb99811e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022108113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4022108113
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3377284751
Short name T230
Test name
Test status
Simulation time 14940514 ps
CPU time 0.65 seconds
Started Apr 23 02:42:45 PM PDT 24
Finished Apr 23 02:42:46 PM PDT 24
Peak memory 196820 kb
Host smart-9c1317e1-7a04-4e87-9d40-1684d6a3db0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377284751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3377284751
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3215606716
Short name T558
Test name
Test status
Simulation time 927341500 ps
CPU time 47.56 seconds
Started Apr 23 02:42:49 PM PDT 24
Finished Apr 23 02:43:37 PM PDT 24
Peak memory 199520 kb
Host smart-d0f7463d-c2ef-433d-b933-ed267d2174e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215606716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3215606716
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2341853696
Short name T305
Test name
Test status
Simulation time 5575380124 ps
CPU time 81.7 seconds
Started Apr 23 02:42:48 PM PDT 24
Finished Apr 23 02:44:10 PM PDT 24
Peak memory 199704 kb
Host smart-15c1e47f-07dc-443c-a3f4-da2d993f323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341853696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2341853696
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.440221803
Short name T82
Test name
Test status
Simulation time 161294965 ps
CPU time 3.83 seconds
Started Apr 23 02:42:49 PM PDT 24
Finished Apr 23 02:42:53 PM PDT 24
Peak memory 199592 kb
Host smart-72596a76-8646-45fd-a4ca-0b558449665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440221803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.440221803
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3811248297
Short name T417
Test name
Test status
Simulation time 81263894351 ps
CPU time 726.37 seconds
Started Apr 23 02:42:51 PM PDT 24
Finished Apr 23 02:54:58 PM PDT 24
Peak memory 199740 kb
Host smart-e86d82ab-f7f4-4f65-ae39-db155dd2465e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811248297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3811248297
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2592889975
Short name T514
Test name
Test status
Simulation time 97699166 ps
CPU time 0.93 seconds
Started Apr 23 02:42:50 PM PDT 24
Finished Apr 23 02:42:52 PM PDT 24
Peak memory 198028 kb
Host smart-2cee9f83-8586-4210-8411-0408f213b9f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592889975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2592889975
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.531596323
Short name T335
Test name
Test status
Simulation time 41156021173 ps
CPU time 465.2 seconds
Started Apr 23 02:42:49 PM PDT 24
Finished Apr 23 02:50:34 PM PDT 24
Peak memory 199724 kb
Host smart-802b8161-b679-4381-8533-3aa6bd79a845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531596323 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.531596323
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.913800325
Short name T180
Test name
Test status
Simulation time 3885021933 ps
CPU time 39.82 seconds
Started Apr 23 02:42:51 PM PDT 24
Finished Apr 23 02:43:31 PM PDT 24
Peak memory 199716 kb
Host smart-8828582d-42d0-4e2a-9fc4-43b0a423aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913800325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.913800325
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2916637380
Short name T503
Test name
Test status
Simulation time 30799481 ps
CPU time 0.59 seconds
Started Apr 23 02:42:57 PM PDT 24
Finished Apr 23 02:42:58 PM PDT 24
Peak memory 195248 kb
Host smart-cf4df821-9df6-4643-af38-5d892558d709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916637380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2916637380
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1399148435
Short name T162
Test name
Test status
Simulation time 8203969408 ps
CPU time 26.8 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:22 PM PDT 24
Peak memory 207872 kb
Host smart-d74ec665-0790-425d-9081-f0981668c671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399148435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1399148435
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3450789031
Short name T473
Test name
Test status
Simulation time 2148637705 ps
CPU time 27.69 seconds
Started Apr 23 02:42:52 PM PDT 24
Finished Apr 23 02:43:20 PM PDT 24
Peak memory 199652 kb
Host smart-e64ae548-a9ba-41fc-b0c3-38195a99aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450789031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3450789031
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1692202708
Short name T346
Test name
Test status
Simulation time 589002470 ps
CPU time 32.95 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:29 PM PDT 24
Peak memory 199584 kb
Host smart-c5aa85f8-a99e-4a24-97e2-a59301d23618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692202708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1692202708
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3279457311
Short name T261
Test name
Test status
Simulation time 16632704200 ps
CPU time 105.47 seconds
Started Apr 23 02:42:52 PM PDT 24
Finished Apr 23 02:44:38 PM PDT 24
Peak memory 199744 kb
Host smart-34b0362d-dcab-4c14-88ed-df03ab17ae03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279457311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3279457311
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3130565751
Short name T94
Test name
Test status
Simulation time 9891096018 ps
CPU time 112.65 seconds
Started Apr 23 02:42:52 PM PDT 24
Finished Apr 23 02:44:45 PM PDT 24
Peak memory 199652 kb
Host smart-1775fba5-dc66-4d40-b7a3-81e1f64b5e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130565751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3130565751
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1052070046
Short name T362
Test name
Test status
Simulation time 412180068 ps
CPU time 3.5 seconds
Started Apr 23 02:42:50 PM PDT 24
Finished Apr 23 02:42:54 PM PDT 24
Peak memory 199600 kb
Host smart-3ae5587c-55b8-4ef0-9e00-5d1e9db67cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052070046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1052070046
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.715024401
Short name T571
Test name
Test status
Simulation time 792067649417 ps
CPU time 1548.63 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 03:08:44 PM PDT 24
Peak memory 230704 kb
Host smart-b205aef9-ad5a-41fe-a2ca-bb018a82541f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715024401 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.715024401
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2036563564
Short name T174
Test name
Test status
Simulation time 28405756 ps
CPU time 1.02 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:42:57 PM PDT 24
Peak memory 199104 kb
Host smart-0a27381e-d3b5-4257-b9d4-4d2f71957801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036563564 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2036563564
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.197060600
Short name T209
Test name
Test status
Simulation time 80460321543 ps
CPU time 496.45 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:51:12 PM PDT 24
Peak memory 199692 kb
Host smart-ce03f9d5-60da-4741-8f89-75a38e2603a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197060600 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.197060600
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1790797670
Short name T432
Test name
Test status
Simulation time 6498554405 ps
CPU time 58.21 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:54 PM PDT 24
Peak memory 199748 kb
Host smart-58e259f9-a8d9-4929-a103-9f4651d21f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790797670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1790797670
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3977178027
Short name T519
Test name
Test status
Simulation time 14195059 ps
CPU time 0.6 seconds
Started Apr 23 02:43:00 PM PDT 24
Finished Apr 23 02:43:01 PM PDT 24
Peak memory 195296 kb
Host smart-326d6312-2305-439c-baea-f62880128025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977178027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3977178027
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1280538772
Short name T574
Test name
Test status
Simulation time 1227678295 ps
CPU time 20.5 seconds
Started Apr 23 02:42:58 PM PDT 24
Finished Apr 23 02:43:19 PM PDT 24
Peak memory 212192 kb
Host smart-66c8fba1-2f94-4404-8ce1-5f5f2c695fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1280538772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1280538772
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1854378793
Short name T583
Test name
Test status
Simulation time 388454586 ps
CPU time 18.54 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:15 PM PDT 24
Peak memory 199584 kb
Host smart-baf3c20f-349c-4ca7-9b64-a9bfbff13670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854378793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1854378793
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1595782831
Short name T423
Test name
Test status
Simulation time 615630030 ps
CPU time 33.16 seconds
Started Apr 23 02:42:56 PM PDT 24
Finished Apr 23 02:43:30 PM PDT 24
Peak memory 199552 kb
Host smart-3cd5e826-1085-460b-926c-1b7f68c3e3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595782831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1595782831
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3429024080
Short name T280
Test name
Test status
Simulation time 13223230332 ps
CPU time 187.61 seconds
Started Apr 23 02:42:57 PM PDT 24
Finished Apr 23 02:46:05 PM PDT 24
Peak memory 199736 kb
Host smart-5ce0ccb4-643a-443c-a68c-bf920e182294
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429024080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3429024080
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3100416293
Short name T205
Test name
Test status
Simulation time 50297137336 ps
CPU time 49.71 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:46 PM PDT 24
Peak memory 199736 kb
Host smart-fa82888a-beb9-431b-9449-1d489b6bd14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100416293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3100416293
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2600532765
Short name T153
Test name
Test status
Simulation time 232468595 ps
CPU time 3.54 seconds
Started Apr 23 02:42:56 PM PDT 24
Finished Apr 23 02:43:00 PM PDT 24
Peak memory 199628 kb
Host smart-aead5d24-8c04-426d-856a-e0840e91f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600532765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2600532765
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1221126112
Short name T74
Test name
Test status
Simulation time 594776534950 ps
CPU time 1939.15 seconds
Started Apr 23 02:42:59 PM PDT 24
Finished Apr 23 03:15:19 PM PDT 24
Peak memory 226372 kb
Host smart-c59f3d88-0b78-4986-86c1-b90f788d0ab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221126112 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1221126112
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.276191523
Short name T306
Test name
Test status
Simulation time 71579260 ps
CPU time 1.25 seconds
Started Apr 23 02:43:00 PM PDT 24
Finished Apr 23 02:43:01 PM PDT 24
Peak memory 199544 kb
Host smart-94d89e16-0a21-45d2-9083-1baa3d68e42f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276191523 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.276191523
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2592738086
Short name T445
Test name
Test status
Simulation time 39257809110 ps
CPU time 449.63 seconds
Started Apr 23 02:43:00 PM PDT 24
Finished Apr 23 02:50:30 PM PDT 24
Peak memory 199724 kb
Host smart-5549e64b-3b95-451a-b179-a77d1cb3ac4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592738086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2592738086
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.728172783
Short name T484
Test name
Test status
Simulation time 4948047936 ps
CPU time 56.05 seconds
Started Apr 23 02:42:55 PM PDT 24
Finished Apr 23 02:43:52 PM PDT 24
Peak memory 199648 kb
Host smart-9288fccf-2c16-46c1-b719-836341fea0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728172783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.728172783
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1160677361
Short name T168
Test name
Test status
Simulation time 14639271 ps
CPU time 0.53 seconds
Started Apr 23 02:43:03 PM PDT 24
Finished Apr 23 02:43:04 PM PDT 24
Peak memory 194164 kb
Host smart-4fab57c7-6056-4567-8b30-14166ba6cecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160677361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1160677361
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2746449662
Short name T314
Test name
Test status
Simulation time 826022525 ps
CPU time 8.62 seconds
Started Apr 23 02:43:01 PM PDT 24
Finished Apr 23 02:43:10 PM PDT 24
Peak memory 229920 kb
Host smart-2d3fcc76-9dd8-44ee-a961-d13020a6f390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746449662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2746449662
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3472568994
Short name T510
Test name
Test status
Simulation time 335504807 ps
CPU time 5.38 seconds
Started Apr 23 02:43:03 PM PDT 24
Finished Apr 23 02:43:09 PM PDT 24
Peak memory 199580 kb
Host smart-0f5e63d4-6e0a-4721-88cb-643f439dddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472568994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3472568994
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.989404489
Short name T96
Test name
Test status
Simulation time 6526083820 ps
CPU time 96.55 seconds
Started Apr 23 02:43:03 PM PDT 24
Finished Apr 23 02:44:40 PM PDT 24
Peak memory 199672 kb
Host smart-0e2b75f1-d6b3-4144-9f55-1dcf0669f76e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989404489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.989404489
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2627177568
Short name T364
Test name
Test status
Simulation time 19986730 ps
CPU time 0.63 seconds
Started Apr 23 02:43:02 PM PDT 24
Finished Apr 23 02:43:03 PM PDT 24
Peak memory 195560 kb
Host smart-ea66f7fc-956e-4b2b-bdc2-86a3c0a7be32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627177568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2627177568
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3273334490
Short name T457
Test name
Test status
Simulation time 11456951074 ps
CPU time 32.07 seconds
Started Apr 23 02:43:00 PM PDT 24
Finished Apr 23 02:43:33 PM PDT 24
Peak memory 199676 kb
Host smart-9f1317e3-471a-4a37-bbdf-7aa502349d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273334490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3273334490
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2294218296
Short name T251
Test name
Test status
Simulation time 791276159 ps
CPU time 4.92 seconds
Started Apr 23 02:43:03 PM PDT 24
Finished Apr 23 02:43:08 PM PDT 24
Peak memory 199564 kb
Host smart-e64e8dc1-37ed-47d9-bff2-8e2efab68fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294218296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2294218296
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3327779282
Short name T14
Test name
Test status
Simulation time 70299131325 ps
CPU time 1307.12 seconds
Started Apr 23 02:43:04 PM PDT 24
Finished Apr 23 03:04:52 PM PDT 24
Peak memory 215912 kb
Host smart-326887aa-40f6-4094-bcce-30f408af6497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327779282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3327779282
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2474353968
Short name T183
Test name
Test status
Simulation time 191308283 ps
CPU time 1.26 seconds
Started Apr 23 02:43:03 PM PDT 24
Finished Apr 23 02:43:05 PM PDT 24
Peak memory 199320 kb
Host smart-d9ca5d2d-23b4-4fcc-be5c-8219b9f4427c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474353968 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2474353968
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2843704437
Short name T376
Test name
Test status
Simulation time 30072894083 ps
CPU time 504.12 seconds
Started Apr 23 02:43:04 PM PDT 24
Finished Apr 23 02:51:29 PM PDT 24
Peak memory 199700 kb
Host smart-2d029d80-0c2d-4042-921f-347229e24cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843704437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2843704437
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3598560232
Short name T284
Test name
Test status
Simulation time 856768875 ps
CPU time 22.11 seconds
Started Apr 23 02:43:04 PM PDT 24
Finished Apr 23 02:43:26 PM PDT 24
Peak memory 199616 kb
Host smart-f09562be-9cac-4a3c-ad4e-cdbb812d701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598560232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3598560232
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2414654560
Short name T504
Test name
Test status
Simulation time 45337666 ps
CPU time 0.59 seconds
Started Apr 23 02:43:08 PM PDT 24
Finished Apr 23 02:43:09 PM PDT 24
Peak memory 194852 kb
Host smart-735c6eaa-f532-41ba-bde6-339b1488b309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414654560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2414654560
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3646840118
Short name T506
Test name
Test status
Simulation time 3330747176 ps
CPU time 54.09 seconds
Started Apr 23 02:43:02 PM PDT 24
Finished Apr 23 02:43:56 PM PDT 24
Peak memory 227340 kb
Host smart-6e58a101-7084-4ee0-9e25-99bda27f9246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646840118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3646840118
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1531759384
Short name T142
Test name
Test status
Simulation time 1012391794 ps
CPU time 47.18 seconds
Started Apr 23 02:43:02 PM PDT 24
Finished Apr 23 02:43:50 PM PDT 24
Peak memory 199568 kb
Host smart-66a1c4eb-58d9-4737-8e19-29d60cdf8f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531759384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1531759384
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.558973797
Short name T90
Test name
Test status
Simulation time 16494477896 ps
CPU time 76.24 seconds
Started Apr 23 02:43:10 PM PDT 24
Finished Apr 23 02:44:27 PM PDT 24
Peak memory 199676 kb
Host smart-afa712d8-ef1e-4f5b-817b-717d8159d827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558973797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.558973797
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1510537179
Short name T242
Test name
Test status
Simulation time 306752742 ps
CPU time 16.68 seconds
Started Apr 23 02:43:09 PM PDT 24
Finished Apr 23 02:43:26 PM PDT 24
Peak memory 199560 kb
Host smart-34f50ed0-fda3-44d0-bbd9-a0d9d0ca970f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510537179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1510537179
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3523067221
Short name T312
Test name
Test status
Simulation time 648260216 ps
CPU time 38.06 seconds
Started Apr 23 02:43:05 PM PDT 24
Finished Apr 23 02:43:43 PM PDT 24
Peak memory 199544 kb
Host smart-ee5ab2e2-e466-452d-9402-a41d19d2e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523067221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3523067221
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2495313349
Short name T590
Test name
Test status
Simulation time 2101922459 ps
CPU time 6.5 seconds
Started Apr 23 02:43:04 PM PDT 24
Finished Apr 23 02:43:11 PM PDT 24
Peak memory 199600 kb
Host smart-bd3ceaad-97f7-4a4f-9a69-8f4886457258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495313349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2495313349
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2607963968
Short name T293
Test name
Test status
Simulation time 68034010847 ps
CPU time 903.12 seconds
Started Apr 23 02:43:05 PM PDT 24
Finished Apr 23 02:58:08 PM PDT 24
Peak memory 215196 kb
Host smart-80eb4c14-18fb-44f3-ab32-c4a9d46f6eb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607963968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2607963968
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.171577716
Short name T5
Test name
Test status
Simulation time 194629075411 ps
CPU time 1400.7 seconds
Started Apr 23 02:43:06 PM PDT 24
Finished Apr 23 03:06:27 PM PDT 24
Peak memory 258272 kb
Host smart-89cf3e53-27d2-4c5b-8094-cb84ac290ff2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171577716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.171577716
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.932666115
Short name T325
Test name
Test status
Simulation time 127843387 ps
CPU time 1.26 seconds
Started Apr 23 02:43:06 PM PDT 24
Finished Apr 23 02:43:08 PM PDT 24
Peak memory 199568 kb
Host smart-4a489305-c9f6-4d00-80ea-4aa7e3ff2526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932666115 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.932666115
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2250991037
Short name T2
Test name
Test status
Simulation time 8193702363 ps
CPU time 422.6 seconds
Started Apr 23 02:43:04 PM PDT 24
Finished Apr 23 02:50:07 PM PDT 24
Peak memory 199684 kb
Host smart-f193f45a-3491-4665-bd40-4b5a8eaa48d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250991037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2250991037
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3924359600
Short name T254
Test name
Test status
Simulation time 1288613545 ps
CPU time 13.85 seconds
Started Apr 23 02:43:05 PM PDT 24
Finished Apr 23 02:43:19 PM PDT 24
Peak memory 199464 kb
Host smart-83104607-c3c2-4fd6-ad9d-3074c33eb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924359600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3924359600
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2220876306
Short name T277
Test name
Test status
Simulation time 13466421 ps
CPU time 0.59 seconds
Started Apr 23 02:43:11 PM PDT 24
Finished Apr 23 02:43:11 PM PDT 24
Peak memory 195248 kb
Host smart-43b9affc-80fe-4b3d-b3ec-f1dca890a69d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220876306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2220876306
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1531603896
Short name T422
Test name
Test status
Simulation time 960369111 ps
CPU time 33.51 seconds
Started Apr 23 02:43:08 PM PDT 24
Finished Apr 23 02:43:42 PM PDT 24
Peak memory 221532 kb
Host smart-6caaae05-5b89-44ca-9d92-575a6aef1a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531603896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1531603896
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2512803673
Short name T144
Test name
Test status
Simulation time 1784250770 ps
CPU time 22.92 seconds
Started Apr 23 02:43:10 PM PDT 24
Finished Apr 23 02:43:33 PM PDT 24
Peak memory 199576 kb
Host smart-fbbdf6ba-ee8c-4412-aa58-037eb3c2a6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512803673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2512803673
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1768632485
Short name T146
Test name
Test status
Simulation time 5769558297 ps
CPU time 80.61 seconds
Started Apr 23 02:43:06 PM PDT 24
Finished Apr 23 02:44:27 PM PDT 24
Peak memory 199692 kb
Host smart-67eb8575-308c-4b4e-9df9-258d81124ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768632485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1768632485
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3323708571
Short name T536
Test name
Test status
Simulation time 13269290024 ps
CPU time 225.33 seconds
Started Apr 23 02:43:12 PM PDT 24
Finished Apr 23 02:46:58 PM PDT 24
Peak memory 199720 kb
Host smart-d027cf98-a854-484f-a599-72221a09ddec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323708571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3323708571
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2092702209
Short name T563
Test name
Test status
Simulation time 1432980910 ps
CPU time 41.3 seconds
Started Apr 23 02:43:06 PM PDT 24
Finished Apr 23 02:43:48 PM PDT 24
Peak memory 199588 kb
Host smart-6839f792-ca4f-4b97-b069-7b53dbf6cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092702209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2092702209
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2889411020
Short name T121
Test name
Test status
Simulation time 519571146 ps
CPU time 1.83 seconds
Started Apr 23 02:43:06 PM PDT 24
Finished Apr 23 02:43:08 PM PDT 24
Peak memory 199540 kb
Host smart-09eb4240-45fa-4540-bcf3-1517dffe53ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889411020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2889411020
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3458064292
Short name T150
Test name
Test status
Simulation time 58614466201 ps
CPU time 277.29 seconds
Started Apr 23 02:43:10 PM PDT 24
Finished Apr 23 02:47:48 PM PDT 24
Peak memory 207924 kb
Host smart-a3c50dc5-9108-447f-82a1-31f795743661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458064292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3458064292
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3007479643
Short name T433
Test name
Test status
Simulation time 54818329 ps
CPU time 0.88 seconds
Started Apr 23 02:43:10 PM PDT 24
Finished Apr 23 02:43:11 PM PDT 24
Peak memory 198080 kb
Host smart-fc8b708d-fdaf-4370-8491-77f4d407c7ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007479643 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3007479643
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1647133523
Short name T350
Test name
Test status
Simulation time 71536902121 ps
CPU time 414.57 seconds
Started Apr 23 02:43:10 PM PDT 24
Finished Apr 23 02:50:05 PM PDT 24
Peak memory 199664 kb
Host smart-296c03a3-f7e6-4c74-a037-23ccc7488830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647133523 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1647133523
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4149642364
Short name T582
Test name
Test status
Simulation time 3104413885 ps
CPU time 14.09 seconds
Started Apr 23 02:43:09 PM PDT 24
Finished Apr 23 02:43:23 PM PDT 24
Peak memory 199696 kb
Host smart-0d446bad-8c1c-49da-b44b-0430c93c7cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149642364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4149642364
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1637606486
Short name T245
Test name
Test status
Simulation time 12467634 ps
CPU time 0.58 seconds
Started Apr 23 02:40:42 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 194812 kb
Host smart-55a4c17a-3c1a-4d9d-bfbe-30ac3027c290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637606486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1637606486
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3238439241
Short name T93
Test name
Test status
Simulation time 438714896 ps
CPU time 3.11 seconds
Started Apr 23 02:40:38 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 199548 kb
Host smart-190c96a2-15ce-4aa5-91f1-5368b9c6efa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238439241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3238439241
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2229647188
Short name T211
Test name
Test status
Simulation time 1740541662 ps
CPU time 34.4 seconds
Started Apr 23 02:40:41 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 199556 kb
Host smart-98499d26-34aa-4f69-a731-0b3b913f0c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229647188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2229647188
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.364486501
Short name T544
Test name
Test status
Simulation time 31864858571 ps
CPU time 167.81 seconds
Started Apr 23 02:40:41 PM PDT 24
Finished Apr 23 02:43:30 PM PDT 24
Peak memory 199720 kb
Host smart-71e4000e-e2e6-4c90-b2c1-8a14d0fac19d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364486501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.364486501
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4171860704
Short name T375
Test name
Test status
Simulation time 25630966921 ps
CPU time 67.18 seconds
Started Apr 23 02:40:40 PM PDT 24
Finished Apr 23 02:41:48 PM PDT 24
Peak memory 199660 kb
Host smart-499b4257-03bd-46c2-8eb0-5226510469f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171860704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4171860704
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4077945765
Short name T487
Test name
Test status
Simulation time 14719473869 ps
CPU time 71.12 seconds
Started Apr 23 02:40:40 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 199680 kb
Host smart-51da3922-37e9-4c8d-871a-45500773123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077945765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4077945765
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2269980104
Short name T290
Test name
Test status
Simulation time 560096957 ps
CPU time 2.4 seconds
Started Apr 23 02:40:39 PM PDT 24
Finished Apr 23 02:40:41 PM PDT 24
Peak memory 199632 kb
Host smart-65d6c93f-d596-4da5-b7ce-b78b2df28510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269980104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2269980104
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1313667633
Short name T77
Test name
Test status
Simulation time 46934983097 ps
CPU time 68.94 seconds
Started Apr 23 02:40:42 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 216088 kb
Host smart-b50fadad-2815-47b6-bb51-37d586eff2d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313667633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1313667633
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.167428162
Short name T322
Test name
Test status
Simulation time 33146092 ps
CPU time 1.17 seconds
Started Apr 23 02:40:44 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 199548 kb
Host smart-e3f8e615-3df8-4287-af13-1bcf57270ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167428162 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.167428162
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2640220045
Short name T540
Test name
Test status
Simulation time 154482599569 ps
CPU time 449.68 seconds
Started Apr 23 02:40:42 PM PDT 24
Finished Apr 23 02:48:12 PM PDT 24
Peak memory 199660 kb
Host smart-082d9e9e-003c-43b1-b208-68f75dbc2535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640220045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2640220045
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.649970724
Short name T434
Test name
Test status
Simulation time 30207774508 ps
CPU time 83.61 seconds
Started Apr 23 02:40:42 PM PDT 24
Finished Apr 23 02:42:06 PM PDT 24
Peak memory 199672 kb
Host smart-6222f534-4720-4908-b8a9-ab67e8c6f395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649970724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.649970724
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1676930220
Short name T474
Test name
Test status
Simulation time 43700339 ps
CPU time 0.58 seconds
Started Apr 23 02:40:46 PM PDT 24
Finished Apr 23 02:40:47 PM PDT 24
Peak memory 195208 kb
Host smart-6b4b4050-4722-49d8-936d-ffd8d01b19e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676930220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1676930220
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4186572735
Short name T501
Test name
Test status
Simulation time 3405788318 ps
CPU time 21.98 seconds
Started Apr 23 02:40:41 PM PDT 24
Finished Apr 23 02:41:03 PM PDT 24
Peak memory 207940 kb
Host smart-fcf815ac-373d-4e4c-bd20-e2c8160b2455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186572735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4186572735
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.298843238
Short name T84
Test name
Test status
Simulation time 2428326536 ps
CPU time 23.39 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:41:17 PM PDT 24
Peak memory 199744 kb
Host smart-035892c8-b140-4857-a936-71bde4e20118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298843238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.298843238
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2335623983
Short name T447
Test name
Test status
Simulation time 342689009 ps
CPU time 18.09 seconds
Started Apr 23 02:40:46 PM PDT 24
Finished Apr 23 02:41:04 PM PDT 24
Peak memory 199644 kb
Host smart-b0469f55-2772-4bb4-bf3e-5c50b4b48933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335623983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2335623983
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2948669809
Short name T295
Test name
Test status
Simulation time 11411886851 ps
CPU time 75.57 seconds
Started Apr 23 02:40:44 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 199748 kb
Host smart-7f053eeb-c111-4da6-ac9c-63378ea64d70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948669809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2948669809
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3010350590
Short name T399
Test name
Test status
Simulation time 2179459157 ps
CPU time 30.02 seconds
Started Apr 23 02:40:40 PM PDT 24
Finished Apr 23 02:41:11 PM PDT 24
Peak memory 199664 kb
Host smart-2b917d72-50f4-4e78-b147-433ebb3ec924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010350590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3010350590
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2719118683
Short name T133
Test name
Test status
Simulation time 756447724 ps
CPU time 2.5 seconds
Started Apr 23 02:40:42 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 199588 kb
Host smart-b165b594-9f0f-4c0c-8d77-844ac6217b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719118683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2719118683
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2952312839
Short name T572
Test name
Test status
Simulation time 396786912283 ps
CPU time 1807.04 seconds
Started Apr 23 02:40:44 PM PDT 24
Finished Apr 23 03:10:52 PM PDT 24
Peak memory 220240 kb
Host smart-52cfb87e-d2f5-4d62-814d-3afe24850210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952312839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2952312839
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3193916422
Short name T554
Test name
Test status
Simulation time 325143171 ps
CPU time 1.22 seconds
Started Apr 23 02:40:45 PM PDT 24
Finished Apr 23 02:40:47 PM PDT 24
Peak memory 199484 kb
Host smart-3285054a-e4dd-4170-9fa9-0c2e876ba48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193916422 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3193916422
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2051107189
Short name T192
Test name
Test status
Simulation time 108664314655 ps
CPU time 493.08 seconds
Started Apr 23 02:40:48 PM PDT 24
Finished Apr 23 02:49:01 PM PDT 24
Peak memory 199692 kb
Host smart-afcac0ad-f5b4-45c2-9682-117cc8bf41a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051107189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2051107189
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.111373787
Short name T580
Test name
Test status
Simulation time 4426745027 ps
CPU time 47.68 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:41:42 PM PDT 24
Peak memory 199764 kb
Host smart-76ac874b-ec8b-4f1b-9991-c758c938ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111373787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.111373787
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.2194864594
Short name T534
Test name
Test status
Simulation time 91100286422 ps
CPU time 2143.93 seconds
Started Apr 23 02:43:16 PM PDT 24
Finished Apr 23 03:19:01 PM PDT 24
Peak memory 248880 kb
Host smart-8f8843e6-ad54-4599-b199-c0fee48b17cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194864594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.2194864594
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.4176261913
Short name T99
Test name
Test status
Simulation time 70682108328 ps
CPU time 830.32 seconds
Started Apr 23 02:43:17 PM PDT 24
Finished Apr 23 02:57:07 PM PDT 24
Peak memory 248736 kb
Host smart-bd1dc3a0-cc6d-4df1-ab51-b3b2739f34b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176261913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.4176261913
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.626796627
Short name T385
Test name
Test status
Simulation time 35081012 ps
CPU time 0.58 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 194164 kb
Host smart-207b406c-ba22-4cc8-aa1f-591bb1c20631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626796627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.626796627
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2654864257
Short name T219
Test name
Test status
Simulation time 1388274836 ps
CPU time 57.4 seconds
Started Apr 23 02:40:45 PM PDT 24
Finished Apr 23 02:41:44 PM PDT 24
Peak memory 232352 kb
Host smart-eb225b4a-4019-4cd2-a307-44fb84a4d2c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654864257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2654864257
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.32998755
Short name T155
Test name
Test status
Simulation time 517314276 ps
CPU time 8.11 seconds
Started Apr 23 02:40:48 PM PDT 24
Finished Apr 23 02:40:56 PM PDT 24
Peak memory 199580 kb
Host smart-ce3e98f2-cbcd-42ff-aa4f-fe86811387ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32998755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.32998755
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.62481873
Short name T388
Test name
Test status
Simulation time 3478261127 ps
CPU time 88.99 seconds
Started Apr 23 02:40:48 PM PDT 24
Finished Apr 23 02:42:17 PM PDT 24
Peak memory 199744 kb
Host smart-7d456748-869a-43ef-9bea-5e693f717c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62481873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.62481873
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.74800756
Short name T32
Test name
Test status
Simulation time 8530005920 ps
CPU time 126.76 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:43:01 PM PDT 24
Peak memory 199720 kb
Host smart-66ab2a29-6c84-4d4a-b0dc-4e124a94c156
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74800756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.74800756
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4282057998
Short name T304
Test name
Test status
Simulation time 730567160 ps
CPU time 38.11 seconds
Started Apr 23 02:40:45 PM PDT 24
Finished Apr 23 02:41:24 PM PDT 24
Peak memory 199588 kb
Host smart-eb35dcf1-291a-4014-b915-15b0f955f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282057998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4282057998
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.952092383
Short name T25
Test name
Test status
Simulation time 1024168541 ps
CPU time 4.4 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:40:59 PM PDT 24
Peak memory 199620 kb
Host smart-be666301-1bf3-43fd-9c3c-502f9e3a0e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952092383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.952092383
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.421635300
Short name T222
Test name
Test status
Simulation time 29983726659 ps
CPU time 150.21 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:43:25 PM PDT 24
Peak memory 215384 kb
Host smart-cddc44ff-3ba9-4fa2-a4a4-b7e79b903518
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421635300 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.421635300
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1764129342
Short name T460
Test name
Test status
Simulation time 65641796 ps
CPU time 1.01 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:40:54 PM PDT 24
Peak memory 199156 kb
Host smart-5bec2a3a-edd6-47ad-ab48-c6942f9db8d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764129342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1764129342
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1343008024
Short name T229
Test name
Test status
Simulation time 162732424339 ps
CPU time 410.25 seconds
Started Apr 23 02:40:52 PM PDT 24
Finished Apr 23 02:47:43 PM PDT 24
Peak memory 199724 kb
Host smart-6c0b1a3e-8b2a-45b5-807c-f416b0d70737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343008024 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1343008024
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2281669993
Short name T73
Test name
Test status
Simulation time 7868405635 ps
CPU time 36.05 seconds
Started Apr 23 02:40:46 PM PDT 24
Finished Apr 23 02:41:22 PM PDT 24
Peak memory 199692 kb
Host smart-ec6d2722-ca87-421e-b1be-353c5de1cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281669993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2281669993
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3116870200
Short name T7
Test name
Test status
Simulation time 91399520877 ps
CPU time 1256.38 seconds
Started Apr 23 02:43:21 PM PDT 24
Finished Apr 23 03:04:18 PM PDT 24
Peak memory 248880 kb
Host smart-59198e01-9e4b-4f61-b980-7c9b4f11ecac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116870200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.3116870200
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.229584122
Short name T311
Test name
Test status
Simulation time 44513763 ps
CPU time 0.57 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 195288 kb
Host smart-2f139aea-fc23-4f6a-9cd3-c1e3d4f983c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229584122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.229584122
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3556549951
Short name T482
Test name
Test status
Simulation time 503396969 ps
CPU time 9.01 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:41:04 PM PDT 24
Peak memory 207832 kb
Host smart-1e1b5c6d-c355-49c9-8ed9-fbe09fe973e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556549951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3556549951
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2935620979
Short name T307
Test name
Test status
Simulation time 425683171 ps
CPU time 23.14 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:41:18 PM PDT 24
Peak memory 199560 kb
Host smart-1ca51902-99ec-4ec0-9a70-d5990a336899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935620979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2935620979
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1846547770
Short name T505
Test name
Test status
Simulation time 21823864529 ps
CPU time 65.64 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 199712 kb
Host smart-35962f8c-b153-447d-86a6-004121ffd85f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846547770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1846547770
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1600528799
Short name T281
Test name
Test status
Simulation time 11201731334 ps
CPU time 105.45 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:42:39 PM PDT 24
Peak memory 199680 kb
Host smart-5b6138e7-a051-4c84-b096-181e3c73f064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600528799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1600528799
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4294600090
Short name T339
Test name
Test status
Simulation time 1354961731 ps
CPU time 6.28 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 199612 kb
Host smart-80474913-aa17-4325-b944-1b29f241e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294600090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4294600090
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1969363671
Short name T573
Test name
Test status
Simulation time 83241526416 ps
CPU time 734.95 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:53:08 PM PDT 24
Peak memory 248172 kb
Host smart-f9050573-47ae-44ff-adf4-d5de508b49fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969363671 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1969363671
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.151669002
Short name T285
Test name
Test status
Simulation time 35132931018 ps
CPU time 757.87 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:53:33 PM PDT 24
Peak memory 257096 kb
Host smart-a8f0fe4f-8361-46b3-882a-d7570d77ac04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151669002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.151669002
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1163680242
Short name T479
Test name
Test status
Simulation time 60681399 ps
CPU time 1.21 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 199356 kb
Host smart-1f0fda9e-fdff-42e7-9fd0-93adf0fcae80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163680242 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1163680242
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2611672432
Short name T256
Test name
Test status
Simulation time 292372209415 ps
CPU time 499.47 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:49:15 PM PDT 24
Peak memory 199720 kb
Host smart-60d909a5-0519-4b22-bbc5-ff6a1556a162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611672432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2611672432
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3194009854
Short name T302
Test name
Test status
Simulation time 17263279706 ps
CPU time 59.75 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 199732 kb
Host smart-bff13aaf-3d41-42b6-9464-c09fb0674b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194009854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3194009854
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2412324477
Short name T250
Test name
Test status
Simulation time 13243259 ps
CPU time 0.57 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:40:57 PM PDT 24
Peak memory 194160 kb
Host smart-7a632de2-84f9-406c-9ecd-303e93e70d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412324477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2412324477
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2955221876
Short name T516
Test name
Test status
Simulation time 305588534 ps
CPU time 11.55 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 223888 kb
Host smart-88789d79-5a85-40c4-9589-58ea7002fe2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955221876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2955221876
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2745679235
Short name T98
Test name
Test status
Simulation time 505854647 ps
CPU time 6.43 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:41:01 PM PDT 24
Peak memory 199556 kb
Host smart-ab587aed-3935-416f-b416-63183d327e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745679235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2745679235
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3117675091
Short name T123
Test name
Test status
Simulation time 2209428243 ps
CPU time 124.46 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:42:58 PM PDT 24
Peak memory 199652 kb
Host smart-c7c6d255-2f46-43f5-9c91-5974253d16d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117675091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3117675091
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3539927095
Short name T176
Test name
Test status
Simulation time 1338818630 ps
CPU time 73.18 seconds
Started Apr 23 02:40:55 PM PDT 24
Finished Apr 23 02:42:08 PM PDT 24
Peak memory 199592 kb
Host smart-ba52723d-8c6a-400a-b8fc-1c7d5b66d6db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539927095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3539927095
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1865685188
Short name T389
Test name
Test status
Simulation time 244487329 ps
CPU time 2.72 seconds
Started Apr 23 02:40:52 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 199620 kb
Host smart-6916c26b-b86a-4e57-a705-57479ff662ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865685188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1865685188
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4243996924
Short name T464
Test name
Test status
Simulation time 745711287 ps
CPU time 5.06 seconds
Started Apr 23 02:40:53 PM PDT 24
Finished Apr 23 02:40:59 PM PDT 24
Peak memory 199592 kb
Host smart-4ff63eaa-d2d2-409b-b807-275d8dc46cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243996924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4243996924
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1605536151
Short name T497
Test name
Test status
Simulation time 134900264594 ps
CPU time 1795.73 seconds
Started Apr 23 02:40:57 PM PDT 24
Finished Apr 23 03:10:53 PM PDT 24
Peak memory 240696 kb
Host smart-8a78784f-aa01-4688-83c0-c9bd5f0aab63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605536151 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1605536151
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.643379501
Short name T441
Test name
Test status
Simulation time 351562286 ps
CPU time 1.25 seconds
Started Apr 23 02:40:57 PM PDT 24
Finished Apr 23 02:40:59 PM PDT 24
Peak memory 198452 kb
Host smart-f7c9cec9-a10b-4990-9297-14952ac42ad7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643379501 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.643379501
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.330162347
Short name T181
Test name
Test status
Simulation time 72348439026 ps
CPU time 462.08 seconds
Started Apr 23 02:40:56 PM PDT 24
Finished Apr 23 02:48:38 PM PDT 24
Peak memory 199664 kb
Host smart-aa449b3c-abcd-4b72-bd4e-f5a47521a96f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330162347 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.330162347
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.670021348
Short name T159
Test name
Test status
Simulation time 5037260859 ps
CPU time 68.59 seconds
Started Apr 23 02:40:54 PM PDT 24
Finished Apr 23 02:42:03 PM PDT 24
Peak memory 199752 kb
Host smart-09094574-5a36-4dd0-839c-179147d4f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670021348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.670021348
Directory /workspace/9.hmac_wipe_secret/latest
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