Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12805281	1			T2	265		T3	38		T4	8573
all_values[1]	12805281	1			T2	265		T3	38		T4	8573
all_values[2]	12805281	1			T2	265		T3	38		T4	8573

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115940

1

T6

6

T7

65

T19

2

auto[1]

38299903

1

T2

795

T3

114

T4

25719

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36268545

1

T2

756

T3

110

T4

25684

auto[1]

2147298

1

T2

39

T3

4

T4

35

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	48391	1			T7	43		T56	31		T101	49
all_values[0]	auto[0]	auto[1]	445	1			T7	8		T56	2		T101	2
all_values[0]	auto[1]	auto[0]	12713682	1			T2	226		T3	34		T4	8538
all_values[0]	auto[1]	auto[1]	42763	1			T2	39		T3	4		T4	35
all_values[1]	auto[0]	auto[0]	35249	1			T7	5		T101	51		T20	2
all_values[1]	auto[0]	auto[1]	198	1			T7	1		T14	2		T103	8
all_values[1]	auto[1]	auto[0]	12769404	1			T2	265		T3	38		T4	8573
all_values[1]	auto[1]	auto[1]	430	1			T7	30		T13	1		T14	2
all_values[2]	auto[0]	auto[0]	27264	1			T6	6		T7	7		T19	2
all_values[2]	auto[0]	auto[1]	4393	1			T7	1		T16	165		T13	3
all_values[2]	auto[1]	auto[0]	10674555	1			T2	265		T3	38		T4	8573
all_values[2]	auto[1]	auto[1]	2099069	1			T5	11952		T18	12		T7	29389