Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5981722

1

T2

968

T3

33

T4

3793

auto[1]

2388838

1

T2

903

T4

4691

T6

303

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2357472

1

T2

734

T4

4429

T6

226

auto[1]

6013088

1

T2

1137

T3

33

T4

4055

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5309704

1

T2

1104

T4

5345

T5

37301

auto[1]

3060856

1

T2

767

T3

33

T4

3139

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5421591	1			T2	1320		T3	4		T4	7658
fifo_depth[1]	419337	1			T2	77		T3	1		T4	459
fifo_depth[2]	354122	1			T2	114		T3	5		T4	239
fifo_depth[3]	289671	1			T2	50		T3	2		T4	96
fifo_depth[4]	248933	1			T2	111		T3	3		T4	26
fifo_depth[5]	221106	1			T2	29		T3	3		T4	4
fifo_depth[6]	208200	1			T2	60		T3	5		T4	1
fifo_depth[7]	183344	1			T2	24		T3	4		T4	1
fifo_depth[8]	159883	1			T2	70		T7	4634		T26	403
fifo_depth[9]	112375	1			T2	7		T3	1		T7	2962
fifo_depth[10]	80719	1			T2	8		T3	3		T7	2880
fifo_depth[11]	50010	1			T7	1950		T26	106		T44	5
fifo_depth[12]	42775	1			T2	1		T3	2		T7	2890
fifo_depth[13]	22361	1			T7	1598		T26	28		T102	85
fifo_depth[14]	24925	1			T7	2575		T26	16		T102	33
fifo_depth[15]	17566	1			T7	1752		T26	3		T102	13
fifo_depth[16]	74443	1			T7	8532		T26	1		T56	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3047386

1

T2

551

T3

29

T4

826

auto[1]

5323174

1

T2

1320

T3

4

T4

7658

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8272143

1

T2

1871

T3

33

T4

8484

auto[1]

98417

1

T7

8657

T19

7

T20

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

202287

1

T2

163

T4

261

T6

25

auto[0]

auto[0]

auto[0]

auto[1]

194506

1

T2

23

T4

92

T6

14

auto[0]

auto[0]

auto[1]

auto[0]

931499

1

T2

86

T4

31

T5

1276

auto[0]

auto[0]

auto[1]

auto[1]

196020

1

T2

58

T4

121

T6

28

auto[0]

auto[1]

auto[0]

auto[0]

386385

1

T2

2

T7

9542

T33

24

auto[0]

auto[1]

auto[0]

auto[1]

373871

1

T2

101

T4

83

T6

20

auto[0]

auto[1]

auto[1]

auto[0]

382591

1

T2

11

T3

29

T4

68

auto[0]

auto[1]

auto[1]

auto[1]

380227

1

T2

107

T4

170

T6

7

auto[1]

auto[0]

auto[0]

auto[0]

219627

1

T2

285

T4

2551

T6

80

auto[1]

auto[0]

auto[0]

auto[1]

214371

1

T2

33

T4

865

T6

37

auto[1]

auto[0]

auto[1]

auto[0]

3120339

1

T2

382

T4

324

T5

36025

auto[1]

auto[0]

auto[1]

auto[1]

231055

1

T2

74

T4

1100

T6

111

auto[1]

auto[1]

auto[0]

auto[0]

365950

1

T2

23

T7

1533

T33

194

auto[1]

auto[1]

auto[0]

auto[1]

400475

1

T2

104

T4

577

T6

50

auto[1]

auto[1]

auto[1]

auto[0]

373044

1

T2

16

T3

4

T4

558

auto[1]

auto[1]

auto[1]

auto[1]

398313

1

T2

403

T4

1683

T6

36

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

408184

1

T2

448

T4

2812

T6

105

auto[0]

auto[0]

auto[0]

auto[1]

399047

1

T2

56

T4

957

T6

51

auto[0]

auto[0]

auto[1]

auto[0]

4038378

1

T2

468

T4

355

T5

37301

auto[0]

auto[0]

auto[1]

auto[1]

414912

1

T2

132

T4

1221

T6

139

auto[0]

auto[1]

auto[0]

auto[0]

741237

1

T2

25

T7

10199

T33

218

auto[0]

auto[1]

auto[0]

auto[1]

763952

1

T2

205

T4

660

T6

70

auto[0]

auto[1]

auto[1]

auto[0]

739678

1

T2

27

T3

33

T4

626

auto[0]

auto[1]

auto[1]

auto[1]

766755

1

T2

510

T4

1853

T6

43

auto[1]

auto[0]

auto[0]

auto[0]

13730

1

T7

335

T19

1

T30

324

auto[1]

auto[0]

auto[0]

auto[1]

9830

1

T7

1381

T19

1

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

13460

1

T7

1002

T19

2

T20

3

auto[1]

auto[0]

auto[1]

auto[1]

12163

1

T7

1433

T19

1

T13

1

auto[1]

auto[1]

auto[0]

auto[0]

11098

1

T7

876

T19

2

T10

218

auto[1]

auto[1]

auto[0]

auto[1]

10394

1

T7

106

T13

2

T51

1

auto[1]

auto[1]

auto[1]

auto[0]

15957

1

T7

1871

T103

309

T10

322

auto[1]

auto[1]

auto[1]

auto[1]

11785

1

T7

1653

T20

1

T10

389

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	233357	1			T2	285		T4	2551		T6	80
fifo_depth[0]	auto[0]	auto[0]	auto[1]	224201	1			T2	33		T4	865		T6	37
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3133799	1			T2	382		T4	324		T5	36025
fifo_depth[0]	auto[0]	auto[1]	auto[1]	243218	1			T2	74		T4	1100		T6	111
fifo_depth[0]	auto[1]	auto[0]	auto[0]	377048	1			T2	23		T7	2409		T33	194
fifo_depth[0]	auto[1]	auto[0]	auto[1]	410869	1			T2	104		T4	577		T6	50
fifo_depth[0]	auto[1]	auto[1]	auto[0]	389001	1			T2	16		T3	4		T4	558
fifo_depth[0]	auto[1]	auto[1]	auto[1]	410098	1			T2	403		T4	1683		T6	36
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17651	1			T2	15		T4	145		T6	6
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18124	1			T2	2		T4	45		T6	3
fifo_depth[1]	auto[0]	auto[1]	auto[0]	195678	1			T2	25		T4	17		T5	912
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18305	1			T2	1		T4	68		T6	7
fifo_depth[1]	auto[1]	auto[0]	auto[0]	41183	1			T2	1		T7	234		T33	18
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43974	1			T2	10		T4	46		T6	4
fifo_depth[1]	auto[1]	auto[1]	auto[0]	42080	1			T3	1		T4	38		T18	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	42342	1			T2	23		T4	100		T6	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	15074	1			T2	35		T4	73		T6	7
fifo_depth[2]	auto[0]	auto[0]	auto[1]	16153	1			T2	4		T4	29		T6	2
fifo_depth[2]	auto[0]	auto[1]	auto[0]	154597	1			T2	26		T4	8		T5	270
fifo_depth[2]	auto[0]	auto[1]	auto[1]	15763	1			T2	4		T4	38		T6	7
fifo_depth[2]	auto[1]	auto[0]	auto[0]	37508	1			T2	1		T7	227		T33	6
fifo_depth[2]	auto[1]	auto[0]	auto[1]	39304	1			T2	20		T4	21		T6	4
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37898	1			T2	2		T3	5		T4	21
fifo_depth[2]	auto[1]	auto[1]	auto[1]	37825	1			T2	22		T4	49		T7	669
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12214	1			T2	19		T4	34		T6	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13211	1			T2	3		T4	12		T6	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	118309	1			T2	14		T4	5		T5	78
fifo_depth[3]	auto[0]	auto[1]	auto[1]	12378	1			T2	2		T4	9		T6	3
fifo_depth[3]	auto[1]	auto[0]	auto[0]	32874	1			T7	195		T26	76		T44	3
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34436	1			T2	1		T4	11		T6	3
fifo_depth[3]	auto[1]	auto[1]	auto[0]	32969	1			T3	2		T4	8		T6	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33280	1			T2	11		T4	17		T7	717
fifo_depth[4]	auto[0]	auto[0]	auto[0]	11493	1			T2	35		T4	8		T6	7
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12326	1			T2	4		T4	4		T6	4
fifo_depth[4]	auto[0]	auto[1]	auto[0]	86841	1			T2	8		T5	14		T6	6
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11892	1			T2	29		T4	5		T6	6
fifo_depth[4]	auto[1]	auto[0]	auto[0]	31506	1			T7	318		T26	81		T44	52
fifo_depth[4]	auto[1]	auto[0]	auto[1]	32096	1			T2	26		T4	4		T6	3
fifo_depth[4]	auto[1]	auto[1]	auto[0]	31342	1			T2	3		T3	3		T4	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	31437	1			T2	6		T4	4		T6	6
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10261	1			T2	14		T4	1		T6	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11102	1			T2	3		T4	1		T6	4
fifo_depth[5]	auto[0]	auto[1]	auto[0]	70898	1			T2	6		T4	1		T5	1
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10162	1			T2	1		T6	3		T7	254
fifo_depth[5]	auto[1]	auto[0]	auto[0]	29696	1			T7	177		T26	81		T44	4
fifo_depth[5]	auto[1]	auto[0]	auto[1]	30054	1			T2	1		T4	1		T6	2
fifo_depth[5]	auto[1]	auto[1]	auto[0]	29363	1			T3	3		T7	432		T26	74
fifo_depth[5]	auto[1]	auto[1]	auto[1]	29570	1			T2	4		T7	702		T33	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	9720	1			T2	21		T7	345		T26	39
fifo_depth[6]	auto[0]	auto[0]	auto[1]	10724	1			T2	3		T4	1		T7	367
fifo_depth[6]	auto[0]	auto[1]	auto[0]	61681	1			T2	5		T5	1		T7	2313
fifo_depth[6]	auto[0]	auto[1]	auto[1]	10166	1			T2	1		T6	2		T7	498
fifo_depth[6]	auto[1]	auto[0]	auto[0]	28907	1			T7	313		T26	74		T44	13
fifo_depth[6]	auto[1]	auto[0]	auto[1]	29323	1			T2	22		T6	3		T7	451
fifo_depth[6]	auto[1]	auto[1]	auto[0]	28538	1			T2	3		T3	5		T7	473
fifo_depth[6]	auto[1]	auto[1]	auto[1]	29141	1			T2	5		T7	696		T26	118
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9010	1			T2	12		T6	1		T7	305
fifo_depth[7]	auto[0]	auto[0]	auto[1]	9625	1			T2	3		T7	317		T26	19
fifo_depth[7]	auto[0]	auto[1]	auto[0]	49202	1			T2	1		T7	1878		T26	64
fifo_depth[7]	auto[0]	auto[1]	auto[1]	9003	1			T2	3		T4	1		T7	251
fifo_depth[7]	auto[1]	auto[0]	auto[0]	26570	1			T7	211		T26	70		T44	3
fifo_depth[7]	auto[1]	auto[0]	auto[1]	26967	1			T2	2		T6	1		T7	435
fifo_depth[7]	auto[1]	auto[1]	auto[0]	26135	1			T2	1		T3	4		T7	434
fifo_depth[7]	auto[1]	auto[1]	auto[1]	26832	1			T2	2		T7	677		T26	102
fifo_depth[8]	auto[0]	auto[0]	auto[0]	8354	1			T2	6		T7	312		T26	23
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9075	1			T2	1		T7	364		T26	12
fifo_depth[8]	auto[0]	auto[1]	auto[0]	37840	1			T2	1		T7	1347		T26	59
fifo_depth[8]	auto[0]	auto[1]	auto[1]	8952	1			T2	16		T7	534		T26	32
fifo_depth[8]	auto[1]	auto[0]	auto[0]	24656	1			T7	330		T26	68		T44	9
fifo_depth[8]	auto[1]	auto[0]	auto[1]	23403	1			T2	12		T7	375		T26	56
fifo_depth[8]	auto[1]	auto[1]	auto[0]	23953	1			T2	1		T7	607		T26	73
fifo_depth[8]	auto[1]	auto[1]	auto[1]	23650	1			T2	33		T7	765		T26	80
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5774	1			T2	2		T7	232		T26	27
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6486	1			T7	220		T26	11		T56	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	25583	1			T7	986		T26	43		T27	47
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5904	1			T7	217		T26	21		T27	19
fifo_depth[9]	auto[1]	auto[0]	auto[0]	17421	1			T7	203		T26	37		T44	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17297	1			T2	5		T7	245		T26	47
fifo_depth[9]	auto[1]	auto[1]	auto[0]	16422	1			T3	1		T7	297		T26	47
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17488	1			T7	562		T26	66		T44	5
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4446	1			T2	4		T7	169		T26	14
fifo_depth[10]	auto[0]	auto[0]	auto[1]	4868	1			T7	233		T26	9		T44	1
fifo_depth[10]	auto[0]	auto[1]	auto[0]	17637	1			T7	875		T26	20		T44	2
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5010	1			T7	463		T26	12		T56	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	12658	1			T7	315		T26	26		T44	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12152	1			T2	2		T7	214		T26	39
fifo_depth[10]	auto[1]	auto[1]	auto[0]	11786	1			T2	1		T3	3		T7	204
fifo_depth[10]	auto[1]	auto[1]	auto[1]	12162	1			T2	1		T7	407		T26	34
fifo_depth[11]	auto[0]	auto[0]	auto[0]	2803	1			T7	181		T26	3		T44	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3428	1			T7	183		T26	9		T27	9
fifo_depth[11]	auto[0]	auto[1]	auto[0]	10390	1			T7	633		T26	18		T27	19
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3282	1			T7	155		T26	5		T27	8
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7759	1			T7	182		T26	15		T102	82
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7553	1			T7	157		T26	19		T102	42
fifo_depth[11]	auto[1]	auto[1]	auto[0]	7204	1			T7	180		T26	21		T44	3
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7591	1			T7	279		T26	16		T44	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	3526	1			T7	182		T26	4		T27	17
fifo_depth[12]	auto[0]	auto[0]	auto[1]	3500	1			T7	281		T26	1		T44	2
fifo_depth[12]	auto[0]	auto[1]	auto[0]	7544	1			T7	503		T26	8		T27	12
fifo_depth[12]	auto[0]	auto[1]	auto[1]	3669	1			T2	1		T7	528		T26	3
fifo_depth[12]	auto[1]	auto[0]	auto[0]	6692	1			T7	291		T26	5		T102	42
fifo_depth[12]	auto[1]	auto[0]	auto[1]	5266	1			T7	215		T26	16		T44	1
fifo_depth[12]	auto[1]	auto[1]	auto[0]	6803	1			T3	2		T7	416		T26	11
fifo_depth[12]	auto[1]	auto[1]	auto[1]	5775	1			T7	474		T26	11		T102	27
fifo_depth[13]	auto[0]	auto[0]	auto[0]	1876	1			T7	179		T27	2		T13	26
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2032	1			T7	182		T26	1		T27	4
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4266	1			T7	434		T26	3		T27	4
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2100	1			T7	173		T26	2		T27	4
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3124	1			T7	85		T26	4		T102	23
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3232	1			T7	199		T26	6		T102	8
fifo_depth[13]	auto[1]	auto[1]	auto[0]	2625	1			T7	114		T26	5		T102	47
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3106	1			T7	232		T26	7		T102	7
fifo_depth[14]	auto[0]	auto[0]	auto[0]	2697	1			T7	289		T26	2		T27	2
fifo_depth[14]	auto[0]	auto[0]	auto[1]	2450	1			T7	310		T26	1		T13	3
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4670	1			T7	503		T26	1		T27	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	2856	1			T7	578		T27	1		T13	14
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3418	1			T7	248		T26	1		T102	9
fifo_depth[14]	auto[1]	auto[0]	auto[1]	2754	1			T7	162		T26	6		T102	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3188	1			T7	124		T26	2		T102	19
fifo_depth[14]	auto[1]	auto[1]	auto[1]	2892	1			T7	361		T26	3		T102	3
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2063	1			T7	333		T26	2		T13	5
fifo_depth[15]	auto[0]	auto[0]	auto[1]	1897	1			T7	259		T13	1		T114	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2942	1			T7	439		T26	1		T13	7
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2095	1			T7	148		T13	6		T114	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2154	1			T7	49		T102	1		T13	15
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2124	1			T7	173		T102	2		T13	7
fifo_depth[15]	auto[1]	auto[1]	auto[0]	1977	1			T7	65		T102	8		T27	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2314	1			T7	286		T102	2		T27	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	13451	1			T7	3029		T13	3		T115	1
fifo_depth[16]	auto[0]	auto[0]	auto[1]	5163	1			T7	638		T56	2		T115	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	12245	1			T7	1177		T13	4		T103	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	6671	1			T7	918		T13	1		T10	138
fifo_depth[16]	auto[1]	auto[0]	auto[0]	12952	1			T7	644		T13	5		T116	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	5844	1			T7	303		T26	1		T27	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	9824	1			T7	455		T102	4		T13	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	8293	1			T7	1368		T27	2		T13	2