Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12805281	1			T2	265		T3	38		T4	8573
all_pins[1]	12805281	1			T2	265		T3	38		T4	8573
all_pins[2]	12805281	1			T2	265		T3	38		T4	8573

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36272366	1			T2	756		T3	110		T4	25680
values[0x1]	2143477	1			T2	39		T3	4		T4	39
transitions[0x0=>0x1]	2143289	1			T2	39		T3	4		T4	39
transitions[0x1=>0x0]	2143304	1			T2	39		T3	4		T4	39

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12761324	1			T2	226		T3	34		T4	8534
all_pins[0]	values[0x1]	43957	1			T2	39		T3	4		T4	39
all_pins[0]	transitions[0x0=>0x1]	43880	1			T2	39		T3	4		T4	39
all_pins[0]	transitions[0x1=>0x0]	2099007	1			T5	11952		T18	12		T7	29389
all_pins[1]	values[0x0]	12804830	1			T2	265		T3	38		T4	8573
all_pins[1]	values[0x1]	451	1			T7	35		T13	1		T14	2
all_pins[1]	transitions[0x0=>0x1]	390	1			T7	34		T14	2		T103	1
all_pins[1]	transitions[0x1=>0x0]	43896	1			T2	39		T3	4		T4	39
all_pins[2]	values[0x0]	10706212	1			T2	265		T3	38		T4	8573
all_pins[2]	values[0x1]	2099069	1			T5	11952		T18	12		T7	29389
all_pins[2]	transitions[0x0=>0x1]	2099019	1			T5	11952		T18	12		T7	29389
all_pins[2]	transitions[0x1=>0x0]	401	1			T7	35		T13	1		T14	1