Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 888 1 T7 18 T13 7 T14 7
all_values[1] 888 1 T7 18 T13 7 T14 7
all_values[2] 888 1 T7 18 T13 7 T14 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1331 1 T7 24 T13 9 T14 12
auto[1] 1333 1 T7 30 T13 12 T14 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 886 1 T7 19 T13 8 T14 7
auto[1] 1778 1 T7 35 T13 13 T14 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1499 1 T7 32 T13 13 T14 11
auto[1] 1165 1 T7 22 T13 8 T14 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 164 1 T7 4 T13 1 T14 3
all_values[0] auto[0] auto[0] auto[1] 82 1 T7 3 T13 1 T103 2
all_values[0] auto[0] auto[1] auto[0] 159 1 T7 1 T103 3 T17 7
all_values[0] auto[0] auto[1] auto[1] 94 1 T7 1 T13 1 T14 1
all_values[0] auto[1] auto[0] auto[1] 190 1 T7 5 T13 1 T14 1
all_values[0] auto[1] auto[1] auto[1] 199 1 T7 4 T13 3 T14 2
all_values[1] auto[0] auto[0] auto[0] 144 1 T7 3 T13 2 T14 1
all_values[1] auto[0] auto[0] auto[1] 110 1 T103 5 T17 3 T10 2
all_values[1] auto[0] auto[1] auto[0] 116 1 T7 3 T13 3 T17 2
all_values[1] auto[0] auto[1] auto[1] 114 1 T7 5 T13 1 T14 2
all_values[1] auto[1] auto[0] auto[1] 210 1 T7 1 T14 2 T103 8
all_values[1] auto[1] auto[1] auto[1] 194 1 T7 6 T13 1 T14 2
all_values[2] auto[0] auto[0] auto[0] 155 1 T7 5 T13 1 T14 2
all_values[2] auto[0] auto[0] auto[1] 97 1 T13 1 T14 1 T103 2
all_values[2] auto[0] auto[1] auto[0] 148 1 T7 3 T13 1 T14 1
all_values[2] auto[0] auto[1] auto[1] 116 1 T7 4 T13 1 T103 1
all_values[2] auto[1] auto[0] auto[1] 179 1 T7 3 T13 2 T14 2
all_values[2] auto[1] auto[1] auto[1] 193 1 T7 3 T13 1 T14 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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