Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.94 92.47 85.22 100.00 76.32 85.98 99.49 69.08


Total test records in report: 732
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T537 /workspace/coverage/default/6.hmac_long_msg.1816411665 Apr 25 01:03:40 PM PDT 24 Apr 25 01:04:03 PM PDT 24 1210566116 ps
T37 /workspace/coverage/default/4.hmac_sec_cm.1781000102 Apr 25 01:03:46 PM PDT 24 Apr 25 01:03:48 PM PDT 24 193371580 ps
T538 /workspace/coverage/default/47.hmac_alert_test.3917569644 Apr 25 01:04:51 PM PDT 24 Apr 25 01:04:53 PM PDT 24 11156775 ps
T12 /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3476723929 Apr 25 01:05:41 PM PDT 24 Apr 25 01:22:36 PM PDT 24 48292211342 ps
T539 /workspace/coverage/default/11.hmac_datapath_stress.252584986 Apr 25 01:04:04 PM PDT 24 Apr 25 01:05:36 PM PDT 24 6281248400 ps
T540 /workspace/coverage/default/4.hmac_smoke.1098397310 Apr 25 01:03:36 PM PDT 24 Apr 25 01:03:44 PM PDT 24 2660097855 ps
T541 /workspace/coverage/default/24.hmac_back_pressure.707555569 Apr 25 01:04:11 PM PDT 24 Apr 25 01:04:16 PM PDT 24 74427205 ps
T542 /workspace/coverage/default/15.hmac_back_pressure.2930633921 Apr 25 01:04:16 PM PDT 24 Apr 25 01:05:15 PM PDT 24 1483507779 ps
T543 /workspace/coverage/default/32.hmac_test_hmac_vectors.1585178460 Apr 25 01:04:29 PM PDT 24 Apr 25 01:04:31 PM PDT 24 110472097 ps
T544 /workspace/coverage/default/10.hmac_long_msg.1920783264 Apr 25 01:03:55 PM PDT 24 Apr 25 01:05:00 PM PDT 24 16176991108 ps
T545 /workspace/coverage/default/28.hmac_back_pressure.1433004241 Apr 25 01:04:22 PM PDT 24 Apr 25 01:04:29 PM PDT 24 580806257 ps
T546 /workspace/coverage/default/26.hmac_back_pressure.982560177 Apr 25 01:04:30 PM PDT 24 Apr 25 01:04:39 PM PDT 24 901684599 ps
T547 /workspace/coverage/default/43.hmac_datapath_stress.2687013969 Apr 25 01:04:50 PM PDT 24 Apr 25 01:06:15 PM PDT 24 1366082186 ps
T548 /workspace/coverage/default/16.hmac_datapath_stress.3867033379 Apr 25 01:03:55 PM PDT 24 Apr 25 01:04:31 PM PDT 24 589652022 ps
T549 /workspace/coverage/default/24.hmac_burst_wr.1537760573 Apr 25 01:04:11 PM PDT 24 Apr 25 01:04:33 PM PDT 24 794095790 ps
T550 /workspace/coverage/default/7.hmac_test_hmac_vectors.4049189477 Apr 25 01:03:41 PM PDT 24 Apr 25 01:03:44 PM PDT 24 1090284701 ps
T47 /workspace/coverage/default/10.hmac_stress_all.1508049792 Apr 25 01:04:10 PM PDT 24 Apr 25 01:11:06 PM PDT 24 79214070660 ps
T551 /workspace/coverage/default/2.hmac_stress_all.133285049 Apr 25 01:03:27 PM PDT 24 Apr 25 01:07:56 PM PDT 24 24292446878 ps
T552 /workspace/coverage/default/6.hmac_smoke.1105406290 Apr 25 01:03:32 PM PDT 24 Apr 25 01:03:34 PM PDT 24 50313093 ps
T553 /workspace/coverage/default/20.hmac_back_pressure.2498164643 Apr 25 01:04:01 PM PDT 24 Apr 25 01:04:18 PM PDT 24 586101776 ps
T554 /workspace/coverage/default/39.hmac_burst_wr.1633137541 Apr 25 01:04:45 PM PDT 24 Apr 25 01:05:37 PM PDT 24 6544566389 ps
T555 /workspace/coverage/default/46.hmac_error.1089276807 Apr 25 01:05:05 PM PDT 24 Apr 25 01:08:15 PM PDT 24 25902901778 ps
T556 /workspace/coverage/default/25.hmac_alert_test.1072198537 Apr 25 01:04:14 PM PDT 24 Apr 25 01:04:16 PM PDT 24 31126604 ps
T557 /workspace/coverage/default/25.hmac_test_hmac_vectors.3610967888 Apr 25 01:04:15 PM PDT 24 Apr 25 01:04:18 PM PDT 24 515055101 ps
T558 /workspace/coverage/default/20.hmac_stress_all.1300029110 Apr 25 01:04:03 PM PDT 24 Apr 25 01:05:16 PM PDT 24 3640123971 ps
T559 /workspace/coverage/default/30.hmac_wipe_secret.2112580638 Apr 25 01:04:28 PM PDT 24 Apr 25 01:04:51 PM PDT 24 600841193 ps
T560 /workspace/coverage/default/0.hmac_test_sha_vectors.675036046 Apr 25 01:03:18 PM PDT 24 Apr 25 01:09:05 PM PDT 24 48061032168 ps
T561 /workspace/coverage/default/27.hmac_error.3886146761 Apr 25 01:04:13 PM PDT 24 Apr 25 01:07:51 PM PDT 24 49849362288 ps
T562 /workspace/coverage/default/19.hmac_smoke.462840430 Apr 25 01:04:12 PM PDT 24 Apr 25 01:04:20 PM PDT 24 689639722 ps
T563 /workspace/coverage/default/46.hmac_back_pressure.2748089677 Apr 25 01:04:56 PM PDT 24 Apr 25 01:05:03 PM PDT 24 277293768 ps
T564 /workspace/coverage/default/10.hmac_test_hmac_vectors.3412907923 Apr 25 01:03:47 PM PDT 24 Apr 25 01:03:49 PM PDT 24 138674432 ps
T565 /workspace/coverage/default/29.hmac_test_hmac_vectors.3267478255 Apr 25 01:04:22 PM PDT 24 Apr 25 01:04:23 PM PDT 24 83142310 ps
T566 /workspace/coverage/default/40.hmac_long_msg.1190634742 Apr 25 01:04:37 PM PDT 24 Apr 25 01:04:57 PM PDT 24 322986332 ps
T567 /workspace/coverage/default/0.hmac_long_msg.4118646424 Apr 25 01:03:32 PM PDT 24 Apr 25 01:04:08 PM PDT 24 10104389027 ps
T568 /workspace/coverage/default/40.hmac_back_pressure.1574110032 Apr 25 01:04:57 PM PDT 24 Apr 25 01:05:23 PM PDT 24 651057783 ps
T569 /workspace/coverage/default/12.hmac_back_pressure.2319380440 Apr 25 01:03:47 PM PDT 24 Apr 25 01:04:24 PM PDT 24 2007619321 ps
T570 /workspace/coverage/default/28.hmac_error.905147142 Apr 25 01:04:32 PM PDT 24 Apr 25 01:07:39 PM PDT 24 16421622564 ps
T571 /workspace/coverage/default/35.hmac_long_msg.2998325924 Apr 25 01:04:45 PM PDT 24 Apr 25 01:07:14 PM PDT 24 10365319573 ps
T572 /workspace/coverage/default/39.hmac_alert_test.310257396 Apr 25 01:04:59 PM PDT 24 Apr 25 01:05:01 PM PDT 24 42206837 ps
T573 /workspace/coverage/default/47.hmac_back_pressure.4045268926 Apr 25 01:05:03 PM PDT 24 Apr 25 01:05:35 PM PDT 24 816493754 ps
T574 /workspace/coverage/default/8.hmac_burst_wr.879366346 Apr 25 01:03:56 PM PDT 24 Apr 25 01:04:25 PM PDT 24 7875034262 ps
T575 /workspace/coverage/default/49.hmac_error.1131752783 Apr 25 01:05:24 PM PDT 24 Apr 25 01:05:32 PM PDT 24 597491887 ps
T576 /workspace/coverage/default/29.hmac_smoke.1156445742 Apr 25 01:04:31 PM PDT 24 Apr 25 01:04:39 PM PDT 24 2432044160 ps
T577 /workspace/coverage/default/29.hmac_datapath_stress.1290116517 Apr 25 01:04:16 PM PDT 24 Apr 25 01:04:28 PM PDT 24 314557745 ps
T578 /workspace/coverage/default/48.hmac_test_hmac_vectors.1930772628 Apr 25 01:04:58 PM PDT 24 Apr 25 01:05:01 PM PDT 24 73279733 ps
T579 /workspace/coverage/default/19.hmac_alert_test.79211527 Apr 25 01:04:05 PM PDT 24 Apr 25 01:04:06 PM PDT 24 23706931 ps
T580 /workspace/coverage/default/33.hmac_alert_test.1522945279 Apr 25 01:04:42 PM PDT 24 Apr 25 01:04:44 PM PDT 24 15258273 ps
T581 /workspace/coverage/default/24.hmac_error.2781919573 Apr 25 01:04:35 PM PDT 24 Apr 25 01:06:00 PM PDT 24 27692359622 ps
T582 /workspace/coverage/default/19.hmac_burst_wr.2642792117 Apr 25 01:04:13 PM PDT 24 Apr 25 01:04:59 PM PDT 24 4258790928 ps
T583 /workspace/coverage/default/16.hmac_smoke.935884513 Apr 25 01:04:09 PM PDT 24 Apr 25 01:04:14 PM PDT 24 291280586 ps
T584 /workspace/coverage/default/33.hmac_error.1570874020 Apr 25 01:04:33 PM PDT 24 Apr 25 01:05:29 PM PDT 24 1051169595 ps
T585 /workspace/coverage/default/46.hmac_wipe_secret.898609026 Apr 25 01:05:13 PM PDT 24 Apr 25 01:05:30 PM PDT 24 344386932 ps
T586 /workspace/coverage/default/10.hmac_alert_test.2442136806 Apr 25 01:04:08 PM PDT 24 Apr 25 01:04:09 PM PDT 24 27912214 ps
T587 /workspace/coverage/default/7.hmac_back_pressure.1154886802 Apr 25 01:03:57 PM PDT 24 Apr 25 01:04:33 PM PDT 24 755203463 ps
T588 /workspace/coverage/default/20.hmac_error.3908941913 Apr 25 01:04:06 PM PDT 24 Apr 25 01:04:45 PM PDT 24 1308800459 ps
T589 /workspace/coverage/default/21.hmac_burst_wr.1282685377 Apr 25 01:04:13 PM PDT 24 Apr 25 01:04:20 PM PDT 24 1550193109 ps
T590 /workspace/coverage/default/21.hmac_test_sha_vectors.3703229426 Apr 25 01:04:04 PM PDT 24 Apr 25 01:12:39 PM PDT 24 80079478823 ps
T591 /workspace/coverage/default/44.hmac_wipe_secret.441077361 Apr 25 01:04:58 PM PDT 24 Apr 25 01:05:02 PM PDT 24 169860946 ps
T592 /workspace/coverage/default/12.hmac_error.3887145719 Apr 25 01:03:53 PM PDT 24 Apr 25 01:05:43 PM PDT 24 1932755159 ps
T593 /workspace/coverage/default/19.hmac_wipe_secret.2592607304 Apr 25 01:04:01 PM PDT 24 Apr 25 01:05:18 PM PDT 24 5685776049 ps
T594 /workspace/coverage/default/6.hmac_test_hmac_vectors.909464351 Apr 25 01:03:42 PM PDT 24 Apr 25 01:03:44 PM PDT 24 169617174 ps
T595 /workspace/coverage/default/43.hmac_stress_all.143378089 Apr 25 01:04:50 PM PDT 24 Apr 25 01:05:39 PM PDT 24 2668594391 ps
T596 /workspace/coverage/default/45.hmac_long_msg.1161270323 Apr 25 01:04:59 PM PDT 24 Apr 25 01:05:49 PM PDT 24 1644814855 ps
T597 /workspace/coverage/default/47.hmac_long_msg.349747090 Apr 25 01:05:02 PM PDT 24 Apr 25 01:05:31 PM PDT 24 2797035966 ps
T38 /workspace/coverage/default/3.hmac_sec_cm.2978346241 Apr 25 01:03:40 PM PDT 24 Apr 25 01:03:41 PM PDT 24 36845358 ps
T598 /workspace/coverage/default/17.hmac_error.1720000144 Apr 25 01:04:10 PM PDT 24 Apr 25 01:06:38 PM PDT 24 9972809518 ps
T599 /workspace/coverage/default/38.hmac_smoke.2013189746 Apr 25 01:04:39 PM PDT 24 Apr 25 01:04:43 PM PDT 24 1061308634 ps
T58 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2781451912 Apr 25 03:54:17 PM PDT 24 Apr 25 03:54:21 PM PDT 24 627866782 ps
T61 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1343837097 Apr 25 03:53:15 PM PDT 24 Apr 25 03:53:17 PM PDT 24 39941022 ps
T59 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.665222193 Apr 25 03:54:27 PM PDT 24 Apr 25 03:54:31 PM PDT 24 810603818 ps
T600 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.464800751 Apr 25 03:53:25 PM PDT 24 Apr 25 03:53:28 PM PDT 24 176326751 ps
T62 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2909553320 Apr 25 03:54:50 PM PDT 24 Apr 25 03:54:51 PM PDT 24 30371842 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1281350154 Apr 25 03:54:09 PM PDT 24 Apr 25 03:54:10 PM PDT 24 26855099 ps
T602 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1289810568 Apr 25 03:54:42 PM PDT 24 Apr 25 03:54:46 PM PDT 24 182697668 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1433025640 Apr 25 03:54:32 PM PDT 24 Apr 25 03:54:36 PM PDT 24 125549492 ps
T604 /workspace/coverage/cover_reg_top/6.hmac_intr_test.855789058 Apr 25 03:53:42 PM PDT 24 Apr 25 03:53:44 PM PDT 24 41896120 ps
T85 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3914121878 Apr 25 03:52:38 PM PDT 24 Apr 25 03:52:40 PM PDT 24 41878892 ps
T60 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1133334899 Apr 25 03:53:36 PM PDT 24 Apr 25 03:53:40 PM PDT 24 181706502 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2548244955 Apr 25 03:53:40 PM PDT 24 Apr 25 03:53:43 PM PDT 24 87794628 ps
T606 /workspace/coverage/cover_reg_top/27.hmac_intr_test.122301245 Apr 25 03:54:58 PM PDT 24 Apr 25 03:55:00 PM PDT 24 13770131 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1311352086 Apr 25 03:54:05 PM PDT 24 Apr 25 03:54:07 PM PDT 24 51629041 ps
T607 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1418938885 Apr 25 03:54:53 PM PDT 24 Apr 25 03:54:55 PM PDT 24 19744710 ps
T608 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1842919596 Apr 25 03:54:25 PM PDT 24 Apr 25 03:54:26 PM PDT 24 36126523 ps
T86 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2963200460 Apr 25 03:54:24 PM PDT 24 Apr 25 03:54:26 PM PDT 24 14135758 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3700580432 Apr 25 03:53:02 PM PDT 24 Apr 25 03:53:05 PM PDT 24 101146921 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3246293315 Apr 25 03:53:57 PM PDT 24 Apr 25 03:53:59 PM PDT 24 21050277 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.99684908 Apr 25 03:54:16 PM PDT 24 Apr 25 03:54:20 PM PDT 24 166421553 ps
T611 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3024116465 Apr 25 03:55:05 PM PDT 24 Apr 25 03:55:07 PM PDT 24 17329125 ps
T612 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2400925255 Apr 25 03:54:28 PM PDT 24 Apr 25 03:54:30 PM PDT 24 22464713 ps
T613 /workspace/coverage/cover_reg_top/2.hmac_intr_test.999370952 Apr 25 03:53:14 PM PDT 24 Apr 25 03:53:16 PM PDT 24 20205084 ps
T614 /workspace/coverage/cover_reg_top/45.hmac_intr_test.301422237 Apr 25 03:55:05 PM PDT 24 Apr 25 03:55:06 PM PDT 24 17775047 ps
T615 /workspace/coverage/cover_reg_top/40.hmac_intr_test.399142409 Apr 25 03:55:35 PM PDT 24 Apr 25 03:55:36 PM PDT 24 39438003 ps
T616 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2658377044 Apr 25 03:53:02 PM PDT 24 Apr 25 03:55:13 PM PDT 24 76597379102 ps
T617 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4276139364 Apr 25 03:54:50 PM PDT 24 Apr 25 03:54:51 PM PDT 24 14295970 ps
T618 /workspace/coverage/cover_reg_top/43.hmac_intr_test.285169392 Apr 25 03:55:05 PM PDT 24 Apr 25 03:55:06 PM PDT 24 48420388 ps
T619 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2111490065 Apr 25 03:52:37 PM PDT 24 Apr 25 03:52:38 PM PDT 24 23002587 ps
T620 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.498592219 Apr 25 03:54:02 PM PDT 24 Apr 25 03:54:05 PM PDT 24 145199684 ps
T621 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3537595164 Apr 25 03:53:34 PM PDT 24 Apr 25 03:53:35 PM PDT 24 24562622 ps
T622 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2161955399 Apr 25 03:54:14 PM PDT 24 Apr 25 03:54:17 PM PDT 24 71539809 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1233521027 Apr 25 03:54:41 PM PDT 24 Apr 25 03:54:44 PM PDT 24 430792305 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3221053599 Apr 25 03:54:13 PM PDT 24 Apr 25 03:54:15 PM PDT 24 99946999 ps
T625 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.671909625 Apr 25 03:54:48 PM PDT 24 Apr 25 03:54:52 PM PDT 24 44201284 ps
T626 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3219017360 Apr 25 03:54:14 PM PDT 24 Apr 25 03:54:16 PM PDT 24 29321435 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1419610283 Apr 25 03:53:51 PM PDT 24 Apr 25 03:53:52 PM PDT 24 46774471 ps
T628 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3953277325 Apr 25 03:53:36 PM PDT 24 Apr 25 03:53:38 PM PDT 24 38294700 ps
T629 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3423158665 Apr 25 03:55:13 PM PDT 24 Apr 25 03:55:15 PM PDT 24 35269442 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3358003326 Apr 25 03:54:27 PM PDT 24 Apr 25 03:54:29 PM PDT 24 33587536 ps
T631 /workspace/coverage/cover_reg_top/36.hmac_intr_test.127798219 Apr 25 03:55:07 PM PDT 24 Apr 25 03:55:08 PM PDT 24 20977251 ps
T632 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2702182740 Apr 25 03:53:11 PM PDT 24 Apr 25 03:53:19 PM PDT 24 301853571 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1880221785 Apr 25 03:52:53 PM PDT 24 Apr 25 03:52:54 PM PDT 24 18075598 ps
T634 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3181597600 Apr 25 03:52:58 PM PDT 24 Apr 25 03:53:00 PM PDT 24 21232529 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3366604138 Apr 25 03:53:23 PM PDT 24 Apr 25 03:53:28 PM PDT 24 445288574 ps
T635 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2760946862 Apr 25 03:53:36 PM PDT 24 Apr 25 03:53:37 PM PDT 24 25935490 ps
T636 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1927656785 Apr 25 03:53:51 PM PDT 24 Apr 25 03:53:52 PM PDT 24 15751620 ps
T637 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1653783760 Apr 25 03:53:53 PM PDT 24 Apr 25 03:53:55 PM PDT 24 97197548 ps
T638 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3712987999 Apr 25 03:54:46 PM PDT 24 Apr 25 03:54:48 PM PDT 24 37401660 ps
T639 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3318248212 Apr 25 03:54:28 PM PDT 24 Apr 25 03:54:31 PM PDT 24 44990287 ps
T110 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2665006378 Apr 25 03:53:59 PM PDT 24 Apr 25 03:54:02 PM PDT 24 362683586 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2288474066 Apr 25 03:54:41 PM PDT 24 Apr 25 03:54:43 PM PDT 24 19703259 ps
T106 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1714598046 Apr 25 03:52:55 PM PDT 24 Apr 25 03:52:58 PM PDT 24 319841195 ps
T641 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2067900498 Apr 25 03:54:20 PM PDT 24 Apr 25 03:54:21 PM PDT 24 36529524 ps
T642 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.677516477 Apr 25 03:53:30 PM PDT 24 Apr 25 03:53:32 PM PDT 24 42523839 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.381884877 Apr 25 03:53:37 PM PDT 24 Apr 25 03:53:41 PM PDT 24 679450107 ps
T644 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1825722917 Apr 25 03:54:39 PM PDT 24 Apr 25 03:54:42 PM PDT 24 227600420 ps
T87 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.284821711 Apr 25 03:53:29 PM PDT 24 Apr 25 03:53:30 PM PDT 24 19900803 ps
T645 /workspace/coverage/cover_reg_top/30.hmac_intr_test.54431864 Apr 25 03:54:56 PM PDT 24 Apr 25 03:54:57 PM PDT 24 42650590 ps
T646 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.697299793 Apr 25 03:53:54 PM PDT 24 Apr 25 03:53:58 PM PDT 24 80632508 ps
T647 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1233745048 Apr 25 03:53:54 PM PDT 24 Apr 25 03:53:57 PM PDT 24 375407742 ps
T648 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4005231342 Apr 25 03:55:04 PM PDT 24 Apr 25 03:55:05 PM PDT 24 91405383 ps
T88 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1907986943 Apr 25 03:53:25 PM PDT 24 Apr 25 03:53:35 PM PDT 24 1716723559 ps
T649 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1518290552 Apr 25 03:54:39 PM PDT 24 Apr 25 03:54:42 PM PDT 24 164976200 ps
T89 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1607409579 Apr 25 03:53:46 PM PDT 24 Apr 25 03:53:48 PM PDT 24 23466468 ps
T650 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3041087499 Apr 25 03:54:45 PM PDT 24 Apr 25 03:54:49 PM PDT 24 245894971 ps
T651 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3805190599 Apr 25 03:54:54 PM PDT 24 Apr 25 03:54:55 PM PDT 24 34588888 ps
T652 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1166153772 Apr 25 03:54:44 PM PDT 24 Apr 25 03:54:48 PM PDT 24 69731276 ps
T653 /workspace/coverage/cover_reg_top/48.hmac_intr_test.974857604 Apr 25 03:55:05 PM PDT 24 Apr 25 03:55:07 PM PDT 24 41632386 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.633831917 Apr 25 03:52:52 PM PDT 24 Apr 25 03:52:59 PM PDT 24 1361500307 ps
T654 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2015667847 Apr 25 03:54:15 PM PDT 24 Apr 25 03:54:17 PM PDT 24 33961852 ps
T655 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4203671125 Apr 25 03:54:54 PM PDT 24 Apr 25 03:54:55 PM PDT 24 15109271 ps
T656 /workspace/coverage/cover_reg_top/38.hmac_intr_test.366676706 Apr 25 03:55:13 PM PDT 24 Apr 25 03:55:15 PM PDT 24 32370814 ps
T657 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.11471138 Apr 25 03:54:45 PM PDT 24 Apr 25 03:54:47 PM PDT 24 57968659 ps
T658 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1428947733 Apr 25 03:54:36 PM PDT 24 Apr 25 03:54:40 PM PDT 24 592595894 ps
T659 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3348299625 Apr 25 03:54:54 PM PDT 24 Apr 25 03:54:55 PM PDT 24 54215684 ps
T107 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3761703121 Apr 25 03:54:27 PM PDT 24 Apr 25 03:54:32 PM PDT 24 230422782 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4036053398 Apr 25 03:53:14 PM PDT 24 Apr 25 03:53:18 PM PDT 24 576050788 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3940537431 Apr 25 03:54:29 PM PDT 24 Apr 25 03:54:32 PM PDT 24 117431997 ps
T661 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.93016138 Apr 25 03:54:25 PM PDT 24 Apr 25 03:54:27 PM PDT 24 47127180 ps
T63 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3772046231 Apr 25 03:54:33 PM PDT 24 Apr 25 03:54:37 PM PDT 24 247646933 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1058477217 Apr 25 03:52:52 PM PDT 24 Apr 25 03:53:10 PM PDT 24 1099626610 ps
T662 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2282271336 Apr 25 03:54:58 PM PDT 24 Apr 25 03:55:00 PM PDT 24 14958590 ps
T663 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2599753600 Apr 25 03:54:14 PM PDT 24 Apr 25 03:58:32 PM PDT 24 107895237050 ps
T664 /workspace/coverage/cover_reg_top/44.hmac_intr_test.4136791346 Apr 25 03:55:06 PM PDT 24 Apr 25 03:55:07 PM PDT 24 18984481 ps
T665 /workspace/coverage/cover_reg_top/32.hmac_intr_test.678725269 Apr 25 03:55:01 PM PDT 24 Apr 25 03:55:02 PM PDT 24 13499868 ps
T666 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.177407192 Apr 25 03:52:56 PM PDT 24 Apr 25 03:52:58 PM PDT 24 37936053 ps
T667 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3224024742 Apr 25 03:53:52 PM PDT 24 Apr 25 03:53:54 PM PDT 24 33078786 ps
T668 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1181246059 Apr 25 03:54:28 PM PDT 24 Apr 25 03:54:29 PM PDT 24 67846542 ps
T669 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2253601524 Apr 25 03:54:50 PM PDT 24 Apr 25 03:54:51 PM PDT 24 18063576 ps
T670 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3594045069 Apr 25 03:53:37 PM PDT 24 Apr 25 03:53:38 PM PDT 24 11236216 ps
T671 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1391384294 Apr 25 03:55:02 PM PDT 24 Apr 25 03:55:03 PM PDT 24 20264937 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2678488978 Apr 25 03:52:56 PM PDT 24 Apr 25 03:52:59 PM PDT 24 118965023 ps
T113 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.471957991 Apr 25 03:53:47 PM PDT 24 Apr 25 03:53:53 PM PDT 24 1274047719 ps
T111 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.58425342 Apr 25 03:54:31 PM PDT 24 Apr 25 03:54:36 PM PDT 24 133987942 ps
T673 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2513734485 Apr 25 03:54:16 PM PDT 24 Apr 25 03:54:21 PM PDT 24 599380649 ps
T674 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2416282985 Apr 25 03:53:15 PM PDT 24 Apr 25 03:53:18 PM PDT 24 41453797 ps
T91 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1423284297 Apr 25 03:53:51 PM PDT 24 Apr 25 03:53:52 PM PDT 24 54992829 ps
T92 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3432375394 Apr 25 03:53:55 PM PDT 24 Apr 25 03:53:57 PM PDT 24 18359902 ps
T675 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2246988885 Apr 25 03:54:24 PM PDT 24 Apr 25 03:54:27 PM PDT 24 47442492 ps
T676 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.512104081 Apr 25 03:53:44 PM PDT 24 Apr 25 03:53:46 PM PDT 24 422741584 ps
T677 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1193437922 Apr 25 03:54:49 PM PDT 24 Apr 25 03:54:52 PM PDT 24 86168261 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3475148096 Apr 25 03:53:24 PM PDT 24 Apr 25 03:53:33 PM PDT 24 306664580 ps
T679 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.96420962 Apr 25 03:52:59 PM PDT 24 Apr 25 03:53:03 PM PDT 24 249342575 ps
T680 /workspace/coverage/cover_reg_top/25.hmac_intr_test.290905415 Apr 25 03:54:55 PM PDT 24 Apr 25 03:54:56 PM PDT 24 13155192 ps
T681 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1120344773 Apr 25 03:54:58 PM PDT 24 Apr 25 03:54:59 PM PDT 24 16498850 ps
T682 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1363989376 Apr 25 03:54:49 PM PDT 24 Apr 25 03:54:51 PM PDT 24 15614615 ps
T683 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.339105684 Apr 25 03:53:21 PM PDT 24 Apr 25 03:53:25 PM PDT 24 251143797 ps
T684 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.392133591 Apr 25 03:54:16 PM PDT 24 Apr 25 03:54:20 PM PDT 24 159149827 ps
T685 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3169999706 Apr 25 03:52:51 PM PDT 24 Apr 25 03:52:55 PM PDT 24 494896277 ps
T686 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3420955155 Apr 25 03:54:47 PM PDT 24 Apr 25 03:54:48 PM PDT 24 17570628 ps
T687 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2820208670 Apr 25 03:55:04 PM PDT 24 Apr 25 03:55:05 PM PDT 24 77311392 ps
T688 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1125411478 Apr 25 03:55:03 PM PDT 24 Apr 25 03:55:04 PM PDT 24 48492241 ps
T689 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.790224911 Apr 25 03:53:42 PM PDT 24 Apr 25 03:53:45 PM PDT 24 124462901 ps
T690 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2555135862 Apr 25 03:53:23 PM PDT 24 Apr 25 03:53:25 PM PDT 24 52090853 ps
T691 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3347554906 Apr 25 03:55:06 PM PDT 24 Apr 25 03:55:07 PM PDT 24 33200970 ps
T692 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.873175825 Apr 25 03:53:45 PM PDT 24 Apr 25 03:53:47 PM PDT 24 78810592 ps
T693 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.345223242 Apr 25 03:54:13 PM PDT 24 Apr 25 03:54:16 PM PDT 24 88589385 ps
T694 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2383406757 Apr 25 03:54:06 PM PDT 24 Apr 25 03:54:07 PM PDT 24 60750814 ps
T695 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.889003007 Apr 25 03:54:13 PM PDT 24 Apr 25 03:54:18 PM PDT 24 496289362 ps
T696 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3356553461 Apr 25 03:53:12 PM PDT 24 Apr 25 03:53:29 PM PDT 24 6131164625 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3494939924 Apr 25 03:53:30 PM PDT 24 Apr 25 03:53:42 PM PDT 24 2260604445 ps
T697 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2048784251 Apr 25 03:54:13 PM PDT 24 Apr 25 04:07:47 PM PDT 24 80571940997 ps
T698 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4156743557 Apr 25 03:54:54 PM PDT 24 Apr 25 03:54:55 PM PDT 24 20990695 ps
T699 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3362806339 Apr 25 03:53:18 PM PDT 24 Apr 25 03:53:19 PM PDT 24 86285416 ps
T700 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3892109275 Apr 25 03:54:14 PM PDT 24 Apr 25 03:54:18 PM PDT 24 63798474 ps
T701 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.738397035 Apr 25 03:54:33 PM PDT 24 Apr 25 03:54:35 PM PDT 24 177369130 ps
T702 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1770026096 Apr 25 03:54:49 PM PDT 24 Apr 25 03:54:50 PM PDT 24 23342331 ps
T703 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2263370591 Apr 25 03:52:57 PM PDT 24 Apr 25 03:52:59 PM PDT 24 87280790 ps
T704 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.144443646 Apr 25 03:54:21 PM PDT 24 Apr 25 03:54:25 PM PDT 24 405008018 ps
T705 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.731046168 Apr 25 03:52:54 PM PDT 24 Apr 25 03:53:06 PM PDT 24 741140746 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2945206664 Apr 25 03:53:23 PM PDT 24 Apr 25 03:53:25 PM PDT 24 20214472 ps
T706 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3224878020 Apr 25 03:54:49 PM PDT 24 Apr 25 03:54:52 PM PDT 24 36954097 ps
T707 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2885073187 Apr 25 03:54:38 PM PDT 24 Apr 25 03:54:40 PM PDT 24 126456606 ps
T708 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1681390493 Apr 25 03:54:02 PM PDT 24 Apr 25 03:54:04 PM PDT 24 28737300 ps
T709 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3270595616 Apr 25 03:53:46 PM PDT 24 Apr 25 03:53:49 PM PDT 24 309198295 ps
T710 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1089376337 Apr 25 03:53:58 PM PDT 24 Apr 25 03:54:00 PM PDT 24 164533263 ps
T711 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1560886782 Apr 25 03:54:33 PM PDT 24 Apr 25 03:54:34 PM PDT 24 17070105 ps
T712 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1639347830 Apr 25 03:54:06 PM PDT 24 Apr 25 03:54:08 PM PDT 24 34671620 ps
T713 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2968405113 Apr 25 03:53:47 PM PDT 24 Apr 25 03:53:50 PM PDT 24 76418187 ps
T714 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3001333066 Apr 25 03:52:49 PM PDT 24 Apr 25 03:52:50 PM PDT 24 36842020 ps
T715 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3712087363 Apr 25 03:54:57 PM PDT 24 Apr 25 03:54:59 PM PDT 24 20594105 ps
T112 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2178703190 Apr 25 03:52:27 PM PDT 24 Apr 25 03:52:29 PM PDT 24 143365592 ps
T716 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3445749654 Apr 25 03:54:13 PM PDT 24 Apr 25 03:54:16 PM PDT 24 115315975 ps
T717 /workspace/coverage/cover_reg_top/14.hmac_intr_test.147459101 Apr 25 03:54:25 PM PDT 24 Apr 25 03:54:27 PM PDT 24 12010391 ps
T718 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2926149968 Apr 25 03:52:35 PM PDT 24 Apr 25 03:52:38 PM PDT 24 114540298 ps
T95 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.76618258 Apr 25 03:54:06 PM PDT 24 Apr 25 03:54:07 PM PDT 24 30420779 ps
T719 /workspace/coverage/cover_reg_top/37.hmac_intr_test.127345981 Apr 25 03:55:12 PM PDT 24 Apr 25 03:55:14 PM PDT 24 16614629 ps
T720 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1107597618 Apr 25 03:54:15 PM PDT 24 Apr 25 03:54:17 PM PDT 24 328706672 ps
T721 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1198150984 Apr 25 03:53:24 PM PDT 24 Apr 25 03:53:27 PM PDT 24 43183170 ps
T722 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3890111180 Apr 25 03:53:07 PM PDT 24 Apr 25 03:53:09 PM PDT 24 37436755 ps
T723 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1349808268 Apr 25 03:55:00 PM PDT 24 Apr 25 03:55:02 PM PDT 24 37891014 ps
T724 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4021113712 Apr 25 03:53:29 PM PDT 24 Apr 25 03:53:32 PM PDT 24 85479727 ps
T725 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.506727030 Apr 25 03:54:38 PM PDT 24 Apr 25 03:54:40 PM PDT 24 100898930 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1581906515 Apr 25 03:52:44 PM PDT 24 Apr 25 03:52:47 PM PDT 24 119941479 ps
T727 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3214551150 Apr 25 03:54:48 PM PDT 24 Apr 25 03:54:51 PM PDT 24 100428887 ps
T96 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1069213446 Apr 25 03:54:33 PM PDT 24 Apr 25 03:54:34 PM PDT 24 18779029 ps
T100 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1136586209 Apr 25 03:54:13 PM PDT 24 Apr 25 03:54:15 PM PDT 24 133199772 ps
T97 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.233001378 Apr 25 03:54:18 PM PDT 24 Apr 25 03:54:20 PM PDT 24 113725134 ps
T728 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2286931360 Apr 25 03:52:31 PM PDT 24 Apr 25 03:52:35 PM PDT 24 155062794 ps
T98 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4182194836 Apr 25 03:53:05 PM PDT 24 Apr 25 03:53:07 PM PDT 24 39058735 ps
T729 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1011019673 Apr 25 03:54:02 PM PDT 24 Apr 25 03:54:06 PM PDT 24 51652670 ps
T730 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.915115872 Apr 25 03:55:02 PM PDT 24 Apr 25 03:55:05 PM PDT 24 314310594 ps
T731 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2673237991 Apr 25 03:53:37 PM PDT 24 Apr 25 03:53:38 PM PDT 24 163389417 ps
T732 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3221126216 Apr 25 03:54:27 PM PDT 24 Apr 25 03:54:29 PM PDT 24 50741587 ps

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.754134582
Short name T7
Test name
Test status
Simulation time 51239469844 ps
CPU time 2092.56 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:39:42 PM PDT 24
Peak memory 245592 kb
Host smart-359a5d69-816c-410f-a1bf-da8a79dfd501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754134582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.754134582
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_error.2575355570
Short name T16
Test name
Test status
Simulation time 38165633217 ps
CPU time 135.78 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:06:00 PM PDT 24
Peak memory 199708 kb
Host smart-fb1f95f6-bb41-4d8c-ba0a-24b856260457
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575355570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2575355570
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3476723929
Short name T12
Test name
Test status
Simulation time 48292211342 ps
CPU time 1014.03 seconds
Started Apr 25 01:05:41 PM PDT 24
Finished Apr 25 01:22:36 PM PDT 24
Peak memory 257156 kb
Host smart-8bd5807d-cfc5-45ee-b07a-e6b65520e627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476723929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.3476723929
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.33827864
Short name T24
Test name
Test status
Simulation time 203449508 ps
CPU time 0.8 seconds
Started Apr 25 01:03:24 PM PDT 24
Finished Apr 25 01:03:25 PM PDT 24
Peak memory 217560 kb
Host smart-333b2feb-5dae-44f7-9cd3-4f8881caf6d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33827864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.33827864
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2781451912
Short name T58
Test name
Test status
Simulation time 627866782 ps
CPU time 3.02 seconds
Started Apr 25 03:54:17 PM PDT 24
Finished Apr 25 03:54:21 PM PDT 24
Peak memory 199276 kb
Host smart-eb2bf0d2-9066-411a-b4bb-5ad804b6c843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781451912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2781451912
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2554895094
Short name T29
Test name
Test status
Simulation time 73388865999 ps
CPU time 908.91 seconds
Started Apr 25 01:03:54 PM PDT 24
Finished Apr 25 01:19:04 PM PDT 24
Peak memory 199728 kb
Host smart-51a3a150-c778-426f-a19b-a7cfa65b2d8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554895094 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2554895094
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1423284297
Short name T91
Test name
Test status
Simulation time 54992829 ps
CPU time 0.92 seconds
Started Apr 25 03:53:51 PM PDT 24
Finished Apr 25 03:53:52 PM PDT 24
Peak memory 198808 kb
Host smart-dbc40dbf-db6c-49ec-9551-3021c00588d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423284297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1423284297
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3634084519
Short name T1
Test name
Test status
Simulation time 15291749 ps
CPU time 0.65 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:00 PM PDT 24
Peak memory 195320 kb
Host smart-a0281bd1-1239-4f5f-971f-5c4789342693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634084519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3634084519
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.58425342
Short name T111
Test name
Test status
Simulation time 133987942 ps
CPU time 4.2 seconds
Started Apr 25 03:54:31 PM PDT 24
Finished Apr 25 03:54:36 PM PDT 24
Peak memory 199340 kb
Host smart-eb0f8317-2af0-403c-baec-6f30e8d6bba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58425342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.58425342
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3772046231
Short name T63
Test name
Test status
Simulation time 247646933 ps
CPU time 3.82 seconds
Started Apr 25 03:54:33 PM PDT 24
Finished Apr 25 03:54:37 PM PDT 24
Peak memory 199280 kb
Host smart-6bb37678-867f-447b-a68a-86f4980dd94a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772046231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3772046231
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2389201439
Short name T36
Test name
Test status
Simulation time 35096871 ps
CPU time 0.79 seconds
Started Apr 25 01:03:41 PM PDT 24
Finished Apr 25 01:03:43 PM PDT 24
Peak memory 218116 kb
Host smart-a3f4425b-e6e3-4b5a-a924-4f2fe238d4d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389201439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2389201439
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2025852262
Short name T3
Test name
Test status
Simulation time 246749943 ps
CPU time 0.96 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 199452 kb
Host smart-dcb1d36c-f4b2-4891-8606-4f29d5e8408e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025852262 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2025852262
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1714598046
Short name T106
Test name
Test status
Simulation time 319841195 ps
CPU time 1.81 seconds
Started Apr 25 03:52:55 PM PDT 24
Finished Apr 25 03:52:58 PM PDT 24
Peak memory 199328 kb
Host smart-cafb9420-d086-406c-b955-c3838e8a1a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714598046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1714598046
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1508049792
Short name T47
Test name
Test status
Simulation time 79214070660 ps
CPU time 414.49 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:11:06 PM PDT 24
Peak memory 199724 kb
Host smart-57c34e75-bb34-46f5-bc2e-0339fb1de9c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508049792 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1508049792
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_error.3386539399
Short name T50
Test name
Test status
Simulation time 7722349470 ps
CPU time 133.48 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:06:56 PM PDT 24
Peak memory 199736 kb
Host smart-e8e2bed5-9390-49e8-88bf-b91a8e7b152f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386539399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3386539399
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2926149968
Short name T718
Test name
Test status
Simulation time 114540298 ps
CPU time 2.99 seconds
Started Apr 25 03:52:35 PM PDT 24
Finished Apr 25 03:52:38 PM PDT 24
Peak memory 198016 kb
Host smart-efb7f98c-4ed0-4ca9-a666-810934db9a58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926149968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2926149968
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1058477217
Short name T94
Test name
Test status
Simulation time 1099626610 ps
CPU time 18.24 seconds
Started Apr 25 03:52:52 PM PDT 24
Finished Apr 25 03:53:10 PM PDT 24
Peak memory 198036 kb
Host smart-d54bdb35-7583-49d6-8924-e5a26ec741c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058477217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1058477217
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3914121878
Short name T85
Test name
Test status
Simulation time 41878892 ps
CPU time 1.02 seconds
Started Apr 25 03:52:38 PM PDT 24
Finished Apr 25 03:52:40 PM PDT 24
Peak memory 199120 kb
Host smart-e42ba727-26ca-4ddb-aaa6-7a634631e13b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914121878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3914121878
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.177407192
Short name T666
Test name
Test status
Simulation time 37936053 ps
CPU time 1.31 seconds
Started Apr 25 03:52:56 PM PDT 24
Finished Apr 25 03:52:58 PM PDT 24
Peak memory 199296 kb
Host smart-5ca4070e-2f3c-44f4-af31-75147690da18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177407192 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.177407192
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3001333066
Short name T714
Test name
Test status
Simulation time 36842020 ps
CPU time 0.78 seconds
Started Apr 25 03:52:49 PM PDT 24
Finished Apr 25 03:52:50 PM PDT 24
Peak memory 196916 kb
Host smart-e93d1882-1e07-4c94-a37d-bc37c6ab892a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001333066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3001333066
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2111490065
Short name T619
Test name
Test status
Simulation time 23002587 ps
CPU time 0.68 seconds
Started Apr 25 03:52:37 PM PDT 24
Finished Apr 25 03:52:38 PM PDT 24
Peak memory 194124 kb
Host smart-ad2a4d0e-1e72-4fd5-b971-aa1c4daadf1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111490065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2111490065
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1581906515
Short name T726
Test name
Test status
Simulation time 119941479 ps
CPU time 2.66 seconds
Started Apr 25 03:52:44 PM PDT 24
Finished Apr 25 03:52:47 PM PDT 24
Peak memory 199320 kb
Host smart-83771889-6cd6-42c4-8084-2a0c1db6397f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581906515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1581906515
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2286931360
Short name T728
Test name
Test status
Simulation time 155062794 ps
CPU time 3.34 seconds
Started Apr 25 03:52:31 PM PDT 24
Finished Apr 25 03:52:35 PM PDT 24
Peak memory 199424 kb
Host smart-43decbcc-06b2-473a-8128-f47af4746b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286931360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2286931360
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2178703190
Short name T112
Test name
Test status
Simulation time 143365592 ps
CPU time 1.81 seconds
Started Apr 25 03:52:27 PM PDT 24
Finished Apr 25 03:52:29 PM PDT 24
Peak memory 199320 kb
Host smart-70dbf27b-d7ab-4f67-9a7a-a26d95c789bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178703190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2178703190
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.633831917
Short name T90
Test name
Test status
Simulation time 1361500307 ps
CPU time 6.33 seconds
Started Apr 25 03:52:52 PM PDT 24
Finished Apr 25 03:52:59 PM PDT 24
Peak memory 198984 kb
Host smart-66e3e83e-dbe2-41e8-b28a-1d4ceb5b0726
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633831917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.633831917
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.731046168
Short name T705
Test name
Test status
Simulation time 741140746 ps
CPU time 11.35 seconds
Started Apr 25 03:52:54 PM PDT 24
Finished Apr 25 03:53:06 PM PDT 24
Peak memory 199212 kb
Host smart-dced541f-ba32-4d8e-9c0a-0d474b15e0c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731046168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.731046168
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3181597600
Short name T634
Test name
Test status
Simulation time 21232529 ps
CPU time 0.8 seconds
Started Apr 25 03:52:58 PM PDT 24
Finished Apr 25 03:53:00 PM PDT 24
Peak memory 196728 kb
Host smart-b63fce54-6454-4c65-abb7-e748f159bfb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181597600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3181597600
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2658377044
Short name T616
Test name
Test status
Simulation time 76597379102 ps
CPU time 129.78 seconds
Started Apr 25 03:53:02 PM PDT 24
Finished Apr 25 03:55:13 PM PDT 24
Peak memory 215824 kb
Host smart-69529d47-7e33-45b0-9023-ba0173e68c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658377044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2658377044
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2263370591
Short name T703
Test name
Test status
Simulation time 87280790 ps
CPU time 0.85 seconds
Started Apr 25 03:52:57 PM PDT 24
Finished Apr 25 03:52:59 PM PDT 24
Peak memory 198092 kb
Host smart-ccd37c9f-9f23-441d-ad39-47ba2cf0bc14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263370591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2263370591
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1880221785
Short name T633
Test name
Test status
Simulation time 18075598 ps
CPU time 0.62 seconds
Started Apr 25 03:52:53 PM PDT 24
Finished Apr 25 03:52:54 PM PDT 24
Peak memory 194204 kb
Host smart-89c61980-f8ca-44c0-926b-4f0707c23592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880221785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1880221785
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2678488978
Short name T672
Test name
Test status
Simulation time 118965023 ps
CPU time 1.65 seconds
Started Apr 25 03:52:56 PM PDT 24
Finished Apr 25 03:52:59 PM PDT 24
Peak memory 199036 kb
Host smart-3408df8d-a9b7-414b-89e2-1d8a8537d819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678488978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2678488978
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3169999706
Short name T685
Test name
Test status
Simulation time 494896277 ps
CPU time 2.9 seconds
Started Apr 25 03:52:51 PM PDT 24
Finished Apr 25 03:52:55 PM PDT 24
Peak memory 199388 kb
Host smart-8191ceac-569d-49d8-bc9e-938b7f3902f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169999706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3169999706
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2048784251
Short name T697
Test name
Test status
Simulation time 80571940997 ps
CPU time 812.92 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 04:07:47 PM PDT 24
Peak memory 224036 kb
Host smart-d609b1f6-ff51-4132-9f46-2fe5e4dee74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048784251 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2048784251
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.76618258
Short name T95
Test name
Test status
Simulation time 30420779 ps
CPU time 0.88 seconds
Started Apr 25 03:54:06 PM PDT 24
Finished Apr 25 03:54:07 PM PDT 24
Peak memory 198488 kb
Host smart-6e4a6dac-8f54-46fa-b388-2d4468c8b1f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76618258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.76618258
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1281350154
Short name T601
Test name
Test status
Simulation time 26855099 ps
CPU time 0.61 seconds
Started Apr 25 03:54:09 PM PDT 24
Finished Apr 25 03:54:10 PM PDT 24
Peak memory 194052 kb
Host smart-960c812e-5dad-49f2-854d-e32f8870e4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281350154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1281350154
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3445749654
Short name T716
Test name
Test status
Simulation time 115315975 ps
CPU time 1.14 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 03:54:16 PM PDT 24
Peak memory 198924 kb
Host smart-30f77cb0-44d9-48b5-b2e9-5198a344d220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445749654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3445749654
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2513734485
Short name T673
Test name
Test status
Simulation time 599380649 ps
CPU time 3.89 seconds
Started Apr 25 03:54:16 PM PDT 24
Finished Apr 25 03:54:21 PM PDT 24
Peak memory 199356 kb
Host smart-d282a7ce-d059-4f3f-949b-39bb281d8be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513734485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2513734485
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1311352086
Short name T108
Test name
Test status
Simulation time 51629041 ps
CPU time 1.83 seconds
Started Apr 25 03:54:05 PM PDT 24
Finished Apr 25 03:54:07 PM PDT 24
Peak memory 199356 kb
Host smart-93eede4e-4b2f-4554-8c7d-9078b5027159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311352086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1311352086
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2161955399
Short name T622
Test name
Test status
Simulation time 71539809 ps
CPU time 1.86 seconds
Started Apr 25 03:54:14 PM PDT 24
Finished Apr 25 03:54:17 PM PDT 24
Peak memory 199392 kb
Host smart-c3d5806b-92a1-4a32-8c64-b1c9d9348238
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161955399 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2161955399
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1136586209
Short name T100
Test name
Test status
Simulation time 133199772 ps
CPU time 1.01 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 03:54:15 PM PDT 24
Peak memory 198828 kb
Host smart-b63d9513-8714-4700-8dd3-9be22add6225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136586209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1136586209
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3221053599
Short name T624
Test name
Test status
Simulation time 99946999 ps
CPU time 0.6 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 03:54:15 PM PDT 24
Peak memory 194020 kb
Host smart-5ff6cc0e-623c-464c-a030-533952b9a037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221053599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3221053599
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2015667847
Short name T654
Test name
Test status
Simulation time 33961852 ps
CPU time 1.85 seconds
Started Apr 25 03:54:15 PM PDT 24
Finished Apr 25 03:54:17 PM PDT 24
Peak memory 199092 kb
Host smart-43512ee7-1c1a-4fe9-9c05-d493ef8b351b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015667847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2015667847
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.345223242
Short name T693
Test name
Test status
Simulation time 88589385 ps
CPU time 1.64 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 03:54:16 PM PDT 24
Peak memory 199324 kb
Host smart-87ca6118-cafa-411f-ab7a-eac1f7f165c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345223242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.345223242
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2599753600
Short name T663
Test name
Test status
Simulation time 107895237050 ps
CPU time 257.45 seconds
Started Apr 25 03:54:14 PM PDT 24
Finished Apr 25 03:58:32 PM PDT 24
Peak memory 215188 kb
Host smart-642e0d6d-9988-4139-abe0-09cbd1582511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599753600 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2599753600
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.233001378
Short name T97
Test name
Test status
Simulation time 113725134 ps
CPU time 0.89 seconds
Started Apr 25 03:54:18 PM PDT 24
Finished Apr 25 03:54:20 PM PDT 24
Peak memory 198688 kb
Host smart-78c1a840-e3b6-4d09-9407-2afb6a18fd00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233001378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.233001378
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3219017360
Short name T626
Test name
Test status
Simulation time 29321435 ps
CPU time 0.59 seconds
Started Apr 25 03:54:14 PM PDT 24
Finished Apr 25 03:54:16 PM PDT 24
Peak memory 194080 kb
Host smart-a39b5b8e-ffa4-4bff-a91a-6a4dc6c7b9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219017360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3219017360
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1107597618
Short name T720
Test name
Test status
Simulation time 328706672 ps
CPU time 1.99 seconds
Started Apr 25 03:54:15 PM PDT 24
Finished Apr 25 03:54:17 PM PDT 24
Peak memory 199332 kb
Host smart-e9c14103-aaf0-4905-8b1e-46af75a80da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107597618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1107597618
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.144443646
Short name T704
Test name
Test status
Simulation time 405008018 ps
CPU time 3.99 seconds
Started Apr 25 03:54:21 PM PDT 24
Finished Apr 25 03:54:25 PM PDT 24
Peak memory 199400 kb
Host smart-ecfefadd-e27f-46af-8880-e1e01d1e41d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144443646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.144443646
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.889003007
Short name T695
Test name
Test status
Simulation time 496289362 ps
CPU time 3.26 seconds
Started Apr 25 03:54:13 PM PDT 24
Finished Apr 25 03:54:18 PM PDT 24
Peak memory 199348 kb
Host smart-1471b079-677f-4c70-9905-9f69ce5df391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889003007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.889003007
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3712987999
Short name T638
Test name
Test status
Simulation time 37401660 ps
CPU time 1.31 seconds
Started Apr 25 03:54:46 PM PDT 24
Finished Apr 25 03:54:48 PM PDT 24
Peak memory 199300 kb
Host smart-f531fb23-9dce-4670-bdf5-16ddcb366d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712987999 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3712987999
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3221126216
Short name T732
Test name
Test status
Simulation time 50741587 ps
CPU time 0.87 seconds
Started Apr 25 03:54:27 PM PDT 24
Finished Apr 25 03:54:29 PM PDT 24
Peak memory 198620 kb
Host smart-82da12a9-6176-424b-ae1f-bd06b606a7a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221126216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3221126216
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2067900498
Short name T641
Test name
Test status
Simulation time 36529524 ps
CPU time 0.69 seconds
Started Apr 25 03:54:20 PM PDT 24
Finished Apr 25 03:54:21 PM PDT 24
Peak memory 194092 kb
Host smart-da80e468-b61e-4083-80c1-8347faadf117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067900498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2067900498
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3940537431
Short name T660
Test name
Test status
Simulation time 117431997 ps
CPU time 2.47 seconds
Started Apr 25 03:54:29 PM PDT 24
Finished Apr 25 03:54:32 PM PDT 24
Peak memory 199376 kb
Host smart-5460b264-f107-4b4d-864f-4437ca6e1be4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940537431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3940537431
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3892109275
Short name T700
Test name
Test status
Simulation time 63798474 ps
CPU time 3.38 seconds
Started Apr 25 03:54:14 PM PDT 24
Finished Apr 25 03:54:18 PM PDT 24
Peak memory 199368 kb
Host smart-af377bbe-8dd7-4a44-b37b-8620727fa4da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892109275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3892109275
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2400925255
Short name T612
Test name
Test status
Simulation time 22464713 ps
CPU time 1.26 seconds
Started Apr 25 03:54:28 PM PDT 24
Finished Apr 25 03:54:30 PM PDT 24
Peak memory 199300 kb
Host smart-fb2c60cb-b94f-41ca-b8ff-dced5ed26640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400925255 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2400925255
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2963200460
Short name T86
Test name
Test status
Simulation time 14135758 ps
CPU time 0.93 seconds
Started Apr 25 03:54:24 PM PDT 24
Finished Apr 25 03:54:26 PM PDT 24
Peak memory 198648 kb
Host smart-d115bb0f-37f7-4198-ac08-8d7c8e7eb0ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963200460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2963200460
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.147459101
Short name T717
Test name
Test status
Simulation time 12010391 ps
CPU time 0.61 seconds
Started Apr 25 03:54:25 PM PDT 24
Finished Apr 25 03:54:27 PM PDT 24
Peak memory 194208 kb
Host smart-1162986a-1095-4014-af9a-a4ddbaa8b21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147459101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.147459101
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.93016138
Short name T661
Test name
Test status
Simulation time 47127180 ps
CPU time 1.21 seconds
Started Apr 25 03:54:25 PM PDT 24
Finished Apr 25 03:54:27 PM PDT 24
Peak memory 198956 kb
Host smart-a33b773c-0c84-4682-b535-6cf311d426bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93016138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_
outstanding.93016138
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2246988885
Short name T675
Test name
Test status
Simulation time 47442492 ps
CPU time 2.59 seconds
Started Apr 25 03:54:24 PM PDT 24
Finished Apr 25 03:54:27 PM PDT 24
Peak memory 199400 kb
Host smart-08d57000-e23c-4e23-b331-95ebf7c8d929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246988885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2246988885
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3761703121
Short name T107
Test name
Test status
Simulation time 230422782 ps
CPU time 4.23 seconds
Started Apr 25 03:54:27 PM PDT 24
Finished Apr 25 03:54:32 PM PDT 24
Peak memory 199348 kb
Host smart-c7f0f574-2dde-4dc3-9afa-8865a6a08286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761703121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3761703121
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3318248212
Short name T639
Test name
Test status
Simulation time 44990287 ps
CPU time 2.71 seconds
Started Apr 25 03:54:28 PM PDT 24
Finished Apr 25 03:54:31 PM PDT 24
Peak memory 199472 kb
Host smart-7d20a5a9-39f9-4596-94b8-c15fce6fef82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318248212 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3318248212
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1560886782
Short name T711
Test name
Test status
Simulation time 17070105 ps
CPU time 0.94 seconds
Started Apr 25 03:54:33 PM PDT 24
Finished Apr 25 03:54:34 PM PDT 24
Peak memory 198460 kb
Host smart-130e0f82-5f22-44a0-8d39-4fd57034d335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560886782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1560886782
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1181246059
Short name T668
Test name
Test status
Simulation time 67846542 ps
CPU time 0.58 seconds
Started Apr 25 03:54:28 PM PDT 24
Finished Apr 25 03:54:29 PM PDT 24
Peak memory 194100 kb
Host smart-72cb75df-9843-4969-b136-1a986961be0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181246059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1181246059
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1825722917
Short name T644
Test name
Test status
Simulation time 227600420 ps
CPU time 1.78 seconds
Started Apr 25 03:54:39 PM PDT 24
Finished Apr 25 03:54:42 PM PDT 24
Peak memory 199336 kb
Host smart-22702b31-9435-471d-a95f-17fb34aa4fa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825722917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1825722917
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3358003326
Short name T630
Test name
Test status
Simulation time 33587536 ps
CPU time 1.72 seconds
Started Apr 25 03:54:27 PM PDT 24
Finished Apr 25 03:54:29 PM PDT 24
Peak memory 199388 kb
Host smart-686023ce-ae34-4595-b594-257b2d6b54bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358003326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3358003326
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.665222193
Short name T59
Test name
Test status
Simulation time 810603818 ps
CPU time 3.27 seconds
Started Apr 25 03:54:27 PM PDT 24
Finished Apr 25 03:54:31 PM PDT 24
Peak memory 199336 kb
Host smart-1f57a785-7427-4288-a947-1f3572b3a347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665222193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.665222193
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2885073187
Short name T707
Test name
Test status
Simulation time 126456606 ps
CPU time 1.27 seconds
Started Apr 25 03:54:38 PM PDT 24
Finished Apr 25 03:54:40 PM PDT 24
Peak memory 199288 kb
Host smart-d5a1fae8-be13-4f43-91f8-916b2a2c8d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885073187 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2885073187
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1069213446
Short name T96
Test name
Test status
Simulation time 18779029 ps
CPU time 0.91 seconds
Started Apr 25 03:54:33 PM PDT 24
Finished Apr 25 03:54:34 PM PDT 24
Peak memory 198556 kb
Host smart-299e96ab-ff65-4c70-af28-5abf2766e41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069213446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1069213446
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1842919596
Short name T608
Test name
Test status
Simulation time 36126523 ps
CPU time 0.57 seconds
Started Apr 25 03:54:25 PM PDT 24
Finished Apr 25 03:54:26 PM PDT 24
Peak memory 194084 kb
Host smart-bbcd7964-e155-4982-8102-dd05d91b78b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842919596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1842919596
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1233521027
Short name T623
Test name
Test status
Simulation time 430792305 ps
CPU time 1.89 seconds
Started Apr 25 03:54:41 PM PDT 24
Finished Apr 25 03:54:44 PM PDT 24
Peak memory 199144 kb
Host smart-5555aa0f-1b24-4766-8b54-89e4325a2819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233521027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1233521027
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1433025640
Short name T603
Test name
Test status
Simulation time 125549492 ps
CPU time 3.48 seconds
Started Apr 25 03:54:32 PM PDT 24
Finished Apr 25 03:54:36 PM PDT 24
Peak memory 199392 kb
Host smart-14b35486-0e03-4317-b41b-44e753694502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433025640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1433025640
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.738397035
Short name T701
Test name
Test status
Simulation time 177369130 ps
CPU time 1.97 seconds
Started Apr 25 03:54:33 PM PDT 24
Finished Apr 25 03:54:35 PM PDT 24
Peak memory 199308 kb
Host smart-beaac5fd-3ede-43a6-8969-322772aced64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738397035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.738397035
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1289810568
Short name T602
Test name
Test status
Simulation time 182697668 ps
CPU time 2.93 seconds
Started Apr 25 03:54:42 PM PDT 24
Finished Apr 25 03:54:46 PM PDT 24
Peak memory 207592 kb
Host smart-a6df4bdb-a944-4c4d-9e7f-e455480f2a47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289810568 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1289810568
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.506727030
Short name T725
Test name
Test status
Simulation time 100898930 ps
CPU time 0.95 seconds
Started Apr 25 03:54:38 PM PDT 24
Finished Apr 25 03:54:40 PM PDT 24
Peak memory 198828 kb
Host smart-303a7a2b-a38a-4591-9ded-5417ae6152e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506727030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.506727030
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2288474066
Short name T640
Test name
Test status
Simulation time 19703259 ps
CPU time 0.69 seconds
Started Apr 25 03:54:41 PM PDT 24
Finished Apr 25 03:54:43 PM PDT 24
Peak memory 194196 kb
Host smart-bddf0409-7300-4328-89f7-4e9d1d7aecdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288474066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2288474066
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1518290552
Short name T649
Test name
Test status
Simulation time 164976200 ps
CPU time 2.14 seconds
Started Apr 25 03:54:39 PM PDT 24
Finished Apr 25 03:54:42 PM PDT 24
Peak memory 199044 kb
Host smart-67bf86cc-3acb-4aa5-b90a-7cecc1685a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518290552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1518290552
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1428947733
Short name T658
Test name
Test status
Simulation time 592595894 ps
CPU time 3.24 seconds
Started Apr 25 03:54:36 PM PDT 24
Finished Apr 25 03:54:40 PM PDT 24
Peak memory 199456 kb
Host smart-e5c2bc93-687a-44d2-b474-02b2bea7a623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428947733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1428947733
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.671909625
Short name T625
Test name
Test status
Simulation time 44201284 ps
CPU time 3.16 seconds
Started Apr 25 03:54:48 PM PDT 24
Finished Apr 25 03:54:52 PM PDT 24
Peak memory 199404 kb
Host smart-14608b8b-b105-4e1c-a460-1346dfa674ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671909625 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.671909625
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3420955155
Short name T686
Test name
Test status
Simulation time 17570628 ps
CPU time 0.8 seconds
Started Apr 25 03:54:47 PM PDT 24
Finished Apr 25 03:54:48 PM PDT 24
Peak memory 198220 kb
Host smart-049b1efc-d92a-4a20-bfaa-ac109c4e289b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420955155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3420955155
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1418938885
Short name T607
Test name
Test status
Simulation time 19744710 ps
CPU time 0.66 seconds
Started Apr 25 03:54:53 PM PDT 24
Finished Apr 25 03:54:55 PM PDT 24
Peak memory 194172 kb
Host smart-f9f499e9-1ba0-46a9-a245-6cb11914f16e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418938885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1418938885
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1193437922
Short name T677
Test name
Test status
Simulation time 86168261 ps
CPU time 2.08 seconds
Started Apr 25 03:54:49 PM PDT 24
Finished Apr 25 03:54:52 PM PDT 24
Peak memory 199340 kb
Host smart-1d68b108-586f-43c9-9160-5ce62d4d67cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193437922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1193437922
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3041087499
Short name T650
Test name
Test status
Simulation time 245894971 ps
CPU time 3.18 seconds
Started Apr 25 03:54:45 PM PDT 24
Finished Apr 25 03:54:49 PM PDT 24
Peak memory 199360 kb
Host smart-9d59fc54-ece7-4a0a-9922-e0cbabee0995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041087499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3041087499
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.11471138
Short name T657
Test name
Test status
Simulation time 57968659 ps
CPU time 1.77 seconds
Started Apr 25 03:54:45 PM PDT 24
Finished Apr 25 03:54:47 PM PDT 24
Peak memory 199308 kb
Host smart-ca653ec1-0a1d-45ea-8e57-2b1f226cbe56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.11471138
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3224878020
Short name T706
Test name
Test status
Simulation time 36954097 ps
CPU time 2.28 seconds
Started Apr 25 03:54:49 PM PDT 24
Finished Apr 25 03:54:52 PM PDT 24
Peak memory 199404 kb
Host smart-809ec335-0e21-4122-af39-ff9bfab277cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224878020 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3224878020
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2909553320
Short name T62
Test name
Test status
Simulation time 30371842 ps
CPU time 0.78 seconds
Started Apr 25 03:54:50 PM PDT 24
Finished Apr 25 03:54:51 PM PDT 24
Peak memory 197300 kb
Host smart-36520896-3701-47a1-9928-9d9e479fc3d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909553320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2909553320
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1770026096
Short name T702
Test name
Test status
Simulation time 23342331 ps
CPU time 0.72 seconds
Started Apr 25 03:54:49 PM PDT 24
Finished Apr 25 03:54:50 PM PDT 24
Peak memory 194104 kb
Host smart-ca2db417-9082-442d-951b-ceebe886b468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770026096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1770026096
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.915115872
Short name T730
Test name
Test status
Simulation time 314310594 ps
CPU time 2.16 seconds
Started Apr 25 03:55:02 PM PDT 24
Finished Apr 25 03:55:05 PM PDT 24
Peak memory 199012 kb
Host smart-8e8ca51d-90b1-4a20-bcaf-b78bd6e328df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915115872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.915115872
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1166153772
Short name T652
Test name
Test status
Simulation time 69731276 ps
CPU time 3.66 seconds
Started Apr 25 03:54:44 PM PDT 24
Finished Apr 25 03:54:48 PM PDT 24
Peak memory 199348 kb
Host smart-96224be6-c3e3-423c-a8af-4c047a195680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166153772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1166153772
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3214551150
Short name T727
Test name
Test status
Simulation time 100428887 ps
CPU time 2.24 seconds
Started Apr 25 03:54:48 PM PDT 24
Finished Apr 25 03:54:51 PM PDT 24
Peak memory 199336 kb
Host smart-52a674ba-34bb-4280-bcf1-cf6adb5ad66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214551150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3214551150
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2702182740
Short name T632
Test name
Test status
Simulation time 301853571 ps
CPU time 6.73 seconds
Started Apr 25 03:53:11 PM PDT 24
Finished Apr 25 03:53:19 PM PDT 24
Peak memory 199280 kb
Host smart-fb4caad3-366d-489e-8569-6199d9c10d8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702182740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2702182740
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3356553461
Short name T696
Test name
Test status
Simulation time 6131164625 ps
CPU time 15.74 seconds
Started Apr 25 03:53:12 PM PDT 24
Finished Apr 25 03:53:29 PM PDT 24
Peak memory 199312 kb
Host smart-bd76bf7e-896d-4b57-adc7-2355cbacb905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356553461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3356553461
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3890111180
Short name T722
Test name
Test status
Simulation time 37436755 ps
CPU time 0.78 seconds
Started Apr 25 03:53:07 PM PDT 24
Finished Apr 25 03:53:09 PM PDT 24
Peak memory 197148 kb
Host smart-0cca1d91-bb61-4cf5-8491-3a515f4dabda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890111180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3890111180
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2416282985
Short name T674
Test name
Test status
Simulation time 41453797 ps
CPU time 2.64 seconds
Started Apr 25 03:53:15 PM PDT 24
Finished Apr 25 03:53:18 PM PDT 24
Peak memory 199276 kb
Host smart-3c72021d-a9cd-4ef0-9a0a-0f584054af76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416282985 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2416282985
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4182194836
Short name T98
Test name
Test status
Simulation time 39058735 ps
CPU time 0.99 seconds
Started Apr 25 03:53:05 PM PDT 24
Finished Apr 25 03:53:07 PM PDT 24
Peak memory 198948 kb
Host smart-381e1ddb-f265-4cd2-a76b-a04f52c6b044
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182194836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.4182194836
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.999370952
Short name T613
Test name
Test status
Simulation time 20205084 ps
CPU time 0.59 seconds
Started Apr 25 03:53:14 PM PDT 24
Finished Apr 25 03:53:16 PM PDT 24
Peak memory 194008 kb
Host smart-0cfb2aad-df24-4945-a350-db9cfbb85bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999370952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.999370952
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1198150984
Short name T721
Test name
Test status
Simulation time 43183170 ps
CPU time 1.86 seconds
Started Apr 25 03:53:24 PM PDT 24
Finished Apr 25 03:53:27 PM PDT 24
Peak memory 199184 kb
Host smart-15fca2db-63c9-4db9-b0b3-cfde60b46174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198150984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1198150984
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.96420962
Short name T679
Test name
Test status
Simulation time 249342575 ps
CPU time 2.64 seconds
Started Apr 25 03:52:59 PM PDT 24
Finished Apr 25 03:53:03 PM PDT 24
Peak memory 199444 kb
Host smart-514f0196-6097-47ad-a272-2f26d60b82a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96420962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.96420962
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3700580432
Short name T105
Test name
Test status
Simulation time 101146921 ps
CPU time 2.05 seconds
Started Apr 25 03:53:02 PM PDT 24
Finished Apr 25 03:53:05 PM PDT 24
Peak memory 199344 kb
Host smart-6ba7a6da-2001-4cb4-bbde-a7077fe0e0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700580432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3700580432
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2253601524
Short name T669
Test name
Test status
Simulation time 18063576 ps
CPU time 0.59 seconds
Started Apr 25 03:54:50 PM PDT 24
Finished Apr 25 03:54:51 PM PDT 24
Peak memory 194192 kb
Host smart-d2e8b1b1-772f-4762-940c-85d16bfe38d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253601524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2253601524
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4276139364
Short name T617
Test name
Test status
Simulation time 14295970 ps
CPU time 0.66 seconds
Started Apr 25 03:54:50 PM PDT 24
Finished Apr 25 03:54:51 PM PDT 24
Peak memory 194208 kb
Host smart-3eb33680-2305-4742-9aa5-9c555d401626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276139364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4276139364
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1363989376
Short name T682
Test name
Test status
Simulation time 15614615 ps
CPU time 0.64 seconds
Started Apr 25 03:54:49 PM PDT 24
Finished Apr 25 03:54:51 PM PDT 24
Peak memory 194088 kb
Host smart-4bde7804-9706-48de-9501-88d248ccb633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363989376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1363989376
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1120344773
Short name T681
Test name
Test status
Simulation time 16498850 ps
CPU time 0.61 seconds
Started Apr 25 03:54:58 PM PDT 24
Finished Apr 25 03:54:59 PM PDT 24
Peak memory 193936 kb
Host smart-ff5eba55-dcfc-4f85-9942-46656a054b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120344773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1120344773
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4203671125
Short name T655
Test name
Test status
Simulation time 15109271 ps
CPU time 0.6 seconds
Started Apr 25 03:54:54 PM PDT 24
Finished Apr 25 03:54:55 PM PDT 24
Peak memory 194068 kb
Host smart-68b1715a-6cf4-4011-b383-74f9262789f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203671125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4203671125
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.290905415
Short name T680
Test name
Test status
Simulation time 13155192 ps
CPU time 0.62 seconds
Started Apr 25 03:54:55 PM PDT 24
Finished Apr 25 03:54:56 PM PDT 24
Peak memory 194204 kb
Host smart-3f07eb08-8d31-43a8-9091-a1cdbf3fb9e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290905415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.290905415
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3712087363
Short name T715
Test name
Test status
Simulation time 20594105 ps
CPU time 0.61 seconds
Started Apr 25 03:54:57 PM PDT 24
Finished Apr 25 03:54:59 PM PDT 24
Peak memory 194056 kb
Host smart-0a45bfc3-93e5-4a8a-ab65-e7ebc9635371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712087363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3712087363
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.122301245
Short name T606
Test name
Test status
Simulation time 13770131 ps
CPU time 0.63 seconds
Started Apr 25 03:54:58 PM PDT 24
Finished Apr 25 03:55:00 PM PDT 24
Peak memory 193992 kb
Host smart-e2c2735c-efe9-40ff-b6dc-e28b0321c26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122301245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.122301245
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4156743557
Short name T698
Test name
Test status
Simulation time 20990695 ps
CPU time 0.63 seconds
Started Apr 25 03:54:54 PM PDT 24
Finished Apr 25 03:54:55 PM PDT 24
Peak memory 194104 kb
Host smart-e913117a-8372-4b34-9e32-f04fdc7225a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156743557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4156743557
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3805190599
Short name T651
Test name
Test status
Simulation time 34588888 ps
CPU time 0.57 seconds
Started Apr 25 03:54:54 PM PDT 24
Finished Apr 25 03:54:55 PM PDT 24
Peak memory 194052 kb
Host smart-650d1f02-8120-4750-9238-519bea13f46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805190599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3805190599
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3475148096
Short name T678
Test name
Test status
Simulation time 306664580 ps
CPU time 8.57 seconds
Started Apr 25 03:53:24 PM PDT 24
Finished Apr 25 03:53:33 PM PDT 24
Peak memory 198840 kb
Host smart-0beccda1-7586-45be-acd7-011d917d43a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475148096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3475148096
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1907986943
Short name T88
Test name
Test status
Simulation time 1716723559 ps
CPU time 10.14 seconds
Started Apr 25 03:53:25 PM PDT 24
Finished Apr 25 03:53:35 PM PDT 24
Peak memory 198228 kb
Host smart-801d5400-e788-4c3b-a47d-2faeb9cc51d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907986943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1907986943
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1343837097
Short name T61
Test name
Test status
Simulation time 39941022 ps
CPU time 0.81 seconds
Started Apr 25 03:53:15 PM PDT 24
Finished Apr 25 03:53:17 PM PDT 24
Peak memory 197168 kb
Host smart-00dd3b3d-1160-4c57-9973-d85ad5abd4f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343837097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1343837097
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4021113712
Short name T724
Test name
Test status
Simulation time 85479727 ps
CPU time 2.19 seconds
Started Apr 25 03:53:29 PM PDT 24
Finished Apr 25 03:53:32 PM PDT 24
Peak memory 199372 kb
Host smart-326e8234-a719-423f-a32b-e9ade3938028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021113712 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.4021113712
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2945206664
Short name T99
Test name
Test status
Simulation time 20214472 ps
CPU time 0.75 seconds
Started Apr 25 03:53:23 PM PDT 24
Finished Apr 25 03:53:25 PM PDT 24
Peak memory 197132 kb
Host smart-d5b09334-9f9a-4d4f-a2f7-5e174907452d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945206664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2945206664
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3362806339
Short name T699
Test name
Test status
Simulation time 86285416 ps
CPU time 0.62 seconds
Started Apr 25 03:53:18 PM PDT 24
Finished Apr 25 03:53:19 PM PDT 24
Peak memory 194176 kb
Host smart-778f34c3-bd5b-4774-972d-ad314c72084f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362806339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3362806339
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.677516477
Short name T642
Test name
Test status
Simulation time 42523839 ps
CPU time 2.28 seconds
Started Apr 25 03:53:30 PM PDT 24
Finished Apr 25 03:53:32 PM PDT 24
Peak memory 199308 kb
Host smart-7efd4184-cf0b-410c-873c-e3dee2d9360d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677516477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.677516477
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.339105684
Short name T683
Test name
Test status
Simulation time 251143797 ps
CPU time 3.61 seconds
Started Apr 25 03:53:21 PM PDT 24
Finished Apr 25 03:53:25 PM PDT 24
Peak memory 199416 kb
Host smart-2dcaf092-beef-4a8e-bbde-51b75dad18ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339105684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.339105684
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4036053398
Short name T109
Test name
Test status
Simulation time 576050788 ps
CPU time 3.29 seconds
Started Apr 25 03:53:14 PM PDT 24
Finished Apr 25 03:53:18 PM PDT 24
Peak memory 199272 kb
Host smart-509c06a6-20f2-40de-9975-a96cf43d514e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036053398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4036053398
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.54431864
Short name T645
Test name
Test status
Simulation time 42650590 ps
CPU time 0.57 seconds
Started Apr 25 03:54:56 PM PDT 24
Finished Apr 25 03:54:57 PM PDT 24
Peak memory 194012 kb
Host smart-ff9d01da-dfe1-4717-be7e-fe0aa6ad0a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54431864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.54431864
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3348299625
Short name T659
Test name
Test status
Simulation time 54215684 ps
CPU time 0.6 seconds
Started Apr 25 03:54:54 PM PDT 24
Finished Apr 25 03:54:55 PM PDT 24
Peak memory 194132 kb
Host smart-d29fe53d-8c2c-4376-9926-d7151e1404d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348299625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3348299625
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.678725269
Short name T665
Test name
Test status
Simulation time 13499868 ps
CPU time 0.65 seconds
Started Apr 25 03:55:01 PM PDT 24
Finished Apr 25 03:55:02 PM PDT 24
Peak memory 194152 kb
Host smart-d283a4e9-286b-4d5a-a8f8-ec2e8d52b76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678725269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.678725269
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2282271336
Short name T662
Test name
Test status
Simulation time 14958590 ps
CPU time 0.64 seconds
Started Apr 25 03:54:58 PM PDT 24
Finished Apr 25 03:55:00 PM PDT 24
Peak memory 194144 kb
Host smart-2ade4d1d-f996-458d-9a85-d1dbbfcf2c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282271336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2282271336
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1349808268
Short name T723
Test name
Test status
Simulation time 37891014 ps
CPU time 0.64 seconds
Started Apr 25 03:55:00 PM PDT 24
Finished Apr 25 03:55:02 PM PDT 24
Peak memory 194116 kb
Host smart-d2d89bed-f8de-45a9-9a0c-0e5de17e6008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349808268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1349808268
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1391384294
Short name T671
Test name
Test status
Simulation time 20264937 ps
CPU time 0.63 seconds
Started Apr 25 03:55:02 PM PDT 24
Finished Apr 25 03:55:03 PM PDT 24
Peak memory 194216 kb
Host smart-c5842d1e-8a64-4d40-aa28-631243e36b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391384294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1391384294
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.127798219
Short name T631
Test name
Test status
Simulation time 20977251 ps
CPU time 0.65 seconds
Started Apr 25 03:55:07 PM PDT 24
Finished Apr 25 03:55:08 PM PDT 24
Peak memory 194216 kb
Host smart-8ac10ef9-17de-4075-9edc-47948e3c6605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127798219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.127798219
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.127345981
Short name T719
Test name
Test status
Simulation time 16614629 ps
CPU time 0.64 seconds
Started Apr 25 03:55:12 PM PDT 24
Finished Apr 25 03:55:14 PM PDT 24
Peak memory 194024 kb
Host smart-cce31439-fa58-4e7c-a869-f5ff076700e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127345981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.127345981
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.366676706
Short name T656
Test name
Test status
Simulation time 32370814 ps
CPU time 0.66 seconds
Started Apr 25 03:55:13 PM PDT 24
Finished Apr 25 03:55:15 PM PDT 24
Peak memory 194116 kb
Host smart-11efbab3-2c3d-4bdf-9dbf-4383050892fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366676706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.366676706
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3347554906
Short name T691
Test name
Test status
Simulation time 33200970 ps
CPU time 0.6 seconds
Started Apr 25 03:55:06 PM PDT 24
Finished Apr 25 03:55:07 PM PDT 24
Peak memory 194208 kb
Host smart-02ea87aa-b893-4f66-8dbd-764b2de3e599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347554906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3347554906
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.381884877
Short name T643
Test name
Test status
Simulation time 679450107 ps
CPU time 3.99 seconds
Started Apr 25 03:53:37 PM PDT 24
Finished Apr 25 03:53:41 PM PDT 24
Peak memory 199272 kb
Host smart-98291ab3-f9bf-48c4-be70-3b661aaf2634
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381884877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.381884877
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3494939924
Short name T93
Test name
Test status
Simulation time 2260604445 ps
CPU time 10.94 seconds
Started Apr 25 03:53:30 PM PDT 24
Finished Apr 25 03:53:42 PM PDT 24
Peak memory 198184 kb
Host smart-da46e463-d811-464c-a27d-ccdc47b2bcc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494939924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3494939924
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2555135862
Short name T690
Test name
Test status
Simulation time 52090853 ps
CPU time 0.7 seconds
Started Apr 25 03:53:23 PM PDT 24
Finished Apr 25 03:53:25 PM PDT 24
Peak memory 197372 kb
Host smart-c3879cf9-a194-4efc-9631-a8cafc71bd7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555135862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2555135862
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2548244955
Short name T605
Test name
Test status
Simulation time 87794628 ps
CPU time 2.78 seconds
Started Apr 25 03:53:40 PM PDT 24
Finished Apr 25 03:53:43 PM PDT 24
Peak memory 207728 kb
Host smart-f0fcd710-c514-447a-b02b-607ef91262d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548244955 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2548244955
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.284821711
Short name T87
Test name
Test status
Simulation time 19900803 ps
CPU time 0.72 seconds
Started Apr 25 03:53:29 PM PDT 24
Finished Apr 25 03:53:30 PM PDT 24
Peak memory 197464 kb
Host smart-360a053a-9de1-4956-80b8-cde6e0d7f25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284821711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.284821711
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3594045069
Short name T670
Test name
Test status
Simulation time 11236216 ps
CPU time 0.66 seconds
Started Apr 25 03:53:37 PM PDT 24
Finished Apr 25 03:53:38 PM PDT 24
Peak memory 194204 kb
Host smart-04b2ae6d-3494-45a5-8ccd-f7a14a8981cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594045069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3594045069
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3953277325
Short name T628
Test name
Test status
Simulation time 38294700 ps
CPU time 1.11 seconds
Started Apr 25 03:53:36 PM PDT 24
Finished Apr 25 03:53:38 PM PDT 24
Peak memory 199320 kb
Host smart-8dc94814-7c1f-4ff4-b8f4-94ccbf3f8dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953277325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3953277325
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.464800751
Short name T600
Test name
Test status
Simulation time 176326751 ps
CPU time 2.2 seconds
Started Apr 25 03:53:25 PM PDT 24
Finished Apr 25 03:53:28 PM PDT 24
Peak memory 199392 kb
Host smart-ed38cc96-1abb-4c5b-9253-c8ff3fa51efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464800751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.464800751
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3366604138
Short name T104
Test name
Test status
Simulation time 445288574 ps
CPU time 4 seconds
Started Apr 25 03:53:23 PM PDT 24
Finished Apr 25 03:53:28 PM PDT 24
Peak memory 199336 kb
Host smart-e72c1220-7c1d-4513-a841-e92a126fc830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366604138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3366604138
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.399142409
Short name T615
Test name
Test status
Simulation time 39438003 ps
CPU time 0.79 seconds
Started Apr 25 03:55:35 PM PDT 24
Finished Apr 25 03:55:36 PM PDT 24
Peak memory 194072 kb
Host smart-b6a226aa-8d27-4e4e-814b-da636961ad59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399142409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.399142409
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2820208670
Short name T687
Test name
Test status
Simulation time 77311392 ps
CPU time 0.63 seconds
Started Apr 25 03:55:04 PM PDT 24
Finished Apr 25 03:55:05 PM PDT 24
Peak memory 194144 kb
Host smart-a4d11b47-0bbe-4c83-8b1f-031473491e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820208670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2820208670
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3024116465
Short name T611
Test name
Test status
Simulation time 17329125 ps
CPU time 0.68 seconds
Started Apr 25 03:55:05 PM PDT 24
Finished Apr 25 03:55:07 PM PDT 24
Peak memory 194212 kb
Host smart-bde75c86-904e-4a24-8e2e-100f71af7a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024116465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3024116465
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.285169392
Short name T618
Test name
Test status
Simulation time 48420388 ps
CPU time 0.69 seconds
Started Apr 25 03:55:05 PM PDT 24
Finished Apr 25 03:55:06 PM PDT 24
Peak memory 194076 kb
Host smart-3adf9ac5-b3c7-4a9a-bf42-dbc9d9424d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285169392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.285169392
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.4136791346
Short name T664
Test name
Test status
Simulation time 18984481 ps
CPU time 0.59 seconds
Started Apr 25 03:55:06 PM PDT 24
Finished Apr 25 03:55:07 PM PDT 24
Peak memory 194208 kb
Host smart-2bf90fc9-4b9c-4d46-ad63-051b5a2f4fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136791346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4136791346
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.301422237
Short name T614
Test name
Test status
Simulation time 17775047 ps
CPU time 0.65 seconds
Started Apr 25 03:55:05 PM PDT 24
Finished Apr 25 03:55:06 PM PDT 24
Peak memory 194216 kb
Host smart-4d216167-bf73-482d-b915-1af1682b228c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301422237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.301422237
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1125411478
Short name T688
Test name
Test status
Simulation time 48492241 ps
CPU time 0.66 seconds
Started Apr 25 03:55:03 PM PDT 24
Finished Apr 25 03:55:04 PM PDT 24
Peak memory 194216 kb
Host smart-e1775e7c-2c9f-4f09-89bf-a86bfac4488e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125411478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1125411478
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4005231342
Short name T648
Test name
Test status
Simulation time 91405383 ps
CPU time 0.63 seconds
Started Apr 25 03:55:04 PM PDT 24
Finished Apr 25 03:55:05 PM PDT 24
Peak memory 194084 kb
Host smart-aa7d0f70-e0a2-4bf7-b497-4b673bb8d8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005231342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4005231342
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.974857604
Short name T653
Test name
Test status
Simulation time 41632386 ps
CPU time 0.6 seconds
Started Apr 25 03:55:05 PM PDT 24
Finished Apr 25 03:55:07 PM PDT 24
Peak memory 194188 kb
Host smart-df66eca8-3b5b-4f58-8acf-a98c3e139b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974857604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.974857604
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3423158665
Short name T629
Test name
Test status
Simulation time 35269442 ps
CPU time 0.57 seconds
Started Apr 25 03:55:13 PM PDT 24
Finished Apr 25 03:55:15 PM PDT 24
Peak memory 194148 kb
Host smart-98c314e1-1ab3-46ef-a7be-37e1253f592d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423158665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3423158665
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2968405113
Short name T713
Test name
Test status
Simulation time 76418187 ps
CPU time 1.92 seconds
Started Apr 25 03:53:47 PM PDT 24
Finished Apr 25 03:53:50 PM PDT 24
Peak memory 199388 kb
Host smart-d591a0a2-fbeb-4f6f-b2d6-7028ec4a5808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968405113 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2968405113
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2673237991
Short name T731
Test name
Test status
Simulation time 163389417 ps
CPU time 0.75 seconds
Started Apr 25 03:53:37 PM PDT 24
Finished Apr 25 03:53:38 PM PDT 24
Peak memory 197040 kb
Host smart-d4f0c40e-c942-4796-b0e6-a02b0b15749b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673237991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2673237991
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2760946862
Short name T635
Test name
Test status
Simulation time 25935490 ps
CPU time 0.64 seconds
Started Apr 25 03:53:36 PM PDT 24
Finished Apr 25 03:53:37 PM PDT 24
Peak memory 194080 kb
Host smart-de354a6e-dfd0-4e7d-b911-2b01c1867a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760946862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2760946862
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3537595164
Short name T621
Test name
Test status
Simulation time 24562622 ps
CPU time 1.1 seconds
Started Apr 25 03:53:34 PM PDT 24
Finished Apr 25 03:53:35 PM PDT 24
Peak memory 197880 kb
Host smart-67ef76fd-6fe1-4af0-8164-819ca3c0df3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537595164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3537595164
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3270595616
Short name T709
Test name
Test status
Simulation time 309198295 ps
CPU time 2.65 seconds
Started Apr 25 03:53:46 PM PDT 24
Finished Apr 25 03:53:49 PM PDT 24
Peak memory 199392 kb
Host smart-9d1cd53b-641f-4b01-9a7a-5153357cab6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270595616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3270595616
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1133334899
Short name T60
Test name
Test status
Simulation time 181706502 ps
CPU time 3.16 seconds
Started Apr 25 03:53:36 PM PDT 24
Finished Apr 25 03:53:40 PM PDT 24
Peak memory 199336 kb
Host smart-48605148-3f48-4e53-a32e-2b2ca0524b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133334899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1133334899
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3224024742
Short name T667
Test name
Test status
Simulation time 33078786 ps
CPU time 1.22 seconds
Started Apr 25 03:53:52 PM PDT 24
Finished Apr 25 03:53:54 PM PDT 24
Peak memory 199316 kb
Host smart-b47ac45c-9e91-4496-9b95-0d30b2e168b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224024742 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3224024742
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1607409579
Short name T89
Test name
Test status
Simulation time 23466468 ps
CPU time 0.69 seconds
Started Apr 25 03:53:46 PM PDT 24
Finished Apr 25 03:53:48 PM PDT 24
Peak memory 196928 kb
Host smart-63d4e4b8-75b9-484d-805e-c8351ea27a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607409579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1607409579
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.855789058
Short name T604
Test name
Test status
Simulation time 41896120 ps
CPU time 0.64 seconds
Started Apr 25 03:53:42 PM PDT 24
Finished Apr 25 03:53:44 PM PDT 24
Peak memory 194104 kb
Host smart-9274a7a4-80cb-49a2-9fae-deccd1688781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855789058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.855789058
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.873175825
Short name T692
Test name
Test status
Simulation time 78810592 ps
CPU time 1.99 seconds
Started Apr 25 03:53:45 PM PDT 24
Finished Apr 25 03:53:47 PM PDT 24
Peak memory 199016 kb
Host smart-b61047fc-462c-46b3-8ce0-60dbca32c0e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873175825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.873175825
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.790224911
Short name T689
Test name
Test status
Simulation time 124462901 ps
CPU time 1.87 seconds
Started Apr 25 03:53:42 PM PDT 24
Finished Apr 25 03:53:45 PM PDT 24
Peak memory 199388 kb
Host smart-12f1f144-19ea-4765-b1c0-22341703c603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790224911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.790224911
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.392133591
Short name T684
Test name
Test status
Simulation time 159149827 ps
CPU time 3.11 seconds
Started Apr 25 03:54:16 PM PDT 24
Finished Apr 25 03:54:20 PM PDT 24
Peak memory 199304 kb
Host smart-4fc8ce14-087d-4d1b-8058-bcd9c3f7223e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392133591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.392133591
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1419610283
Short name T627
Test name
Test status
Simulation time 46774471 ps
CPU time 1.3 seconds
Started Apr 25 03:53:51 PM PDT 24
Finished Apr 25 03:53:52 PM PDT 24
Peak memory 199232 kb
Host smart-d1335139-5de7-454b-b959-6495bebbc279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419610283 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1419610283
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1927656785
Short name T636
Test name
Test status
Simulation time 15751620 ps
CPU time 0.59 seconds
Started Apr 25 03:53:51 PM PDT 24
Finished Apr 25 03:53:52 PM PDT 24
Peak memory 194128 kb
Host smart-02a5b584-25cb-4eb0-89fc-2097cac6ab97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927656785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1927656785
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1089376337
Short name T710
Test name
Test status
Simulation time 164533263 ps
CPU time 1.34 seconds
Started Apr 25 03:53:58 PM PDT 24
Finished Apr 25 03:54:00 PM PDT 24
Peak memory 197684 kb
Host smart-b940749b-ed2b-485a-a5a8-80e615996488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089376337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1089376337
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.512104081
Short name T676
Test name
Test status
Simulation time 422741584 ps
CPU time 1.6 seconds
Started Apr 25 03:53:44 PM PDT 24
Finished Apr 25 03:53:46 PM PDT 24
Peak memory 199364 kb
Host smart-09da3171-fcb8-44e8-80d8-2dc59d915e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512104081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.512104081
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.471957991
Short name T113
Test name
Test status
Simulation time 1274047719 ps
CPU time 4.38 seconds
Started Apr 25 03:53:47 PM PDT 24
Finished Apr 25 03:53:53 PM PDT 24
Peak memory 199396 kb
Host smart-bb8cc5bb-9e5d-4aa6-8dba-0bb8aeb40729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471957991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.471957991
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.498592219
Short name T620
Test name
Test status
Simulation time 145199684 ps
CPU time 2.16 seconds
Started Apr 25 03:54:02 PM PDT 24
Finished Apr 25 03:54:05 PM PDT 24
Peak memory 199336 kb
Host smart-1be1b85d-aeea-4238-89ee-f7d3e7211b47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498592219 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.498592219
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3432375394
Short name T92
Test name
Test status
Simulation time 18359902 ps
CPU time 0.96 seconds
Started Apr 25 03:53:55 PM PDT 24
Finished Apr 25 03:53:57 PM PDT 24
Peak memory 198940 kb
Host smart-b5f704ff-758e-48bd-9e9c-8df8fb9d4988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432375394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3432375394
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1681390493
Short name T708
Test name
Test status
Simulation time 28737300 ps
CPU time 0.75 seconds
Started Apr 25 03:54:02 PM PDT 24
Finished Apr 25 03:54:04 PM PDT 24
Peak memory 194108 kb
Host smart-426c369a-dbdd-4415-bc55-4259d6516495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681390493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1681390493
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1653783760
Short name T637
Test name
Test status
Simulation time 97197548 ps
CPU time 1.04 seconds
Started Apr 25 03:53:53 PM PDT 24
Finished Apr 25 03:53:55 PM PDT 24
Peak memory 199264 kb
Host smart-761ee871-55a9-4abd-a12d-92d73d2cb713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653783760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1653783760
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.697299793
Short name T646
Test name
Test status
Simulation time 80632508 ps
CPU time 3.48 seconds
Started Apr 25 03:53:54 PM PDT 24
Finished Apr 25 03:53:58 PM PDT 24
Peak memory 199408 kb
Host smart-0255efb6-eca1-4db3-8c4e-879e68140b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697299793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.697299793
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1233745048
Short name T647
Test name
Test status
Simulation time 375407742 ps
CPU time 1.94 seconds
Started Apr 25 03:53:54 PM PDT 24
Finished Apr 25 03:53:57 PM PDT 24
Peak memory 199296 kb
Host smart-cadbc6a7-47fb-4e04-bcba-f66440b21b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233745048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1233745048
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2383406757
Short name T694
Test name
Test status
Simulation time 60750814 ps
CPU time 1.23 seconds
Started Apr 25 03:54:06 PM PDT 24
Finished Apr 25 03:54:07 PM PDT 24
Peak memory 199420 kb
Host smart-60194c5b-1cdd-419a-97e4-17bc08772deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383406757 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2383406757
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1639347830
Short name T712
Test name
Test status
Simulation time 34671620 ps
CPU time 1.11 seconds
Started Apr 25 03:54:06 PM PDT 24
Finished Apr 25 03:54:08 PM PDT 24
Peak memory 199132 kb
Host smart-090c13c4-c896-4c05-a2fc-c60a4c7324bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639347830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1639347830
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3246293315
Short name T609
Test name
Test status
Simulation time 21050277 ps
CPU time 0.57 seconds
Started Apr 25 03:53:57 PM PDT 24
Finished Apr 25 03:53:59 PM PDT 24
Peak memory 194064 kb
Host smart-af79dd02-7a1e-4cab-ad40-1022501a1074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246293315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3246293315
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.99684908
Short name T610
Test name
Test status
Simulation time 166421553 ps
CPU time 2.45 seconds
Started Apr 25 03:54:16 PM PDT 24
Finished Apr 25 03:54:20 PM PDT 24
Peak memory 199108 kb
Host smart-7b4ef45c-f894-45fc-9745-75f1aeedb35f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99684908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_o
utstanding.99684908
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1011019673
Short name T729
Test name
Test status
Simulation time 51652670 ps
CPU time 2.47 seconds
Started Apr 25 03:54:02 PM PDT 24
Finished Apr 25 03:54:06 PM PDT 24
Peak memory 199388 kb
Host smart-549e4e35-1d6d-4ac3-86a1-b5e074d44d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011019673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1011019673
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2665006378
Short name T110
Test name
Test status
Simulation time 362683586 ps
CPU time 1.76 seconds
Started Apr 25 03:53:59 PM PDT 24
Finished Apr 25 03:54:02 PM PDT 24
Peak memory 199320 kb
Host smart-2e5c319a-196c-47ee-8b3a-ec4690c99854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665006378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2665006378
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1091110379
Short name T210
Test name
Test status
Simulation time 20957050 ps
CPU time 0.57 seconds
Started Apr 25 01:03:35 PM PDT 24
Finished Apr 25 01:03:36 PM PDT 24
Peak memory 195288 kb
Host smart-33b18653-7627-4879-a22b-38398feaf49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091110379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1091110379
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3065934645
Short name T392
Test name
Test status
Simulation time 8939875534 ps
CPU time 64.69 seconds
Started Apr 25 01:03:17 PM PDT 24
Finished Apr 25 01:04:25 PM PDT 24
Peak memory 229412 kb
Host smart-1e3d02b1-98a4-409b-970e-57e1a38bd50a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065934645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3065934645
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2928442856
Short name T400
Test name
Test status
Simulation time 2962020819 ps
CPU time 45.7 seconds
Started Apr 25 01:03:31 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199636 kb
Host smart-0fd5906e-bf5a-485e-9d4c-095c011dc4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928442856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2928442856
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.947644695
Short name T425
Test name
Test status
Simulation time 2406434482 ps
CPU time 81.31 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 199736 kb
Host smart-9f76d901-1d33-4ddc-8fd0-58063f6204ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947644695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.947644695
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2091243635
Short name T418
Test name
Test status
Simulation time 10593559429 ps
CPU time 187.06 seconds
Started Apr 25 01:03:27 PM PDT 24
Finished Apr 25 01:06:35 PM PDT 24
Peak memory 199668 kb
Host smart-ad65bcce-74eb-4cdb-83d0-1154fb205eb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091243635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2091243635
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4118646424
Short name T567
Test name
Test status
Simulation time 10104389027 ps
CPU time 35.33 seconds
Started Apr 25 01:03:32 PM PDT 24
Finished Apr 25 01:04:08 PM PDT 24
Peak memory 199664 kb
Host smart-c48a9be7-151b-4f17-a29e-f3630b37f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118646424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4118646424
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1166057508
Short name T380
Test name
Test status
Simulation time 536915891 ps
CPU time 3.61 seconds
Started Apr 25 01:03:31 PM PDT 24
Finished Apr 25 01:03:35 PM PDT 24
Peak memory 199628 kb
Host smart-8b5eb753-e9fb-4d7f-b42c-644e238f4c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166057508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1166057508
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4086190901
Short name T30
Test name
Test status
Simulation time 24490977395 ps
CPU time 693.14 seconds
Started Apr 25 01:03:36 PM PDT 24
Finished Apr 25 01:15:10 PM PDT 24
Peak memory 247452 kb
Host smart-03980065-2db8-473a-836c-8985d51c6140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086190901 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4086190901
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1829679761
Short name T9
Test name
Test status
Simulation time 99440249350 ps
CPU time 524.58 seconds
Started Apr 25 01:03:27 PM PDT 24
Finished Apr 25 01:12:13 PM PDT 24
Peak memory 246076 kb
Host smart-6cd001d9-212c-4bed-bc4a-a71bee3cedf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829679761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1829679761
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2400459400
Short name T524
Test name
Test status
Simulation time 49791583 ps
CPU time 0.98 seconds
Started Apr 25 01:03:17 PM PDT 24
Finished Apr 25 01:03:21 PM PDT 24
Peak memory 199580 kb
Host smart-d6ec1e5b-be90-49ac-9fa2-963a08821b0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400459400 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2400459400
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.675036046
Short name T560
Test name
Test status
Simulation time 48061032168 ps
CPU time 344.05 seconds
Started Apr 25 01:03:18 PM PDT 24
Finished Apr 25 01:09:05 PM PDT 24
Peak memory 199200 kb
Host smart-ebf260c5-a762-4918-a2da-e82c8c456fd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675036046 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.675036046
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1916692871
Short name T277
Test name
Test status
Simulation time 35430837 ps
CPU time 0.66 seconds
Started Apr 25 01:03:36 PM PDT 24
Finished Apr 25 01:03:37 PM PDT 24
Peak memory 195780 kb
Host smart-11f2245c-a752-4b6a-8c35-681df57071a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916692871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1916692871
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3771451572
Short name T481
Test name
Test status
Simulation time 21581098 ps
CPU time 0.55 seconds
Started Apr 25 01:03:34 PM PDT 24
Finished Apr 25 01:03:35 PM PDT 24
Peak memory 194092 kb
Host smart-3671d286-fa0f-4a06-8996-496c876ed033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771451572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3771451572
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.657237005
Short name T398
Test name
Test status
Simulation time 1489751354 ps
CPU time 56.29 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:04:35 PM PDT 24
Peak memory 222388 kb
Host smart-015ca539-b023-473f-b990-9fb91fab5fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657237005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.657237005
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.362534447
Short name T332
Test name
Test status
Simulation time 990541071 ps
CPU time 12.4 seconds
Started Apr 25 01:03:35 PM PDT 24
Finished Apr 25 01:03:48 PM PDT 24
Peak memory 199580 kb
Host smart-8b070876-0c3c-478a-a595-3418142369f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362534447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.362534447
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1816378876
Short name T479
Test name
Test status
Simulation time 1420711990 ps
CPU time 82.33 seconds
Started Apr 25 01:03:39 PM PDT 24
Finished Apr 25 01:05:02 PM PDT 24
Peak memory 199628 kb
Host smart-a5211a35-e896-43b2-bcb6-1296279e2e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816378876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1816378876
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.136403211
Short name T305
Test name
Test status
Simulation time 12109640327 ps
CPU time 68.26 seconds
Started Apr 25 01:03:51 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199700 kb
Host smart-5888f83a-7b33-4922-9ac5-e7fff172c0e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136403211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.136403211
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.421249218
Short name T315
Test name
Test status
Simulation time 621125130 ps
CPU time 18.38 seconds
Started Apr 25 01:03:42 PM PDT 24
Finished Apr 25 01:04:02 PM PDT 24
Peak memory 199632 kb
Host smart-4bd3f163-b69f-42cd-a3c2-44b180e777f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421249218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.421249218
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.4069646696
Short name T248
Test name
Test status
Simulation time 807078909 ps
CPU time 4.32 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:03:38 PM PDT 24
Peak memory 199660 kb
Host smart-52407e64-55f7-4e23-8956-35d482f82ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069646696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4069646696
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.857941456
Short name T25
Test name
Test status
Simulation time 28503538424 ps
CPU time 98.07 seconds
Started Apr 25 01:03:19 PM PDT 24
Finished Apr 25 01:05:00 PM PDT 24
Peak memory 199748 kb
Host smart-5df5ac82-9a26-45cf-8028-92588e22e7b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857941456 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.857941456
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2416595045
Short name T422
Test name
Test status
Simulation time 114617010 ps
CPU time 1.19 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:03:46 PM PDT 24
Peak memory 199652 kb
Host smart-f33dfbe8-dd95-47b7-9dad-164d25cc50e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416595045 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2416595045
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1061651353
Short name T501
Test name
Test status
Simulation time 25319268843 ps
CPU time 457.79 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:11:23 PM PDT 24
Peak memory 199596 kb
Host smart-bfe03dbf-123a-49b1-b2fd-91f5b93e2eb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061651353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1061651353
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.9711247
Short name T461
Test name
Test status
Simulation time 1595570796 ps
CPU time 16.49 seconds
Started Apr 25 01:03:19 PM PDT 24
Finished Apr 25 01:03:38 PM PDT 24
Peak memory 199664 kb
Host smart-135a3e7f-8fde-4ed6-b5bb-8be5dd0c408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9711247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.9711247
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2442136806
Short name T586
Test name
Test status
Simulation time 27912214 ps
CPU time 0.58 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:09 PM PDT 24
Peak memory 195316 kb
Host smart-7e3ec8f2-eab5-4d1b-903e-53caf7fd5f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442136806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2442136806
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1746451931
Short name T467
Test name
Test status
Simulation time 3424278638 ps
CPU time 38 seconds
Started Apr 25 01:03:45 PM PDT 24
Finished Apr 25 01:04:24 PM PDT 24
Peak memory 232500 kb
Host smart-30cdca29-1088-42a1-abe8-d1de46235be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746451931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1746451931
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4107827204
Short name T265
Test name
Test status
Simulation time 1427262020 ps
CPU time 7.3 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:04:10 PM PDT 24
Peak memory 199600 kb
Host smart-54352279-72ee-4d63-8851-c7a96feca209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107827204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4107827204
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2409275216
Short name T439
Test name
Test status
Simulation time 4360812085 ps
CPU time 65.13 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:05:14 PM PDT 24
Peak memory 199748 kb
Host smart-7093f9cd-c815-4cd1-9d73-4850e2010586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409275216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2409275216
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1022112640
Short name T207
Test name
Test status
Simulation time 9298784744 ps
CPU time 125 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:06:11 PM PDT 24
Peak memory 199764 kb
Host smart-6c165372-c212-4f63-a8a7-94244cd700a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022112640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1022112640
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1920783264
Short name T544
Test name
Test status
Simulation time 16176991108 ps
CPU time 64.13 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:05:00 PM PDT 24
Peak memory 199744 kb
Host smart-93bcf269-1aef-4815-bd95-f691fafa26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920783264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1920783264
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.356185668
Short name T244
Test name
Test status
Simulation time 905449058 ps
CPU time 3.61 seconds
Started Apr 25 01:04:06 PM PDT 24
Finished Apr 25 01:04:11 PM PDT 24
Peak memory 199640 kb
Host smart-c42f4b78-417f-4a2a-9523-97ac8c2b29be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356185668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.356185668
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3412907923
Short name T564
Test name
Test status
Simulation time 138674432 ps
CPU time 1.01 seconds
Started Apr 25 01:03:47 PM PDT 24
Finished Apr 25 01:03:49 PM PDT 24
Peak memory 198796 kb
Host smart-bbfe0b79-9a97-499f-a838-bc805e869592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412907923 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3412907923
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.508292485
Short name T278
Test name
Test status
Simulation time 34244389023 ps
CPU time 435.75 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 199656 kb
Host smart-280bdc76-5d01-44a5-91a6-ea43234da02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508292485 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.508292485
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.59155971
Short name T167
Test name
Test status
Simulation time 6029969746 ps
CPU time 43.21 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199772 kb
Host smart-3f58251b-00a1-4afc-b586-e3874fede45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59155971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.59155971
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.2865642487
Short name T431
Test name
Test status
Simulation time 227434271936 ps
CPU time 2835.65 seconds
Started Apr 25 01:05:29 PM PDT 24
Finished Apr 25 01:52:46 PM PDT 24
Peak memory 257184 kb
Host smart-172f0893-0462-4b31-8180-14dd1c6cf62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865642487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.2865642487
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3497678573
Short name T22
Test name
Test status
Simulation time 12135079 ps
CPU time 0.6 seconds
Started Apr 25 01:03:49 PM PDT 24
Finished Apr 25 01:03:51 PM PDT 24
Peak memory 195344 kb
Host smart-538e43c3-fa9c-483f-939b-ec05b850728e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497678573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3497678573
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1477814164
Short name T173
Test name
Test status
Simulation time 1894549875 ps
CPU time 17.46 seconds
Started Apr 25 01:03:58 PM PDT 24
Finished Apr 25 01:04:17 PM PDT 24
Peak memory 207880 kb
Host smart-4cf98c7f-cbf7-416c-ba9d-2c3b488f2e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477814164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1477814164
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3161164998
Short name T345
Test name
Test status
Simulation time 279040920 ps
CPU time 6.28 seconds
Started Apr 25 01:03:45 PM PDT 24
Finished Apr 25 01:03:52 PM PDT 24
Peak memory 199532 kb
Host smart-f111d77a-7199-4d63-bbd6-1eb38051c886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161164998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3161164998
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.252584986
Short name T539
Test name
Test status
Simulation time 6281248400 ps
CPU time 91.07 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:05:36 PM PDT 24
Peak memory 199692 kb
Host smart-63eaaebb-3b7a-427e-bb78-98a03bd9cf4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252584986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.252584986
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2320288494
Short name T476
Test name
Test status
Simulation time 974885540 ps
CPU time 51.39 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:04:46 PM PDT 24
Peak memory 199676 kb
Host smart-c41ea157-1730-4800-87b0-446bfd1c12d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320288494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2320288494
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1794917398
Short name T493
Test name
Test status
Simulation time 6756619627 ps
CPU time 89.66 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:05:38 PM PDT 24
Peak memory 199716 kb
Host smart-6950e56c-703a-4b81-acba-cd53c02e89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794917398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1794917398
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1112272877
Short name T403
Test name
Test status
Simulation time 141470844 ps
CPU time 0.95 seconds
Started Apr 25 01:03:46 PM PDT 24
Finished Apr 25 01:03:48 PM PDT 24
Peak memory 198408 kb
Host smart-c0e887be-49ed-4a93-82bb-6b9a78354bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112272877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1112272877
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2671192933
Short name T46
Test name
Test status
Simulation time 340060074652 ps
CPU time 2249.09 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:41:19 PM PDT 24
Peak memory 237072 kb
Host smart-d4e5b9b8-ad63-40ed-b556-e76fba66887e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671192933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2671192933
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2031766224
Short name T142
Test name
Test status
Simulation time 56504017 ps
CPU time 1.23 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 199488 kb
Host smart-0ab32cf3-12f7-4e99-a3a5-26e53dbebdcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031766224 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2031766224
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3343854285
Short name T352
Test name
Test status
Simulation time 38938101920 ps
CPU time 510.11 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 199668 kb
Host smart-09996917-f482-4dd8-9a26-67b417946c3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343854285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3343854285
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2538161452
Short name T279
Test name
Test status
Simulation time 2302655708 ps
CPU time 83.55 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:05:21 PM PDT 24
Peak memory 199692 kb
Host smart-f61160a5-b269-4b48-8a1d-9ed7f8eb8609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538161452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2538161452
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.1992317135
Short name T10
Test name
Test status
Simulation time 56784527734 ps
CPU time 834.69 seconds
Started Apr 25 01:05:20 PM PDT 24
Finished Apr 25 01:19:15 PM PDT 24
Peak memory 248660 kb
Host smart-8133fa82-ea2f-4191-a530-81056f5cd098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992317135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.1992317135
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.534066529
Short name T379
Test name
Test status
Simulation time 15282718 ps
CPU time 0.61 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:03:55 PM PDT 24
Peak memory 195336 kb
Host smart-4598c394-9817-4278-929e-f57acae471a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534066529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.534066529
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2319380440
Short name T569
Test name
Test status
Simulation time 2007619321 ps
CPU time 35.24 seconds
Started Apr 25 01:03:47 PM PDT 24
Finished Apr 25 01:04:24 PM PDT 24
Peak memory 225612 kb
Host smart-be1efce7-2437-47a6-931e-b1a8ff12412b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319380440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2319380440
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2718711432
Short name T366
Test name
Test status
Simulation time 25524718052 ps
CPU time 38.39 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:04:28 PM PDT 24
Peak memory 199716 kb
Host smart-996a2b59-4570-4775-9a80-210a0c707548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718711432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2718711432
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3070958016
Short name T155
Test name
Test status
Simulation time 4543115643 ps
CPU time 68.39 seconds
Started Apr 25 01:03:51 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199760 kb
Host smart-2b8608db-4868-4902-80ef-c2eec767f2f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070958016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3070958016
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3887145719
Short name T592
Test name
Test status
Simulation time 1932755159 ps
CPU time 108.26 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:05:43 PM PDT 24
Peak memory 199672 kb
Host smart-4b920659-e4b3-4268-b7e6-28c8f9c2cae3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887145719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3887145719
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4198992778
Short name T320
Test name
Test status
Simulation time 1553104029 ps
CPU time 31.02 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:04:15 PM PDT 24
Peak memory 199708 kb
Host smart-42559c52-2ff9-4a3a-8a5f-ffaaa1de8838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198992778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4198992778
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3658364690
Short name T166
Test name
Test status
Simulation time 310161748 ps
CPU time 4.71 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:04:15 PM PDT 24
Peak memory 199648 kb
Host smart-53828f06-d268-457a-8382-ef9d449dee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658364690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3658364690
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3305730386
Short name T300
Test name
Test status
Simulation time 24807355728 ps
CPU time 458.87 seconds
Started Apr 25 01:03:58 PM PDT 24
Finished Apr 25 01:11:38 PM PDT 24
Peak memory 199728 kb
Host smart-0ed125c6-d1b5-4eae-a9c9-d14a21a0cc1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305730386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3305730386
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2623327232
Short name T535
Test name
Test status
Simulation time 8672656318 ps
CPU time 480.02 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:11:50 PM PDT 24
Peak memory 199628 kb
Host smart-5aa936b2-0d70-4770-bbb4-1fa32689f075
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623327232 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2623327232
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.718726341
Short name T219
Test name
Test status
Simulation time 403863740 ps
CPU time 14.58 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:06 PM PDT 24
Peak memory 199524 kb
Host smart-3ecfa66f-88a4-4587-aa36-dda5c89a6cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718726341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.718726341
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2003916733
Short name T67
Test name
Test status
Simulation time 25260134773 ps
CPU time 668.57 seconds
Started Apr 25 01:05:16 PM PDT 24
Finished Apr 25 01:16:27 PM PDT 24
Peak memory 232412 kb
Host smart-c7cd7916-b93a-4dec-b112-df9a0dddbfa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003916733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.2003916733
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2656582616
Short name T506
Test name
Test status
Simulation time 16434852 ps
CPU time 0.62 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:03:52 PM PDT 24
Peak memory 195472 kb
Host smart-2be49009-7b13-41b8-bd94-8e849a56631e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656582616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2656582616
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1219638491
Short name T424
Test name
Test status
Simulation time 1465466499 ps
CPU time 60.08 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:05:13 PM PDT 24
Peak memory 240312 kb
Host smart-115fc0f5-8ada-40bd-9b4b-8df58d59d63c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219638491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1219638491
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2123233472
Short name T347
Test name
Test status
Simulation time 3130666939 ps
CPU time 24.62 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 199700 kb
Host smart-7b33d4c0-4e91-48af-97cb-79a1affdbec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123233472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2123233472
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1656055808
Short name T182
Test name
Test status
Simulation time 1582466563 ps
CPU time 85.21 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:05:29 PM PDT 24
Peak memory 199604 kb
Host smart-fc4d9c7d-c03e-41f5-9ed9-a5cb671cd1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656055808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1656055808
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.897428515
Short name T325
Test name
Test status
Simulation time 11648921516 ps
CPU time 23.57 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:20 PM PDT 24
Peak memory 199728 kb
Host smart-970dfc5b-550a-453c-b6dd-8d5c6831fff7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897428515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.897428515
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1531777027
Short name T521
Test name
Test status
Simulation time 9203019986 ps
CPU time 31.59 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:23 PM PDT 24
Peak memory 199564 kb
Host smart-122a7f35-5190-42aa-9c0e-b2a030673f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531777027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1531777027
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3682548833
Short name T331
Test name
Test status
Simulation time 2421417518 ps
CPU time 7.19 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:04:15 PM PDT 24
Peak memory 199716 kb
Host smart-4436b7a4-5105-4282-a6ab-a044edc65b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682548833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3682548833
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3576395602
Short name T348
Test name
Test status
Simulation time 14926039231 ps
CPU time 187.86 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:07:05 PM PDT 24
Peak memory 216136 kb
Host smart-86a7baca-0bc4-4d76-b97d-a8dff1c405b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576395602 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3576395602
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3227311050
Short name T491
Test name
Test status
Simulation time 94924276 ps
CPU time 1.06 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:03:50 PM PDT 24
Peak memory 199504 kb
Host smart-be2f03a8-9889-4cf7-bd6e-ca29facf465a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227311050 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3227311050
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.101421668
Short name T81
Test name
Test status
Simulation time 13671824796 ps
CPU time 408.53 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:10:42 PM PDT 24
Peak memory 199724 kb
Host smart-e013c6ac-3114-477a-bd9b-1f79da57493e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101421668 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.101421668
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1773906334
Short name T533
Test name
Test status
Simulation time 2814420367 ps
CPU time 27.11 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:04:35 PM PDT 24
Peak memory 199744 kb
Host smart-0c6113e7-dc4b-465e-a16f-71f6835b78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773906334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1773906334
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.2020136442
Short name T64
Test name
Test status
Simulation time 24059437059 ps
CPU time 1267.56 seconds
Started Apr 25 01:05:16 PM PDT 24
Finished Apr 25 01:26:25 PM PDT 24
Peak memory 215240 kb
Host smart-9bc7f5d5-5cb2-42fb-9d76-bcb3e7ea91b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020136442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.2020136442
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2027637298
Short name T274
Test name
Test status
Simulation time 56190499 ps
CPU time 0.64 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 195364 kb
Host smart-172bd274-c822-4ed6-b02c-f523e71e01c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027637298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2027637298
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3753990407
Short name T214
Test name
Test status
Simulation time 18602943010 ps
CPU time 35.88 seconds
Started Apr 25 01:04:01 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 223396 kb
Host smart-a78b2bce-cad0-4e98-baf1-bf2e10a2afce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753990407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3753990407
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1280853025
Short name T303
Test name
Test status
Simulation time 2667980231 ps
CPU time 47.08 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:04:41 PM PDT 24
Peak memory 199740 kb
Host smart-451ae1f5-eb14-4a05-8140-6caa7e290150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280853025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1280853025
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4089757360
Short name T153
Test name
Test status
Simulation time 1875712831 ps
CPU time 26.85 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199532 kb
Host smart-34f32920-e668-41df-a64f-cc9c5fb93436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089757360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4089757360
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1565883804
Short name T396
Test name
Test status
Simulation time 12140072039 ps
CPU time 142.16 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:06:41 PM PDT 24
Peak memory 199628 kb
Host smart-2fc4dad3-628f-4bc8-b362-a78659ee99f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565883804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1565883804
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1104324696
Short name T410
Test name
Test status
Simulation time 4317223098 ps
CPU time 66.08 seconds
Started Apr 25 01:03:59 PM PDT 24
Finished Apr 25 01:05:06 PM PDT 24
Peak memory 199640 kb
Host smart-0ec7384d-6e23-419b-b100-47285a78fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104324696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1104324696
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2854575262
Short name T518
Test name
Test status
Simulation time 279436886 ps
CPU time 2.68 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 199620 kb
Host smart-39e6baf7-f464-4646-839d-7f45b46d6804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854575262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2854575262
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.828141513
Short name T511
Test name
Test status
Simulation time 374502398963 ps
CPU time 1077.77 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:21:52 PM PDT 24
Peak memory 216108 kb
Host smart-849c7f79-0646-4c22-899b-27a157279745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828141513 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.828141513
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.551789551
Short name T196
Test name
Test status
Simulation time 192542575 ps
CPU time 1.26 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:05 PM PDT 24
Peak memory 199596 kb
Host smart-9648c64b-1afe-4346-bd71-d8202c9fa50c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551789551 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.551789551
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2472396739
Short name T288
Test name
Test status
Simulation time 41168159365 ps
CPU time 507 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:12:23 PM PDT 24
Peak memory 199664 kb
Host smart-b337598b-e935-4ad1-9afd-6545ecc417c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472396739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2472396739
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.990944130
Short name T250
Test name
Test status
Simulation time 5566005683 ps
CPU time 68.12 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:05:18 PM PDT 24
Peak memory 199656 kb
Host smart-2db517bb-aad5-4eac-a211-41737a4253a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990944130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.990944130
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.385385691
Short name T251
Test name
Test status
Simulation time 16502635 ps
CPU time 0.62 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 195392 kb
Host smart-45557bbd-a6fa-4ee7-a581-361c3539b92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385385691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.385385691
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2930633921
Short name T542
Test name
Test status
Simulation time 1483507779 ps
CPU time 56.8 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:05:15 PM PDT 24
Peak memory 225328 kb
Host smart-5d4f2783-81b2-437a-9bca-aed310ee5980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930633921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2930633921
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1507071740
Short name T485
Test name
Test status
Simulation time 897293846 ps
CPU time 19.05 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199628 kb
Host smart-fbc3044d-167a-41f2-b447-c7eef2568bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507071740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1507071740
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4172018906
Short name T514
Test name
Test status
Simulation time 691562619 ps
CPU time 19.51 seconds
Started Apr 25 01:03:58 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199672 kb
Host smart-2511e370-d153-4de1-a783-1c49310fb316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172018906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4172018906
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3356698422
Short name T502
Test name
Test status
Simulation time 27420306737 ps
CPU time 175.19 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:06:54 PM PDT 24
Peak memory 199724 kb
Host smart-9adcbffe-e4d3-4525-ba9d-00e2879bbe2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356698422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3356698422
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2931739068
Short name T4
Test name
Test status
Simulation time 4208168449 ps
CPU time 60.34 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:56 PM PDT 24
Peak memory 199752 kb
Host smart-57aebb4b-91ca-40e0-8550-23a74dfb4afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931739068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2931739068
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3651643207
Short name T42
Test name
Test status
Simulation time 1259913630 ps
CPU time 3.33 seconds
Started Apr 25 01:03:54 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 199668 kb
Host smart-1e2e8eed-b409-4e37-9c17-a3f8bc26e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651643207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3651643207
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2931722609
Short name T51
Test name
Test status
Simulation time 11489093225 ps
CPU time 20.54 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:04:30 PM PDT 24
Peak memory 240724 kb
Host smart-ea2d09e1-58f3-4605-bf1a-e426bd77a9d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931722609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2931722609
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1546984960
Short name T344
Test name
Test status
Simulation time 104246661 ps
CPU time 1.11 seconds
Started Apr 25 01:03:58 PM PDT 24
Finished Apr 25 01:04:00 PM PDT 24
Peak memory 198892 kb
Host smart-06768560-1cf8-4994-b73c-9cd572a61030
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546984960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1546984960
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.897370519
Short name T5
Test name
Test status
Simulation time 37730537952 ps
CPU time 531.14 seconds
Started Apr 25 01:04:21 PM PDT 24
Finished Apr 25 01:13:13 PM PDT 24
Peak memory 199692 kb
Host smart-cbfdaab9-4a66-4a9d-97fe-13b3f97499cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897370519 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.897370519
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1382551134
Short name T283
Test name
Test status
Simulation time 2676778092 ps
CPU time 22.89 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 199496 kb
Host smart-471e9ce0-fd62-46f6-9faf-a93f80e80d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382551134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1382551134
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.423601733
Short name T376
Test name
Test status
Simulation time 10693656 ps
CPU time 0.58 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 194316 kb
Host smart-6a3e3851-9d29-420c-8b36-f4ac6fd58ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423601733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.423601733
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2305616635
Short name T435
Test name
Test status
Simulation time 1559698456 ps
CPU time 58.96 seconds
Started Apr 25 01:04:05 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 240648 kb
Host smart-1d85a29b-ddf6-4e7e-a770-ab9613cfdfbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305616635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2305616635
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2368316096
Short name T441
Test name
Test status
Simulation time 5180962282 ps
CPU time 11.58 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:29 PM PDT 24
Peak memory 199688 kb
Host smart-45f70793-5ece-46c0-9a72-1798e3bbca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368316096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2368316096
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3867033379
Short name T548
Test name
Test status
Simulation time 589652022 ps
CPU time 35.08 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 199668 kb
Host smart-a2e13dda-3825-4d28-afc7-d9ff524b6baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867033379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3867033379
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2245529282
Short name T291
Test name
Test status
Simulation time 52960144722 ps
CPU time 157.73 seconds
Started Apr 25 01:04:06 PM PDT 24
Finished Apr 25 01:06:45 PM PDT 24
Peak memory 199660 kb
Host smart-011a1de1-06d0-4b27-a99b-16e39c52024b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245529282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2245529282
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2608754526
Short name T101
Test name
Test status
Simulation time 18453185341 ps
CPU time 88.9 seconds
Started Apr 25 01:03:58 PM PDT 24
Finished Apr 25 01:05:28 PM PDT 24
Peak memory 199692 kb
Host smart-27c7f648-838c-45b8-8454-5a2692bb3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608754526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2608754526
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.935884513
Short name T583
Test name
Test status
Simulation time 291280586 ps
CPU time 4.58 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:04:14 PM PDT 24
Peak memory 199656 kb
Host smart-e6e822d5-e85f-4a58-b1bc-e07102635b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935884513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.935884513
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4229802458
Short name T355
Test name
Test status
Simulation time 231658121501 ps
CPU time 2878.31 seconds
Started Apr 25 01:04:06 PM PDT 24
Finished Apr 25 01:52:06 PM PDT 24
Peak memory 224340 kb
Host smart-82f04739-10de-4d43-b524-6007700f1b1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229802458 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4229802458
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1548706847
Short name T164
Test name
Test status
Simulation time 108390962 ps
CPU time 0.95 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:03:54 PM PDT 24
Peak memory 198260 kb
Host smart-8cc1f972-933f-4710-ac14-866d3aad0473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548706847 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1548706847
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1897801892
Short name T452
Test name
Test status
Simulation time 43457142685 ps
CPU time 549.88 seconds
Started Apr 25 01:04:00 PM PDT 24
Finished Apr 25 01:13:10 PM PDT 24
Peak memory 199664 kb
Host smart-4df6333f-7f94-476b-9884-3267e5de4ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897801892 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1897801892
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.207058633
Short name T40
Test name
Test status
Simulation time 10442778993 ps
CPU time 44.55 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:58 PM PDT 24
Peak memory 199720 kb
Host smart-fa69261a-8759-4b45-80b6-6f8eaee98ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207058633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.207058633
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.3041639167
Short name T49
Test name
Test status
Simulation time 13925111261 ps
CPU time 683.49 seconds
Started Apr 25 01:05:32 PM PDT 24
Finished Apr 25 01:16:57 PM PDT 24
Peak memory 232488 kb
Host smart-7d49a370-1a86-423e-a52d-1dddbb82195e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041639167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.3041639167
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.209804192
Short name T483
Test name
Test status
Simulation time 69172064 ps
CPU time 0.6 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:09 PM PDT 24
Peak memory 195260 kb
Host smart-f970a919-c3a3-4740-8442-aad44e80a8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209804192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.209804192
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4183945433
Short name T430
Test name
Test status
Simulation time 1697426452 ps
CPU time 67.03 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:05:18 PM PDT 24
Peak memory 232480 kb
Host smart-3d174dff-95ab-4deb-8aac-ec160aa8c825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183945433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4183945433
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1757715784
Short name T236
Test name
Test status
Simulation time 8052466488 ps
CPU time 41.16 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199736 kb
Host smart-3fc5b3a9-7fca-475a-a03f-115a2ebbe67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757715784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1757715784
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.687740735
Short name T428
Test name
Test status
Simulation time 3820309064 ps
CPU time 55.34 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 199744 kb
Host smart-215ce509-5f8d-4d0b-93f5-5598c89a654c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687740735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.687740735
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1720000144
Short name T598
Test name
Test status
Simulation time 9972809518 ps
CPU time 146.92 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:06:38 PM PDT 24
Peak memory 199684 kb
Host smart-992cc287-0c69-4639-8ae7-b1cf7c653aaa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720000144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1720000144
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4224513338
Short name T334
Test name
Test status
Simulation time 27886162587 ps
CPU time 100.22 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:05:58 PM PDT 24
Peak memory 199716 kb
Host smart-45c381a0-877a-4555-aa93-eabb66c57504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224513338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4224513338
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1742187812
Short name T498
Test name
Test status
Simulation time 2143013256 ps
CPU time 6.72 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199664 kb
Host smart-c789bf5f-6fc1-421a-9e91-4610ff6722b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742187812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1742187812
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2036935635
Short name T402
Test name
Test status
Simulation time 130252609830 ps
CPU time 1166.96 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:23:38 PM PDT 24
Peak memory 199768 kb
Host smart-ecbd9492-65dd-420c-a435-660603561505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036935635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2036935635
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.662291954
Short name T131
Test name
Test status
Simulation time 40907486 ps
CPU time 1.04 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:11 PM PDT 24
Peak memory 198352 kb
Host smart-21fd967e-c3da-4421-930c-2e725d1fb652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662291954 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.662291954
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3267429869
Short name T83
Test name
Test status
Simulation time 26420866198 ps
CPU time 420 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:11:14 PM PDT 24
Peak memory 199684 kb
Host smart-68b83038-e9e0-458d-a3dd-96d7bf952106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267429869 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3267429869
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1055642996
Short name T297
Test name
Test status
Simulation time 193278419 ps
CPU time 10.24 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:04:07 PM PDT 24
Peak memory 199680 kb
Host smart-8f1135b0-0cc8-47d1-9f56-7a67037fbc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055642996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1055642996
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.1766463809
Short name T65
Test name
Test status
Simulation time 61465479477 ps
CPU time 189.01 seconds
Started Apr 25 01:05:29 PM PDT 24
Finished Apr 25 01:08:40 PM PDT 24
Peak memory 207980 kb
Host smart-6fe9008d-856d-4354-b795-0099b08160c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766463809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.1766463809
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3009866511
Short name T280
Test name
Test status
Simulation time 20498196 ps
CPU time 0.55 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:14 PM PDT 24
Peak memory 195188 kb
Host smart-de5c6b5d-faea-4acf-8756-4f1a98ec36d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009866511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3009866511
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1762856069
Short name T423
Test name
Test status
Simulation time 6329511872 ps
CPU time 44.23 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:04:38 PM PDT 24
Peak memory 215320 kb
Host smart-8ae66259-4528-4828-8a8f-11852edc5e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762856069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1762856069
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2676950129
Short name T389
Test name
Test status
Simulation time 2201931589 ps
CPU time 27.71 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:24 PM PDT 24
Peak memory 199744 kb
Host smart-d824a2a7-0e3b-455d-9e2c-a6ba0e472e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676950129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2676950129
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1902867170
Short name T478
Test name
Test status
Simulation time 746613288 ps
CPU time 40.6 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:04:38 PM PDT 24
Peak memory 199656 kb
Host smart-6406244d-6712-422c-a1b8-8b5b72f72c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902867170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1902867170
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3913439349
Short name T445
Test name
Test status
Simulation time 2489412757 ps
CPU time 38.93 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199692 kb
Host smart-49eac2bc-28bf-4f67-9219-b50910ef7ae5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913439349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3913439349
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4282463463
Short name T206
Test name
Test status
Simulation time 523361399 ps
CPU time 11.09 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:04:30 PM PDT 24
Peak memory 199664 kb
Host smart-2373dc53-93ec-4b81-9283-a83d69726a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282463463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4282463463
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1680534953
Short name T407
Test name
Test status
Simulation time 244013588 ps
CPU time 3.59 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:04:00 PM PDT 24
Peak memory 199680 kb
Host smart-0c0020ad-b8f3-4eae-9186-b1971efdca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680534953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1680534953
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1100441972
Short name T195
Test name
Test status
Simulation time 8126896476 ps
CPU time 486.34 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:12:02 PM PDT 24
Peak memory 199748 kb
Host smart-0c8a2897-0c14-46e1-9164-d076504148c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100441972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1100441972
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2538739847
Short name T318
Test name
Test status
Simulation time 52294120 ps
CPU time 1.09 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:03:58 PM PDT 24
Peak memory 199196 kb
Host smart-13ae1546-47e3-41f5-9dbf-d82363f94a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538739847 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2538739847
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.4135083972
Short name T508
Test name
Test status
Simulation time 26296825195 ps
CPU time 489.18 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:12:07 PM PDT 24
Peak memory 199664 kb
Host smart-ed7aed30-c40c-4064-977b-72780e0754ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135083972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.4135083972
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1523731266
Short name T486
Test name
Test status
Simulation time 4680513053 ps
CPU time 47.47 seconds
Started Apr 25 01:04:06 PM PDT 24
Finished Apr 25 01:04:54 PM PDT 24
Peak memory 199716 kb
Host smart-06bb9c3d-bff2-45c0-9ecb-e38dadfd0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523731266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1523731266
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.4171368781
Short name T11
Test name
Test status
Simulation time 197390173725 ps
CPU time 3218.97 seconds
Started Apr 25 01:05:34 PM PDT 24
Finished Apr 25 01:59:14 PM PDT 24
Peak memory 265188 kb
Host smart-f995cd80-8a93-4cbc-9647-e7c0a6c1dbea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171368781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.4171368781
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.79211527
Short name T579
Test name
Test status
Simulation time 23706931 ps
CPU time 0.6 seconds
Started Apr 25 01:04:05 PM PDT 24
Finished Apr 25 01:04:06 PM PDT 24
Peak memory 195184 kb
Host smart-910093f0-e842-4190-9e23-180449b6ea4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79211527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.79211527
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3721802387
Short name T449
Test name
Test status
Simulation time 4269102516 ps
CPU time 38.43 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:43 PM PDT 24
Peak memory 215280 kb
Host smart-f5007643-4e91-428d-ae0d-1c1db8411b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721802387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3721802387
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2642792117
Short name T582
Test name
Test status
Simulation time 4258790928 ps
CPU time 43.43 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 199696 kb
Host smart-e265cf86-dafe-4cd6-a9fe-fa5f733fb85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642792117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2642792117
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2037048326
Short name T184
Test name
Test status
Simulation time 2103002251 ps
CPU time 117.83 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:06:00 PM PDT 24
Peak memory 199660 kb
Host smart-8566ec38-df32-45db-91ac-13a7273ff018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037048326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2037048326
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2656829457
Short name T146
Test name
Test status
Simulation time 15197223805 ps
CPU time 56.32 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:05:08 PM PDT 24
Peak memory 199660 kb
Host smart-0f222814-9d5d-4d4a-8870-6e8b878f12dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656829457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2656829457
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1849148596
Short name T200
Test name
Test status
Simulation time 7210932161 ps
CPU time 98.01 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:05:48 PM PDT 24
Peak memory 199740 kb
Host smart-89a24fb4-f34b-4974-b945-b47cd7a53b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849148596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1849148596
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.462840430
Short name T562
Test name
Test status
Simulation time 689639722 ps
CPU time 4.83 seconds
Started Apr 25 01:04:12 PM PDT 24
Finished Apr 25 01:04:20 PM PDT 24
Peak memory 199600 kb
Host smart-53b73676-53ff-4556-9115-4b0b480942c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462840430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.462840430
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1599321546
Short name T254
Test name
Test status
Simulation time 4321435591 ps
CPU time 50.69 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 199696 kb
Host smart-30db7b37-b563-412e-809a-2f190d5c4ee5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599321546 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1599321546
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.832920815
Short name T438
Test name
Test status
Simulation time 208022394 ps
CPU time 1.31 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:05 PM PDT 24
Peak memory 199300 kb
Host smart-977145d6-a753-451b-9151-b6a57149d4ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832920815 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.832920815
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1567210095
Short name T470
Test name
Test status
Simulation time 316695892507 ps
CPU time 467.56 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:11:56 PM PDT 24
Peak memory 199664 kb
Host smart-5d844db3-dfcd-4f6d-8b13-c678908a631d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567210095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1567210095
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2592607304
Short name T593
Test name
Test status
Simulation time 5685776049 ps
CPU time 76.45 seconds
Started Apr 25 01:04:01 PM PDT 24
Finished Apr 25 01:05:18 PM PDT 24
Peak memory 199716 kb
Host smart-94a1eb4c-7741-45da-9674-9a7e2fa965a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592607304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2592607304
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2000956975
Short name T23
Test name
Test status
Simulation time 36016747 ps
CPU time 0.56 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:03:38 PM PDT 24
Peak memory 194312 kb
Host smart-baec03ae-bb15-4b08-85bc-aefce7ead5f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000956975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2000956975
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3243130591
Short name T395
Test name
Test status
Simulation time 3489635238 ps
CPU time 22.9 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:04:02 PM PDT 24
Peak memory 207908 kb
Host smart-0ef7c85f-d7b2-4f63-aab3-8e3306ca1f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243130591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3243130591
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2074499258
Short name T281
Test name
Test status
Simulation time 5035631046 ps
CPU time 36.03 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:28 PM PDT 24
Peak memory 199740 kb
Host smart-f7ceaace-586a-41b1-b09d-ed9f6fe70633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074499258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2074499258
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2634822264
Short name T158
Test name
Test status
Simulation time 2551576337 ps
CPU time 99.27 seconds
Started Apr 25 01:03:41 PM PDT 24
Finished Apr 25 01:05:21 PM PDT 24
Peak memory 199728 kb
Host smart-a21a4d38-a9cc-42e4-9b3e-a09f05e0d7a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634822264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2634822264
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4064386520
Short name T135
Test name
Test status
Simulation time 27464235 ps
CPU time 0.75 seconds
Started Apr 25 01:03:45 PM PDT 24
Finished Apr 25 01:03:46 PM PDT 24
Peak memory 196948 kb
Host smart-ab155b68-1a83-48ba-8b02-c8a5cac8b138
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064386520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4064386520
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.774231532
Short name T474
Test name
Test status
Simulation time 7094550591 ps
CPU time 70.77 seconds
Started Apr 25 01:03:29 PM PDT 24
Finished Apr 25 01:04:41 PM PDT 24
Peak memory 199700 kb
Host smart-432dd987-41bd-4376-acce-571f28d1bfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774231532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.774231532
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1888477849
Short name T35
Test name
Test status
Simulation time 126866573 ps
CPU time 0.81 seconds
Started Apr 25 01:03:20 PM PDT 24
Finished Apr 25 01:03:22 PM PDT 24
Peak memory 218088 kb
Host smart-fefd35f6-4e19-4c84-bb64-07e4bf69f0eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888477849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1888477849
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4184165221
Short name T229
Test name
Test status
Simulation time 1328684490 ps
CPU time 4.11 seconds
Started Apr 25 01:03:47 PM PDT 24
Finished Apr 25 01:03:53 PM PDT 24
Peak memory 199632 kb
Host smart-1e3ee288-a255-4442-9312-ffb719708e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184165221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4184165221
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.133285049
Short name T551
Test name
Test status
Simulation time 24292446878 ps
CPU time 269.32 seconds
Started Apr 25 01:03:27 PM PDT 24
Finished Apr 25 01:07:56 PM PDT 24
Peak memory 235292 kb
Host smart-8a1a245b-a111-4417-bc87-81de82f6aa38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133285049 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.133285049
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1346957937
Short name T218
Test name
Test status
Simulation time 61417870 ps
CPU time 1.18 seconds
Started Apr 25 01:03:35 PM PDT 24
Finished Apr 25 01:03:37 PM PDT 24
Peak memory 199676 kb
Host smart-c5fb2e22-bd26-49be-a933-c5d782ea9988
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346957937 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1346957937
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2954157700
Short name T489
Test name
Test status
Simulation time 25018296011 ps
CPU time 475.38 seconds
Started Apr 25 01:03:20 PM PDT 24
Finished Apr 25 01:11:17 PM PDT 24
Peak memory 199656 kb
Host smart-40d4b68a-189f-4286-a556-fdf758129cad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954157700 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2954157700
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4184302477
Short name T307
Test name
Test status
Simulation time 4666423929 ps
CPU time 91.16 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:05:26 PM PDT 24
Peak memory 199728 kb
Host smart-f9185c7d-0a7c-4fe2-8d0c-edbe2fcac6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184302477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4184302477
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.870316656
Short name T465
Test name
Test status
Simulation time 36705629 ps
CPU time 0.58 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:05 PM PDT 24
Peak memory 195348 kb
Host smart-c2c847cd-9ee9-4865-ba00-ad65119dafd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870316656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.870316656
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2498164643
Short name T553
Test name
Test status
Simulation time 586101776 ps
CPU time 15.85 seconds
Started Apr 25 01:04:01 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 207856 kb
Host smart-3b6beb5f-17ca-4024-8840-0115bedf29be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498164643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2498164643
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1914013684
Short name T401
Test name
Test status
Simulation time 7495076040 ps
CPU time 60.57 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:05:03 PM PDT 24
Peak memory 199708 kb
Host smart-b39ca850-0b6c-49e7-9fdd-7632bd91682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914013684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1914013684
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.945018299
Short name T132
Test name
Test status
Simulation time 1254332370 ps
CPU time 63.9 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 199692 kb
Host smart-39aa7fdc-1a44-4563-ab5a-13d62895b0ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945018299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.945018299
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3908941913
Short name T588
Test name
Test status
Simulation time 1308800459 ps
CPU time 38.07 seconds
Started Apr 25 01:04:06 PM PDT 24
Finished Apr 25 01:04:45 PM PDT 24
Peak memory 199664 kb
Host smart-af27f576-c9bd-4520-b494-e0946054fe3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908941913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3908941913
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2167403204
Short name T175
Test name
Test status
Simulation time 29323811191 ps
CPU time 61.78 seconds
Started Apr 25 01:04:05 PM PDT 24
Finished Apr 25 01:05:08 PM PDT 24
Peak memory 199756 kb
Host smart-b4c4fad3-c4d1-4ca9-b57a-af48ae111c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167403204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2167403204
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3352439576
Short name T391
Test name
Test status
Simulation time 189018913 ps
CPU time 3.27 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:04:08 PM PDT 24
Peak memory 199688 kb
Host smart-a10fbe2a-2ccc-42f9-8829-16d8f6255504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352439576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3352439576
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1300029110
Short name T558
Test name
Test status
Simulation time 3640123971 ps
CPU time 72.45 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 215492 kb
Host smart-07d2c299-7225-4969-a4ed-b17ffd0731c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300029110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1300029110
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.68422812
Short name T324
Test name
Test status
Simulation time 102907769 ps
CPU time 1.1 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:15 PM PDT 24
Peak memory 199508 kb
Host smart-85cb1bd2-7059-48fc-8acd-1701f280574a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68422812 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.hmac_test_hmac_vectors.68422812
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.441016902
Short name T143
Test name
Test status
Simulation time 30091444233 ps
CPU time 428.17 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 199596 kb
Host smart-4abb3946-1255-4202-ad95-07a2118ff0b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441016902 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.441016902
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4149568001
Short name T157
Test name
Test status
Simulation time 4066259924 ps
CPU time 40.33 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:50 PM PDT 24
Peak memory 199740 kb
Host smart-eb6385b0-3377-4d78-afaa-75b1ba1ae1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149568001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4149568001
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.913399274
Short name T286
Test name
Test status
Simulation time 14070808 ps
CPU time 0.58 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:04:08 PM PDT 24
Peak memory 194300 kb
Host smart-f95c78c0-f26b-4c08-80e1-89cfe80ef6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913399274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.913399274
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3506415830
Short name T399
Test name
Test status
Simulation time 5886339886 ps
CPU time 46.46 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 209968 kb
Host smart-9fe72ff9-97cd-4a30-be06-f3be16985254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506415830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3506415830
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1282685377
Short name T589
Test name
Test status
Simulation time 1550193109 ps
CPU time 4.83 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:04:20 PM PDT 24
Peak memory 199644 kb
Host smart-6b59453a-5430-4bce-b0e8-d142299fc7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282685377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1282685377
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1369556155
Short name T129
Test name
Test status
Simulation time 2078496474 ps
CPU time 116.52 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:06:09 PM PDT 24
Peak memory 199672 kb
Host smart-a4a50ae2-956e-4682-9b70-f39b57a88967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369556155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1369556155
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3173011300
Short name T15
Test name
Test status
Simulation time 6336891620 ps
CPU time 90.82 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:05:34 PM PDT 24
Peak memory 199668 kb
Host smart-eb70829f-45d1-4cdf-ab89-32b5e9b63ccd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173011300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3173011300
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.547569434
Short name T394
Test name
Test status
Simulation time 12513157811 ps
CPU time 92.65 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:05:49 PM PDT 24
Peak memory 199728 kb
Host smart-bdbaaccc-bcf5-4718-949e-4e7da89a4925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547569434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.547569434
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.349628883
Short name T429
Test name
Test status
Simulation time 905839654 ps
CPU time 5.16 seconds
Started Apr 25 01:04:07 PM PDT 24
Finished Apr 25 01:04:13 PM PDT 24
Peak memory 199656 kb
Host smart-df967df0-c212-441b-92f4-bb1dc43f48d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349628883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.349628883
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2188673887
Short name T260
Test name
Test status
Simulation time 118899458745 ps
CPU time 580.01 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:13:55 PM PDT 24
Peak memory 216100 kb
Host smart-7b8fd978-f3dc-42b5-90cb-e65bea3f0552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188673887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2188673887
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.160521112
Short name T271
Test name
Test status
Simulation time 142583903 ps
CPU time 1.18 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:05 PM PDT 24
Peak memory 199660 kb
Host smart-6b2a9152-5800-4cb0-9a63-4a4dbbd500fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160521112 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.160521112
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3703229426
Short name T590
Test name
Test status
Simulation time 80079478823 ps
CPU time 512.95 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:12:39 PM PDT 24
Peak memory 199592 kb
Host smart-c4f4e1ff-a08e-4fc6-a489-0051dc9ba8b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703229426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3703229426
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.806069044
Short name T363
Test name
Test status
Simulation time 1368505020 ps
CPU time 7.69 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 199688 kb
Host smart-abba9bde-0056-424c-87a1-dfb4649b835b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806069044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.806069044
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1796218565
Short name T163
Test name
Test status
Simulation time 25154391 ps
CPU time 0.59 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 195356 kb
Host smart-673d179a-d3cb-4bb0-b3a1-59d34200ee4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796218565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1796218565
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.355421691
Short name T80
Test name
Test status
Simulation time 25259834104 ps
CPU time 45.84 seconds
Started Apr 25 01:04:12 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 213312 kb
Host smart-ab9a51f9-2c80-4897-8c33-faee3eaa6a3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355421691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.355421691
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4069597250
Short name T161
Test name
Test status
Simulation time 12577415068 ps
CPU time 51.08 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:05:02 PM PDT 24
Peak memory 199760 kb
Host smart-2f52c888-3148-43fc-902c-6f82d3b53c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069597250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4069597250
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2526876342
Short name T257
Test name
Test status
Simulation time 25514441 ps
CPU time 0.76 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:13 PM PDT 24
Peak memory 197048 kb
Host smart-464605d8-2d3f-4f4f-b901-63de4b703f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526876342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2526876342
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2470548331
Short name T216
Test name
Test status
Simulation time 1712414294 ps
CPU time 99.04 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:05:43 PM PDT 24
Peak memory 199656 kb
Host smart-c12f38ea-6015-4e8d-8b52-2199cecb2a2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470548331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2470548331
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1264880225
Short name T33
Test name
Test status
Simulation time 13698270373 ps
CPU time 44.73 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:49 PM PDT 24
Peak memory 199756 kb
Host smart-f481e1c6-d74f-4369-8824-971018760b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264880225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1264880225
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1586018697
Short name T350
Test name
Test status
Simulation time 119608626 ps
CPU time 1.38 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:13 PM PDT 24
Peak memory 199544 kb
Host smart-8a7db1d7-67db-4a4d-8cfb-cbfe5416c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586018697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1586018697
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2258213009
Short name T70
Test name
Test status
Simulation time 9832765879 ps
CPU time 33.39 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:05:06 PM PDT 24
Peak memory 199692 kb
Host smart-65976c03-03f0-4bf3-b322-119fdb861ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258213009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2258213009
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3109062153
Short name T41
Test name
Test status
Simulation time 28222865 ps
CPU time 1.01 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:04:04 PM PDT 24
Peak memory 199036 kb
Host smart-9477e498-b2eb-4532-aedc-6dc1a7faba70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109062153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3109062153
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1476106963
Short name T172
Test name
Test status
Simulation time 50691192346 ps
CPU time 545.13 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:13:17 PM PDT 24
Peak memory 199592 kb
Host smart-13af8e41-5895-4a22-9b63-6695c32367f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476106963 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1476106963
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1398962010
Short name T144
Test name
Test status
Simulation time 398249096 ps
CPU time 6.62 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:20 PM PDT 24
Peak memory 199588 kb
Host smart-c7f6e614-a539-47a6-9f9d-3c238285de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398962010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1398962010
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1930048051
Short name T162
Test name
Test status
Simulation time 19984501 ps
CPU time 0.57 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:04:16 PM PDT 24
Peak memory 195220 kb
Host smart-add07a45-c4c1-40c6-84d9-22534642f757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930048051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1930048051
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.277516647
Short name T522
Test name
Test status
Simulation time 1698563411 ps
CPU time 62.56 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:05:06 PM PDT 24
Peak memory 227324 kb
Host smart-e8638883-8bb3-4e2e-8004-67cfe5aaa426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277516647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.277516647
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2012155906
Short name T239
Test name
Test status
Simulation time 1807955876 ps
CPU time 57.89 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:05:14 PM PDT 24
Peak memory 199624 kb
Host smart-412ef8c2-70c1-4f9a-9a19-033947771385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012155906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2012155906
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2102378391
Short name T233
Test name
Test status
Simulation time 428045097 ps
CPU time 24.48 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199724 kb
Host smart-566a2103-face-4288-9e59-d0e4e6f093a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102378391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2102378391
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.628211132
Short name T490
Test name
Test status
Simulation time 6899052814 ps
CPU time 100.07 seconds
Started Apr 25 01:04:36 PM PDT 24
Finished Apr 25 01:06:18 PM PDT 24
Peak memory 199728 kb
Host smart-dab05c17-f261-4c99-a183-37f9a92cadc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628211132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.628211132
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2481848463
Short name T421
Test name
Test status
Simulation time 45783821843 ps
CPU time 130.94 seconds
Started Apr 25 01:04:12 PM PDT 24
Finished Apr 25 01:06:26 PM PDT 24
Peak memory 199692 kb
Host smart-6896aea7-0e93-4cb7-ac93-9c9542aac23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481848463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2481848463
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1562418853
Short name T384
Test name
Test status
Simulation time 165458233 ps
CPU time 1.63 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:04:07 PM PDT 24
Peak memory 199604 kb
Host smart-64f4f011-715a-484c-b3dc-197eecf2b336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562418853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1562418853
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2249764387
Short name T14
Test name
Test status
Simulation time 186688999464 ps
CPU time 807.42 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:18:03 PM PDT 24
Peak memory 226356 kb
Host smart-273ca6d0-66f0-418c-b3d1-c178705fa25b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249764387 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2249764387
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2330822527
Short name T310
Test name
Test status
Simulation time 93648665 ps
CPU time 0.97 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 198444 kb
Host smart-91fbab73-a6a0-47a5-a18b-d71e9af7ce09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330822527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2330822527
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.881935205
Short name T285
Test name
Test status
Simulation time 7214212729 ps
CPU time 382.51 seconds
Started Apr 25 01:04:02 PM PDT 24
Finished Apr 25 01:10:26 PM PDT 24
Peak memory 199520 kb
Host smart-f0397c3c-409d-4497-b554-767a57eb7cc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881935205 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.881935205
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3323956398
Short name T282
Test name
Test status
Simulation time 2470274334 ps
CPU time 31.03 seconds
Started Apr 25 01:04:03 PM PDT 24
Finished Apr 25 01:04:35 PM PDT 24
Peak memory 199684 kb
Host smart-0e3fc336-1199-4481-9684-8c30745f49ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323956398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3323956398
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2009612831
Short name T446
Test name
Test status
Simulation time 11767993 ps
CPU time 0.57 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:17 PM PDT 24
Peak memory 195060 kb
Host smart-c9217fa4-49aa-4b07-84ff-b0f2a11389db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009612831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2009612831
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.707555569
Short name T541
Test name
Test status
Simulation time 74427205 ps
CPU time 2.23 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:16 PM PDT 24
Peak memory 199632 kb
Host smart-ef7df8ab-b9b7-4f21-ba98-0afc1a5650f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707555569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.707555569
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1537760573
Short name T549
Test name
Test status
Simulation time 794095790 ps
CPU time 19.48 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:33 PM PDT 24
Peak memory 199632 kb
Host smart-ad21ad0b-f6f5-431a-ad94-ca2bfa78136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537760573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1537760573
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2350454103
Short name T126
Test name
Test status
Simulation time 1251110096 ps
CPU time 76.76 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:05:26 PM PDT 24
Peak memory 199684 kb
Host smart-3197600d-5b8c-47b3-b9c2-c1d24a22a2e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350454103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2350454103
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2781919573
Short name T581
Test name
Test status
Simulation time 27692359622 ps
CPU time 84.21 seconds
Started Apr 25 01:04:35 PM PDT 24
Finished Apr 25 01:06:00 PM PDT 24
Peak memory 199728 kb
Host smart-54417d05-6ea3-4b5c-9dfa-25e98028c5fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781919573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2781919573
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3824762384
Short name T487
Test name
Test status
Simulation time 718681735 ps
CPU time 40.31 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:05:15 PM PDT 24
Peak memory 199600 kb
Host smart-cd1a010a-c64c-4c45-a996-4a8ca8f14c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824762384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3824762384
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.759572220
Short name T505
Test name
Test status
Simulation time 1620973287 ps
CPU time 5.03 seconds
Started Apr 25 01:04:09 PM PDT 24
Finished Apr 25 01:04:15 PM PDT 24
Peak memory 199632 kb
Host smart-ded1c11a-4283-44d7-995a-435c295d8ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759572220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.759572220
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3586875501
Short name T213
Test name
Test status
Simulation time 62458517791 ps
CPU time 805.59 seconds
Started Apr 25 01:04:27 PM PDT 24
Finished Apr 25 01:17:53 PM PDT 24
Peak memory 199724 kb
Host smart-a99ad833-4beb-4adc-bdb6-243b5bd4781f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586875501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3586875501
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2034571479
Short name T209
Test name
Test status
Simulation time 46085539 ps
CPU time 1.01 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:14 PM PDT 24
Peak memory 199320 kb
Host smart-6418fc57-ea86-4684-97e6-07bd27e1ec7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034571479 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2034571479
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1238526740
Short name T453
Test name
Test status
Simulation time 150741414916 ps
CPU time 510.55 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:12:44 PM PDT 24
Peak memory 199692 kb
Host smart-99e681e2-d8b2-4feb-950d-9eec01a2587b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238526740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1238526740
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.292636181
Short name T289
Test name
Test status
Simulation time 746520200 ps
CPU time 5.32 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 199648 kb
Host smart-2a4c1097-f1f1-426a-b615-c5e36e27b318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292636181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.292636181
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1072198537
Short name T556
Test name
Test status
Simulation time 31126604 ps
CPU time 0.59 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:16 PM PDT 24
Peak memory 195344 kb
Host smart-b3cf4875-592a-4e2e-9322-e385158988c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072198537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1072198537
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1469672807
Short name T203
Test name
Test status
Simulation time 445641992 ps
CPU time 16.16 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 216012 kb
Host smart-41545dd4-f3a3-4b17-bfb2-a4a62a8591b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469672807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1469672807
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2222484265
Short name T287
Test name
Test status
Simulation time 1524575713 ps
CPU time 30.26 seconds
Started Apr 25 01:04:35 PM PDT 24
Finished Apr 25 01:05:07 PM PDT 24
Peak memory 199532 kb
Host smart-4e3fe884-3a81-4578-8e85-518a41711814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222484265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2222484265
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2465014067
Short name T217
Test name
Test status
Simulation time 8032856481 ps
CPU time 121.6 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:06:34 PM PDT 24
Peak memory 199724 kb
Host smart-a8c2d083-12ce-464f-a465-7818a5331d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465014067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2465014067
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2791561928
Short name T28
Test name
Test status
Simulation time 13953022816 ps
CPU time 128.79 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:06:27 PM PDT 24
Peak memory 199644 kb
Host smart-edb6a34d-f5d3-490b-84f3-165d5ed9474b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791561928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2791561928
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2771922639
Short name T227
Test name
Test status
Simulation time 2350180876 ps
CPU time 42.69 seconds
Started Apr 25 01:04:12 PM PDT 24
Finished Apr 25 01:04:58 PM PDT 24
Peak memory 199788 kb
Host smart-3b62f4a0-daf4-4b27-a951-b9a779cb9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771922639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2771922639
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.465454560
Short name T186
Test name
Test status
Simulation time 1699594165 ps
CPU time 5.43 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:04:19 PM PDT 24
Peak memory 199644 kb
Host smart-42e0228f-71cb-445e-8829-87e8f082d670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465454560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.465454560
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2968894119
Short name T258
Test name
Test status
Simulation time 126450649316 ps
CPU time 1197.52 seconds
Started Apr 25 01:04:11 PM PDT 24
Finished Apr 25 01:24:12 PM PDT 24
Peak memory 240780 kb
Host smart-04ec72c5-c51c-47fa-949f-454777739575
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968894119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2968894119
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3610967888
Short name T557
Test name
Test status
Simulation time 515055101 ps
CPU time 1.12 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199644 kb
Host smart-d3a98170-1efe-416c-a55a-1c5bd0f26fac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610967888 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3610967888
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3895849945
Short name T120
Test name
Test status
Simulation time 49134519504 ps
CPU time 454.01 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 199592 kb
Host smart-758a639d-eabc-4e59-8d7b-c285bf134299
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895849945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3895849945
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3144503648
Short name T115
Test name
Test status
Simulation time 1800859790 ps
CPU time 15.58 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 199592 kb
Host smart-31f2ffa4-9242-460a-8f44-3ea13251f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144503648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3144503648
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1286743825
Short name T361
Test name
Test status
Simulation time 14499378 ps
CPU time 0.59 seconds
Started Apr 25 01:04:28 PM PDT 24
Finished Apr 25 01:04:29 PM PDT 24
Peak memory 194288 kb
Host smart-5e055ee6-35ac-4549-8ad0-b6355d0eaa5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286743825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1286743825
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.982560177
Short name T546
Test name
Test status
Simulation time 901684599 ps
CPU time 8.05 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 199708 kb
Host smart-173e546f-f84c-4ae6-9379-35aed2cd3e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982560177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.982560177
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.902409854
Short name T473
Test name
Test status
Simulation time 3654607815 ps
CPU time 20.55 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199700 kb
Host smart-cb6b191f-21b9-4060-abcd-4cbbd7367431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902409854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.902409854
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4191624350
Short name T204
Test name
Test status
Simulation time 394683630 ps
CPU time 21.95 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:04:40 PM PDT 24
Peak memory 199656 kb
Host smart-3296bd3b-4a5a-4413-b52c-919d1a0723ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191624350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4191624350
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2248140169
Short name T293
Test name
Test status
Simulation time 1226119296 ps
CPU time 4.26 seconds
Started Apr 25 01:04:12 PM PDT 24
Finished Apr 25 01:04:19 PM PDT 24
Peak memory 199596 kb
Host smart-4add6b2f-6b04-40eb-893c-64214dc1a143
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248140169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2248140169
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.528271987
Short name T124
Test name
Test status
Simulation time 6270184425 ps
CPU time 41.05 seconds
Started Apr 25 01:04:19 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199696 kb
Host smart-fb120382-dc50-4b80-9285-f919ee521657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528271987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.528271987
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1577138162
Short name T406
Test name
Test status
Simulation time 152863458 ps
CPU time 5.05 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:04:23 PM PDT 24
Peak memory 199556 kb
Host smart-710b9eda-f8e7-44b5-86af-c72ab69b16de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577138162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1577138162
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4110354015
Short name T364
Test name
Test status
Simulation time 4655999273 ps
CPU time 259.51 seconds
Started Apr 25 01:04:20 PM PDT 24
Finished Apr 25 01:08:40 PM PDT 24
Peak memory 199740 kb
Host smart-1eee61e9-3c41-4d0e-a50f-3b8af3a4af6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110354015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4110354015
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.725331125
Short name T284
Test name
Test status
Simulation time 32587292 ps
CPU time 1.2 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 199644 kb
Host smart-6ef7b7c7-90c9-4d5e-b0bd-c18c550c889c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725331125 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.725331125
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2796801175
Short name T496
Test name
Test status
Simulation time 8567309356 ps
CPU time 452.74 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 199656 kb
Host smart-2230cd79-a914-4d6d-bdf0-d623847eeff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796801175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2796801175
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2743904075
Short name T378
Test name
Test status
Simulation time 3473887521 ps
CPU time 87.05 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:05:45 PM PDT 24
Peak memory 199716 kb
Host smart-bdb9cff2-5137-4be6-82b0-838b9d1c9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743904075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2743904075
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.477769315
Short name T383
Test name
Test status
Simulation time 14706224 ps
CPU time 0.61 seconds
Started Apr 25 01:04:20 PM PDT 24
Finished Apr 25 01:04:21 PM PDT 24
Peak memory 195340 kb
Host smart-e29a6b6c-d956-428a-9502-e02386957ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477769315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.477769315
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.428045219
Short name T340
Test name
Test status
Simulation time 416340492 ps
CPU time 17.75 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 215912 kb
Host smart-398f8173-fabb-4cc8-9c88-6130a13a4fa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428045219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.428045219
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3358888071
Short name T393
Test name
Test status
Simulation time 819635331 ps
CPU time 9.82 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:04:27 PM PDT 24
Peak memory 199604 kb
Host smart-0b8b0507-09f3-460f-80e1-4ecc8e47b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358888071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3358888071
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3707878095
Short name T194
Test name
Test status
Simulation time 3280118560 ps
CPU time 52.34 seconds
Started Apr 25 01:04:10 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 199660 kb
Host smart-e1b225d0-421b-4c0f-ba02-baa58f088c0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707878095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3707878095
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3886146761
Short name T561
Test name
Test status
Simulation time 49849362288 ps
CPU time 216.24 seconds
Started Apr 25 01:04:13 PM PDT 24
Finished Apr 25 01:07:51 PM PDT 24
Peak memory 199760 kb
Host smart-5105bca5-a431-4824-9d8d-65968c2dcf99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886146761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3886146761
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4166660647
Short name T77
Test name
Test status
Simulation time 14736083621 ps
CPU time 74.69 seconds
Started Apr 25 01:04:21 PM PDT 24
Finished Apr 25 01:05:37 PM PDT 24
Peak memory 199616 kb
Host smart-c6c4bbdd-14a6-4032-8c4b-cc8ca3d5237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166660647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4166660647
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3185787412
Short name T346
Test name
Test status
Simulation time 131716800 ps
CPU time 1.27 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:17 PM PDT 24
Peak memory 199668 kb
Host smart-0aa2f690-ef46-4034-b6ce-22b514e72321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185787412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3185787412
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3003451549
Short name T497
Test name
Test status
Simulation time 39349660017 ps
CPU time 466.74 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:12:04 PM PDT 24
Peak memory 247596 kb
Host smart-9564b34e-1f8c-46d9-b25b-d5e3831931b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003451549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3003451549
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.926968496
Short name T269
Test name
Test status
Simulation time 155032136 ps
CPU time 1.01 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:04:20 PM PDT 24
Peak memory 199508 kb
Host smart-16697d7a-fac1-479f-8a43-beb5c1990f33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926968496 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.926968496
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.4102853416
Short name T466
Test name
Test status
Simulation time 135986711275 ps
CPU time 500.34 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:12:38 PM PDT 24
Peak memory 199660 kb
Host smart-d789d7a1-000f-46f7-83e3-6abd4fe68022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102853416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.4102853416
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2029559760
Short name T243
Test name
Test status
Simulation time 1388630773 ps
CPU time 25.74 seconds
Started Apr 25 01:04:14 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 199684 kb
Host smart-10c7367d-9720-4ba2-b9e3-b691d5f79fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029559760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2029559760
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4231622029
Short name T339
Test name
Test status
Simulation time 21007240 ps
CPU time 0.58 seconds
Started Apr 25 01:04:22 PM PDT 24
Finished Apr 25 01:04:23 PM PDT 24
Peak memory 195052 kb
Host smart-0911cc33-35a7-403b-ad3f-4b3b6abe1c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231622029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4231622029
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1433004241
Short name T545
Test name
Test status
Simulation time 580806257 ps
CPU time 5.97 seconds
Started Apr 25 01:04:22 PM PDT 24
Finished Apr 25 01:04:29 PM PDT 24
Peak memory 216016 kb
Host smart-1642a270-2622-40b1-a0fa-36814e551ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433004241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1433004241
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.830461359
Short name T241
Test name
Test status
Simulation time 1292727025 ps
CPU time 15.38 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:04:50 PM PDT 24
Peak memory 199648 kb
Host smart-b1454021-6519-4665-8a35-7b9865fbe267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830461359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.830461359
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3370987684
Short name T267
Test name
Test status
Simulation time 1801288907 ps
CPU time 97.53 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:06:08 PM PDT 24
Peak memory 199604 kb
Host smart-324c8d09-55d5-492c-9aec-b9d5f291ccdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370987684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3370987684
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.905147142
Short name T570
Test name
Test status
Simulation time 16421622564 ps
CPU time 186.01 seconds
Started Apr 25 01:04:32 PM PDT 24
Finished Apr 25 01:07:39 PM PDT 24
Peak memory 199700 kb
Host smart-c73d0b03-0dc7-4410-b805-6df4597fb089
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905147142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.905147142
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.39638025
Short name T462
Test name
Test status
Simulation time 5522448704 ps
CPU time 71.43 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:05:29 PM PDT 24
Peak memory 199736 kb
Host smart-5c3a2df9-e45d-4674-b9ed-b4ead77220c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39638025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.39638025
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2674685790
Short name T534
Test name
Test status
Simulation time 175099696 ps
CPU time 5.49 seconds
Started Apr 25 01:04:35 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 199600 kb
Host smart-f7c42236-dc87-4676-8bfb-fd5f277714c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674685790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2674685790
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2651784282
Short name T168
Test name
Test status
Simulation time 27551240869 ps
CPU time 719.64 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:16:18 PM PDT 24
Peak memory 199712 kb
Host smart-c5efd88e-2e41-476e-94ab-a7d7d7bd719f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651784282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2651784282
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3527350411
Short name T321
Test name
Test status
Simulation time 116455568 ps
CPU time 1.09 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:27 PM PDT 24
Peak memory 199600 kb
Host smart-8b9768bd-10ae-4407-85e2-f589693f3322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527350411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3527350411
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.4093410409
Short name T306
Test name
Test status
Simulation time 14437890683 ps
CPU time 434.72 seconds
Started Apr 25 01:04:21 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 199652 kb
Host smart-e131fd66-1319-404a-bf4b-7944ec2255e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093410409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.4093410409
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.743021322
Short name T301
Test name
Test status
Simulation time 3845615964 ps
CPU time 69.52 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:05:42 PM PDT 24
Peak memory 199736 kb
Host smart-f16eaebe-0f90-47f1-bf00-b28caf0ee77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743021322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.743021322
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3692616015
Short name T527
Test name
Test status
Simulation time 14105117 ps
CPU time 0.61 seconds
Started Apr 25 01:04:32 PM PDT 24
Finished Apr 25 01:04:34 PM PDT 24
Peak memory 195324 kb
Host smart-6dbe05b5-5965-450a-97b3-75bbbec57fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692616015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3692616015
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2827666393
Short name T160
Test name
Test status
Simulation time 1725328547 ps
CPU time 17.91 seconds
Started Apr 25 01:04:18 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 215656 kb
Host smart-aee01832-6996-4328-9fb1-d3930219e294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827666393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2827666393
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3737129959
Short name T118
Test name
Test status
Simulation time 722650441 ps
CPU time 7.79 seconds
Started Apr 25 01:04:43 PM PDT 24
Finished Apr 25 01:04:51 PM PDT 24
Peak memory 199552 kb
Host smart-fee2af2c-1d5c-4fa5-90d9-370333506d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737129959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3737129959
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1290116517
Short name T577
Test name
Test status
Simulation time 314557745 ps
CPU time 9.39 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:04:28 PM PDT 24
Peak memory 199644 kb
Host smart-a2a8853d-8992-4afc-b93d-f282bc5db0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290116517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1290116517
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3774855699
Short name T390
Test name
Test status
Simulation time 6515024103 ps
CPU time 186.71 seconds
Started Apr 25 01:04:18 PM PDT 24
Finished Apr 25 01:07:26 PM PDT 24
Peak memory 199768 kb
Host smart-c1065273-1e3d-45ef-9c6f-5bbfd88ccbf1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774855699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3774855699
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.232449213
Short name T323
Test name
Test status
Simulation time 20397527691 ps
CPU time 100.62 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:05:59 PM PDT 24
Peak memory 199604 kb
Host smart-fe06aa52-3636-4630-b560-d7cbce12fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232449213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.232449213
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1156445742
Short name T576
Test name
Test status
Simulation time 2432044160 ps
CPU time 7.38 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 199716 kb
Host smart-771b82bd-252f-47b8-9b79-d21dc0257a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156445742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1156445742
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2618321567
Short name T73
Test name
Test status
Simulation time 22941480011 ps
CPU time 343.35 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 230708 kb
Host smart-f8b34a3f-e333-46c9-8787-6ac9731a6cad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618321567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2618321567
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3267478255
Short name T565
Test name
Test status
Simulation time 83142310 ps
CPU time 1.07 seconds
Started Apr 25 01:04:22 PM PDT 24
Finished Apr 25 01:04:23 PM PDT 24
Peak memory 199280 kb
Host smart-40ac639e-eec0-4e73-af43-a492d902cc6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267478255 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3267478255
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.96645722
Short name T191
Test name
Test status
Simulation time 7580825522 ps
CPU time 440.76 seconds
Started Apr 25 01:04:19 PM PDT 24
Finished Apr 25 01:11:40 PM PDT 24
Peak memory 199708 kb
Host smart-6bea287b-e748-48e6-b971-f49ae154a41a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96645722 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.96645722
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.386514113
Short name T322
Test name
Test status
Simulation time 650688451 ps
CPU time 17.95 seconds
Started Apr 25 01:04:27 PM PDT 24
Finished Apr 25 01:04:46 PM PDT 24
Peak memory 199592 kb
Host smart-1462d529-d42e-4b5a-8c0d-d3ceaf150906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386514113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.386514113
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3492928010
Short name T341
Test name
Test status
Simulation time 18628233 ps
CPU time 0.61 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:03:40 PM PDT 24
Peak memory 195436 kb
Host smart-6bd6271b-7e2c-4966-b681-57d1f99eb926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492928010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3492928010
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3522333701
Short name T159
Test name
Test status
Simulation time 7170315497 ps
CPU time 46.43 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:04:21 PM PDT 24
Peak memory 216088 kb
Host smart-8150256b-9b1d-47f0-a3f8-9d2d5f0617b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522333701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3522333701
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.868721762
Short name T197
Test name
Test status
Simulation time 2426351668 ps
CPU time 12.16 seconds
Started Apr 25 01:03:45 PM PDT 24
Finished Apr 25 01:03:58 PM PDT 24
Peak memory 199472 kb
Host smart-ea519db4-7ab0-4c03-a360-a47ffe86e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868721762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.868721762
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3235728166
Short name T116
Test name
Test status
Simulation time 2333673719 ps
CPU time 133.61 seconds
Started Apr 25 01:03:32 PM PDT 24
Finished Apr 25 01:05:47 PM PDT 24
Peak memory 199732 kb
Host smart-da956b06-47b0-437f-993f-f7f4e5dec9b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235728166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3235728166
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.567204540
Short name T32
Test name
Test status
Simulation time 14320676580 ps
CPU time 183.71 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:06:41 PM PDT 24
Peak memory 199732 kb
Host smart-4373bb65-e508-4c23-9b74-ec80b2931ea9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567204540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.567204540
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4244257793
Short name T140
Test name
Test status
Simulation time 5678477205 ps
CPU time 19.55 seconds
Started Apr 25 01:03:39 PM PDT 24
Finished Apr 25 01:04:00 PM PDT 24
Peak memory 199784 kb
Host smart-54ad669a-5252-4e3f-8f08-c0242dee2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244257793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4244257793
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2978346241
Short name T38
Test name
Test status
Simulation time 36845358 ps
CPU time 0.8 seconds
Started Apr 25 01:03:40 PM PDT 24
Finished Apr 25 01:03:41 PM PDT 24
Peak memory 218148 kb
Host smart-15e09df2-19c0-43f2-923c-46f26077dc01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978346241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2978346241
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.997500317
Short name T179
Test name
Test status
Simulation time 138448763 ps
CPU time 4.01 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:03:54 PM PDT 24
Peak memory 199532 kb
Host smart-31e00dca-ce9b-4198-a3d3-05bce3d2cbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997500317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.997500317
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.471465167
Short name T528
Test name
Test status
Simulation time 21225627306 ps
CPU time 635.98 seconds
Started Apr 25 01:03:42 PM PDT 24
Finished Apr 25 01:14:20 PM PDT 24
Peak memory 199712 kb
Host smart-b193c882-4927-4368-9aa5-ee76baf0aa1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471465167 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.471465167
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2351426287
Short name T180
Test name
Test status
Simulation time 53907771 ps
CPU time 0.93 seconds
Started Apr 25 01:03:41 PM PDT 24
Finished Apr 25 01:03:43 PM PDT 24
Peak memory 198480 kb
Host smart-ad999bbb-e950-442e-a0d4-e09594c4f618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351426287 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2351426287
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1532634177
Short name T262
Test name
Test status
Simulation time 29279439363 ps
CPU time 527.87 seconds
Started Apr 25 01:03:31 PM PDT 24
Finished Apr 25 01:12:20 PM PDT 24
Peak memory 199664 kb
Host smart-d0f9eff3-f546-493d-a8d9-3caf19091ea6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532634177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1532634177
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3108252342
Short name T133
Test name
Test status
Simulation time 1292360707 ps
CPU time 31.15 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:04:16 PM PDT 24
Peak memory 199700 kb
Host smart-53bc0252-1d16-44a9-b0f8-107a63cdf215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108252342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3108252342
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.395786123
Short name T377
Test name
Test status
Simulation time 47577591 ps
CPU time 0.59 seconds
Started Apr 25 01:04:16 PM PDT 24
Finished Apr 25 01:04:19 PM PDT 24
Peak memory 195324 kb
Host smart-329ab468-f840-4c1c-8f14-13541106397d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395786123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.395786123
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1684944505
Short name T231
Test name
Test status
Simulation time 7130255760 ps
CPU time 44.91 seconds
Started Apr 25 01:04:22 PM PDT 24
Finished Apr 25 01:05:08 PM PDT 24
Peak memory 207952 kb
Host smart-c08bc8eb-57be-4054-b944-1bdbcd82ad9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684944505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1684944505
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2180721435
Short name T382
Test name
Test status
Simulation time 215910629 ps
CPU time 5.13 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199620 kb
Host smart-a18d9093-ba98-446a-9743-083e028b6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180721435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2180721435
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2367826756
Short name T475
Test name
Test status
Simulation time 903683019 ps
CPU time 52.24 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:05:11 PM PDT 24
Peak memory 199672 kb
Host smart-1181c02e-fb1d-4ed9-b5db-b82d2553e68f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367826756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2367826756
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1787657437
Short name T79
Test name
Test status
Simulation time 1539818429 ps
CPU time 13.87 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:04:49 PM PDT 24
Peak memory 199628 kb
Host smart-d136ace5-ba4f-4494-8f77-b2d9208258b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787657437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1787657437
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2326644770
Short name T84
Test name
Test status
Simulation time 1188666249 ps
CPU time 11.85 seconds
Started Apr 25 01:04:35 PM PDT 24
Finished Apr 25 01:04:48 PM PDT 24
Peak memory 199556 kb
Host smart-ed6b1f6a-775f-421a-9e45-08df5b8aa0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326644770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2326644770
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1319327185
Short name T434
Test name
Test status
Simulation time 762346677 ps
CPU time 5.98 seconds
Started Apr 25 01:04:15 PM PDT 24
Finished Apr 25 01:04:23 PM PDT 24
Peak memory 199620 kb
Host smart-cd508caf-58c9-4bd3-b344-fbad8833d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319327185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1319327185
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2962516647
Short name T238
Test name
Test status
Simulation time 4400334177 ps
CPU time 136.32 seconds
Started Apr 25 01:04:22 PM PDT 24
Finished Apr 25 01:06:39 PM PDT 24
Peak memory 199660 kb
Host smart-27e5ffa7-ada0-42e9-8673-059dbcf76d75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962516647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2962516647
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4201951535
Short name T18
Test name
Test status
Simulation time 109057721 ps
CPU time 1.42 seconds
Started Apr 25 01:04:21 PM PDT 24
Finished Apr 25 01:04:24 PM PDT 24
Peak memory 199584 kb
Host smart-96e4d60c-4bb7-4598-8809-3766cd52072b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201951535 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4201951535
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.988345559
Short name T510
Test name
Test status
Simulation time 141123461927 ps
CPU time 452.58 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:12:13 PM PDT 24
Peak memory 199680 kb
Host smart-e1c65a3a-03fd-446c-9bb1-2fcc08080c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988345559 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.988345559
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2112580638
Short name T559
Test name
Test status
Simulation time 600841193 ps
CPU time 22.34 seconds
Started Apr 25 01:04:28 PM PDT 24
Finished Apr 25 01:04:51 PM PDT 24
Peak memory 199680 kb
Host smart-6374c0b9-9d5b-44dc-8bac-46bd30d33183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112580638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2112580638
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.456396481
Short name T457
Test name
Test status
Simulation time 20631933 ps
CPU time 0.59 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:04:30 PM PDT 24
Peak memory 195360 kb
Host smart-cf7188e4-aab6-4ec6-a2ae-feccf3394cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456396481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.456396481
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1678416263
Short name T211
Test name
Test status
Simulation time 73478551 ps
CPU time 2.87 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:29 PM PDT 24
Peak memory 207868 kb
Host smart-9185d44e-e5ea-4904-9581-c9652f0b5518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678416263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1678416263
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1383452540
Short name T295
Test name
Test status
Simulation time 13573271890 ps
CPU time 51.32 seconds
Started Apr 25 01:04:20 PM PDT 24
Finished Apr 25 01:05:12 PM PDT 24
Peak memory 199724 kb
Host smart-ac9cc3a3-5dff-45e3-a9d5-f48b7fdc90d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383452540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1383452540
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1315661719
Short name T308
Test name
Test status
Simulation time 2891463518 ps
CPU time 87.08 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:05:54 PM PDT 24
Peak memory 199620 kb
Host smart-64f3e43d-81a6-4b8d-b36b-7c38c9b3a806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315661719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1315661719
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3623239348
Short name T152
Test name
Test status
Simulation time 3785556169 ps
CPU time 49.1 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 199732 kb
Host smart-e32ecd41-fb6d-4bcd-a824-a5a1b4ba3fdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623239348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3623239348
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1825605991
Short name T268
Test name
Test status
Simulation time 444145475 ps
CPU time 7.29 seconds
Started Apr 25 01:04:35 PM PDT 24
Finished Apr 25 01:04:43 PM PDT 24
Peak memory 199616 kb
Host smart-d371f083-ea2e-4ebe-b2b1-9e3b095eb1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825605991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1825605991
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.768789020
Short name T136
Test name
Test status
Simulation time 124704745 ps
CPU time 2.16 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:04:21 PM PDT 24
Peak memory 199520 kb
Host smart-a7bcdee4-b476-4c80-9f07-8e8deeef6088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768789020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.768789020
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4113425465
Short name T336
Test name
Test status
Simulation time 8748548253 ps
CPU time 123.53 seconds
Started Apr 25 01:04:36 PM PDT 24
Finished Apr 25 01:06:41 PM PDT 24
Peak memory 199696 kb
Host smart-09d34eb8-6ea8-442c-a7df-a24efa4abadf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113425465 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4113425465
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.363891843
Short name T326
Test name
Test status
Simulation time 200383829 ps
CPU time 1.31 seconds
Started Apr 25 01:04:44 PM PDT 24
Finished Apr 25 01:04:47 PM PDT 24
Peak memory 199636 kb
Host smart-db4d315f-d5d3-4b83-a4ae-576968437b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363891843 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.363891843
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.565683814
Short name T139
Test name
Test status
Simulation time 107993696839 ps
CPU time 503.76 seconds
Started Apr 25 01:04:17 PM PDT 24
Finished Apr 25 01:12:43 PM PDT 24
Peak memory 199628 kb
Host smart-a60ab207-4d29-40e9-8cb2-34b89532bbd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565683814 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.565683814
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.543266808
Short name T114
Test name
Test status
Simulation time 3995196749 ps
CPU time 75.37 seconds
Started Apr 25 01:04:18 PM PDT 24
Finished Apr 25 01:05:35 PM PDT 24
Peak memory 199580 kb
Host smart-56e0ab32-9499-481a-934e-3d9b6228e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543266808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.543266808
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2924811007
Short name T349
Test name
Test status
Simulation time 11222105 ps
CPU time 0.55 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 195296 kb
Host smart-f64be92c-7a20-4378-9ab7-c43b80743685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924811007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2924811007
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1718254275
Short name T20
Test name
Test status
Simulation time 1010085700 ps
CPU time 37.31 seconds
Started Apr 25 01:04:45 PM PDT 24
Finished Apr 25 01:05:23 PM PDT 24
Peak memory 215956 kb
Host smart-52f933e4-84b9-4598-82bf-b4d2da73c535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718254275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1718254275
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3063899945
Short name T454
Test name
Test status
Simulation time 4055644414 ps
CPU time 19.49 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:45 PM PDT 24
Peak memory 199776 kb
Host smart-abd07781-9180-452a-95fb-d15f4d233967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063899945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3063899945
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.388307061
Short name T224
Test name
Test status
Simulation time 423965996 ps
CPU time 24.72 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:04:50 PM PDT 24
Peak memory 199688 kb
Host smart-084e9eb8-47e2-4483-a28c-f5a460740bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388307061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.388307061
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.61902488
Short name T411
Test name
Test status
Simulation time 5192808314 ps
CPU time 73.62 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:05:51 PM PDT 24
Peak memory 199660 kb
Host smart-cca78516-5d20-41a9-8613-8411a2649fdd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61902488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.61902488
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3814528140
Short name T526
Test name
Test status
Simulation time 499620123 ps
CPU time 28.74 seconds
Started Apr 25 01:04:19 PM PDT 24
Finished Apr 25 01:04:48 PM PDT 24
Peak memory 199676 kb
Host smart-c3e14846-3395-4696-8eb6-ec178d12e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814528140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3814528140
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2167986354
Short name T523
Test name
Test status
Simulation time 651699579 ps
CPU time 5.09 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:04:43 PM PDT 24
Peak memory 199620 kb
Host smart-4892b2da-23a6-429d-a49b-9068084dcb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167986354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2167986354
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2504891657
Short name T72
Test name
Test status
Simulation time 71792613475 ps
CPU time 190.95 seconds
Started Apr 25 01:04:44 PM PDT 24
Finished Apr 25 01:07:55 PM PDT 24
Peak memory 246712 kb
Host smart-7b617672-6555-455c-a64c-34ce8e27f9a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504891657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2504891657
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1585178460
Short name T543
Test name
Test status
Simulation time 110472097 ps
CPU time 1.15 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 199532 kb
Host smart-d93c563b-cb67-4a24-a5e7-46e037b6b894
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585178460 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1585178460
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2967603968
Short name T225
Test name
Test status
Simulation time 50059466140 ps
CPU time 457.65 seconds
Started Apr 25 01:04:33 PM PDT 24
Finished Apr 25 01:12:12 PM PDT 24
Peak memory 199632 kb
Host smart-9f40b867-1b5e-4e81-bc77-d5e443d124cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967603968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2967603968
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1542656756
Short name T242
Test name
Test status
Simulation time 7777092767 ps
CPU time 29.79 seconds
Started Apr 25 01:04:32 PM PDT 24
Finished Apr 25 01:05:03 PM PDT 24
Peak memory 199720 kb
Host smart-2d8c049b-e800-4fac-96e7-8f69f5a9f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542656756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1542656756
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1522945279
Short name T580
Test name
Test status
Simulation time 15258273 ps
CPU time 0.6 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:04:44 PM PDT 24
Peak memory 194268 kb
Host smart-1a84f906-200b-4149-9db2-ca15cebe0a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522945279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1522945279
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2409335782
Short name T247
Test name
Test status
Simulation time 92033627 ps
CPU time 3.34 seconds
Started Apr 25 01:04:27 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 207868 kb
Host smart-00d4760b-a568-487c-9312-08318833c1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409335782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2409335782
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2152083612
Short name T56
Test name
Test status
Simulation time 7080724432 ps
CPU time 36.32 seconds
Started Apr 25 01:04:28 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 199740 kb
Host smart-4715e5f0-878a-44b4-9788-34cce4d3a4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152083612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2152083612
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1731053927
Short name T234
Test name
Test status
Simulation time 5526537148 ps
CPU time 103.01 seconds
Started Apr 25 01:04:33 PM PDT 24
Finished Apr 25 01:06:17 PM PDT 24
Peak memory 199720 kb
Host smart-65e94fa0-2769-4ca8-9946-03d88bb6311e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731053927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1731053927
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1570874020
Short name T584
Test name
Test status
Simulation time 1051169595 ps
CPU time 55.15 seconds
Started Apr 25 01:04:33 PM PDT 24
Finished Apr 25 01:05:29 PM PDT 24
Peak memory 199672 kb
Host smart-99265e54-1301-4ca8-8152-293a76c06a57
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570874020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1570874020
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2807435895
Short name T119
Test name
Test status
Simulation time 28186965617 ps
CPU time 101.45 seconds
Started Apr 25 01:04:25 PM PDT 24
Finished Apr 25 01:06:08 PM PDT 24
Peak memory 199664 kb
Host smart-8f756876-6a15-488b-aafe-aaa58c7044ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807435895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2807435895
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3555736415
Short name T372
Test name
Test status
Simulation time 322827637 ps
CPU time 4 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 199636 kb
Host smart-c17db59e-0eb9-4cd6-93c2-204294b15e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555736415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3555736415
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3114846611
Short name T427
Test name
Test status
Simulation time 673845528 ps
CPU time 1.12 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:04:31 PM PDT 24
Peak memory 199600 kb
Host smart-dc05f9b3-074a-47f4-91d1-e6ad88dfd516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114846611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3114846611
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3104910350
Short name T55
Test name
Test status
Simulation time 96561752 ps
CPU time 0.96 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 198308 kb
Host smart-b1a4e9b8-892c-408c-afc9-b3e65803f7f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104910350 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3104910350
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.4134701564
Short name T151
Test name
Test status
Simulation time 109995907814 ps
CPU time 485.66 seconds
Started Apr 25 01:04:33 PM PDT 24
Finished Apr 25 01:12:39 PM PDT 24
Peak memory 199604 kb
Host smart-e7396a23-70f2-4572-ac90-3034c7aaa800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134701564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.4134701564
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3467782592
Short name T477
Test name
Test status
Simulation time 98008682 ps
CPU time 5.21 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:04:40 PM PDT 24
Peak memory 199672 kb
Host smart-655e6f0f-5fd3-40c8-aaaa-1e1845da139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467782592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3467782592
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2883367679
Short name T426
Test name
Test status
Simulation time 78160355 ps
CPU time 0.59 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:04:27 PM PDT 24
Peak memory 195360 kb
Host smart-f95d1ef5-7ce6-4f52-81e8-0166e8e3b11f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883367679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2883367679
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4155727913
Short name T221
Test name
Test status
Simulation time 3192260585 ps
CPU time 30.81 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:04:58 PM PDT 24
Peak memory 216116 kb
Host smart-c498fbb6-3ee8-4eb6-abbf-ec35eb046d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155727913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4155727913
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3377748806
Short name T148
Test name
Test status
Simulation time 1836164390 ps
CPU time 18.49 seconds
Started Apr 25 01:04:44 PM PDT 24
Finished Apr 25 01:05:03 PM PDT 24
Peak memory 199616 kb
Host smart-79223fab-e060-41a6-b617-49070676d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377748806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3377748806
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2415329240
Short name T249
Test name
Test status
Simulation time 2149349667 ps
CPU time 13.01 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:04:48 PM PDT 24
Peak memory 199720 kb
Host smart-fdb2e147-1804-4176-abc4-5587e7a94f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415329240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2415329240
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1274866786
Short name T45
Test name
Test status
Simulation time 1662006605 ps
CPU time 93.66 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:06:08 PM PDT 24
Peak memory 199632 kb
Host smart-450f1202-9550-42b8-a944-2596c439736f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274866786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1274866786
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.936074011
Short name T409
Test name
Test status
Simulation time 203646704 ps
CPU time 5.14 seconds
Started Apr 25 01:04:27 PM PDT 24
Finished Apr 25 01:04:33 PM PDT 24
Peak memory 199668 kb
Host smart-67948b6b-0598-4a4a-896d-ff6c26c190bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936074011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.936074011
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2689516331
Short name T469
Test name
Test status
Simulation time 1485305415 ps
CPU time 5.56 seconds
Started Apr 25 01:04:36 PM PDT 24
Finished Apr 25 01:04:43 PM PDT 24
Peak memory 199624 kb
Host smart-66bd6c14-9950-41d1-871e-eea7e1194d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689516331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2689516331
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.4094283674
Short name T75
Test name
Test status
Simulation time 11341643509 ps
CPU time 37.64 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 199744 kb
Host smart-de62c3c5-9cef-42a1-86e2-78ba1b4c7df9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094283674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4094283674
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.907560376
Short name T264
Test name
Test status
Simulation time 95109855 ps
CPU time 0.91 seconds
Started Apr 25 01:04:36 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 198044 kb
Host smart-72224d87-11d3-40f9-9393-443a4e36cf8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907560376 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.907560376
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3449306620
Short name T78
Test name
Test status
Simulation time 132790824854 ps
CPU time 523.26 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:13:14 PM PDT 24
Peak memory 199692 kb
Host smart-7897331b-13be-48cf-8c26-b643f16031de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449306620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3449306620
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1685923657
Short name T494
Test name
Test status
Simulation time 3017703524 ps
CPU time 28.44 seconds
Started Apr 25 01:04:26 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 199620 kb
Host smart-211351be-f355-4062-8fbf-74998ef25c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685923657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1685923657
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2045761968
Short name T520
Test name
Test status
Simulation time 11742563 ps
CPU time 0.58 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 195020 kb
Host smart-1b59bfe6-3cd0-4eee-a136-acd91728edaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045761968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2045761968
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.235819889
Short name T328
Test name
Test status
Simulation time 6035737140 ps
CPU time 25.28 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:05:17 PM PDT 24
Peak memory 199644 kb
Host smart-3cc28298-2e08-4ce7-90a3-c3ed9683bcf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235819889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.235819889
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1223658891
Short name T436
Test name
Test status
Simulation time 4574964052 ps
CPU time 23.27 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:23 PM PDT 24
Peak memory 199716 kb
Host smart-11b9719e-f5e2-4fed-ae7e-2f3ffbe7c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223658891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1223658891
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.963211317
Short name T102
Test name
Test status
Simulation time 16993547467 ps
CPU time 160.44 seconds
Started Apr 25 01:04:52 PM PDT 24
Finished Apr 25 01:07:33 PM PDT 24
Peak memory 199732 kb
Host smart-7fc7576c-17e3-4665-a575-9a736a9d3311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963211317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.963211317
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.798184945
Short name T529
Test name
Test status
Simulation time 100811508047 ps
CPU time 220.16 seconds
Started Apr 25 01:04:32 PM PDT 24
Finished Apr 25 01:08:13 PM PDT 24
Peak memory 199740 kb
Host smart-f5cab4a4-e18f-450c-84bf-ad982c7ee8cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798184945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.798184945
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2998325924
Short name T571
Test name
Test status
Simulation time 10365319573 ps
CPU time 147.95 seconds
Started Apr 25 01:04:45 PM PDT 24
Finished Apr 25 01:07:14 PM PDT 24
Peak memory 199720 kb
Host smart-2dc85489-3cd4-400a-b5d1-90015fc468a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998325924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2998325924
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1118627780
Short name T82
Test name
Test status
Simulation time 1979458849 ps
CPU time 4.24 seconds
Started Apr 25 01:04:38 PM PDT 24
Finished Apr 25 01:04:44 PM PDT 24
Peak memory 199536 kb
Host smart-ae692acb-a6ee-4075-aba9-65e4f0aceb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118627780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1118627780
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2567439364
Short name T519
Test name
Test status
Simulation time 190740797145 ps
CPU time 1634.5 seconds
Started Apr 25 01:04:54 PM PDT 24
Finished Apr 25 01:32:10 PM PDT 24
Peak memory 228648 kb
Host smart-302be7ad-ec47-4573-8455-bfc0a592143b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567439364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2567439364
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.4168050444
Short name T117
Test name
Test status
Simulation time 161905575 ps
CPU time 1.02 seconds
Started Apr 25 01:04:52 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 198600 kb
Host smart-9b7cf06f-0676-4c20-867d-6d2aac36eb5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168050444 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.4168050444
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1542302443
Short name T468
Test name
Test status
Simulation time 100622961593 ps
CPU time 482.65 seconds
Started Apr 25 01:04:28 PM PDT 24
Finished Apr 25 01:12:32 PM PDT 24
Peak memory 199632 kb
Host smart-1c38f101-0b13-41ff-99e7-b0fa053febde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542302443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1542302443
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4214004304
Short name T371
Test name
Test status
Simulation time 6808243045 ps
CPU time 23.2 seconds
Started Apr 25 01:04:50 PM PDT 24
Finished Apr 25 01:05:14 PM PDT 24
Peak memory 199752 kb
Host smart-5217386b-ac1c-4bb3-ac84-a2d352b83458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214004304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4214004304
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1968566654
Short name T176
Test name
Test status
Simulation time 13838281 ps
CPU time 0.63 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:04:49 PM PDT 24
Peak memory 195356 kb
Host smart-5389ff32-3295-445f-a47e-b5299096b5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968566654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1968566654
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.469170050
Short name T495
Test name
Test status
Simulation time 629914348 ps
CPU time 22.2 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 232272 kb
Host smart-5256a8d2-d484-4154-a6f6-9bd48067e888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469170050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.469170050
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1213527769
Short name T365
Test name
Test status
Simulation time 1022498456 ps
CPU time 10.27 seconds
Started Apr 25 01:04:29 PM PDT 24
Finished Apr 25 01:04:40 PM PDT 24
Peak memory 199512 kb
Host smart-ee1d585b-52d2-4c6f-9cbf-e1df5e42722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213527769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1213527769
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3272661223
Short name T413
Test name
Test status
Simulation time 2755438370 ps
CPU time 141.56 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:06:53 PM PDT 24
Peak memory 199664 kb
Host smart-6fed1901-1e7c-4706-967c-4be495a12983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272661223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3272661223
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2748983531
Short name T357
Test name
Test status
Simulation time 23537382329 ps
CPU time 189.88 seconds
Started Apr 25 01:04:52 PM PDT 24
Finished Apr 25 01:08:02 PM PDT 24
Peak memory 199692 kb
Host smart-8366776f-ef23-4bf5-87fc-b51f238aa9f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748983531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2748983531
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3708990737
Short name T456
Test name
Test status
Simulation time 4529233202 ps
CPU time 71.03 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:06:03 PM PDT 24
Peak memory 199724 kb
Host smart-9ccb8311-cf85-4911-b83a-2fc43d7e3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708990737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3708990737
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.90713060
Short name T201
Test name
Test status
Simulation time 26706676 ps
CPU time 1.08 seconds
Started Apr 25 01:04:30 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 199628 kb
Host smart-c6052347-a9f2-4289-932c-229bfbddcd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90713060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.90713060
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4097648216
Short name T397
Test name
Test status
Simulation time 42581280890 ps
CPU time 830.74 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:18:42 PM PDT 24
Peak memory 240700 kb
Host smart-ffb4491d-c05c-4432-a35f-be438d9b974f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097648216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4097648216
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.4157963269
Short name T330
Test name
Test status
Simulation time 174201091 ps
CPU time 1.05 seconds
Started Apr 25 01:04:49 PM PDT 24
Finished Apr 25 01:04:51 PM PDT 24
Peak memory 198636 kb
Host smart-2aa975ef-ac93-4efb-afd4-12dd29c184fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157963269 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.4157963269
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3904140210
Short name T356
Test name
Test status
Simulation time 22281077550 ps
CPU time 401.34 seconds
Started Apr 25 01:04:44 PM PDT 24
Finished Apr 25 01:11:26 PM PDT 24
Peak memory 199600 kb
Host smart-ade9bc12-6464-4498-bde5-a2bd4edd736c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904140210 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3904140210
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2883904121
Short name T141
Test name
Test status
Simulation time 6542199468 ps
CPU time 55.36 seconds
Started Apr 25 01:04:32 PM PDT 24
Finished Apr 25 01:05:28 PM PDT 24
Peak memory 199720 kb
Host smart-f865d495-9cb2-448d-a5ca-ffffd63360b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883904121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2883904121
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1235315761
Short name T169
Test name
Test status
Simulation time 105828642 ps
CPU time 0.59 seconds
Started Apr 25 01:04:43 PM PDT 24
Finished Apr 25 01:04:44 PM PDT 24
Peak memory 195400 kb
Host smart-ba63f194-a7cd-48e7-a18e-84474d8d3ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235315761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1235315761
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2158132003
Short name T220
Test name
Test status
Simulation time 39703658 ps
CPU time 1.34 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:04:48 PM PDT 24
Peak memory 199536 kb
Host smart-17162e38-14c6-42b0-ba3e-66ed72b88cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158132003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2158132003
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1537017876
Short name T459
Test name
Test status
Simulation time 4115604527 ps
CPU time 36.51 seconds
Started Apr 25 01:04:46 PM PDT 24
Finished Apr 25 01:05:23 PM PDT 24
Peak memory 199716 kb
Host smart-08c717e6-d6f3-46fb-93e2-98558cd20f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537017876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1537017876
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.9031566
Short name T123
Test name
Test status
Simulation time 4428803126 ps
CPU time 68.24 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:05:41 PM PDT 24
Peak memory 199724 kb
Host smart-0acae93b-ea2e-424e-bb27-f767fae3cfbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9031566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.9031566
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1354675133
Short name T412
Test name
Test status
Simulation time 13893156491 ps
CPU time 116.41 seconds
Started Apr 25 01:04:45 PM PDT 24
Finished Apr 25 01:06:43 PM PDT 24
Peak memory 199740 kb
Host smart-23a8a70f-b6a3-43c6-ac69-3f1463de0af1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354675133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1354675133
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1126934736
Short name T253
Test name
Test status
Simulation time 8700375228 ps
CPU time 62.23 seconds
Started Apr 25 01:04:31 PM PDT 24
Finished Apr 25 01:05:34 PM PDT 24
Peak memory 199640 kb
Host smart-3def094c-21a1-4a36-bde8-0468be25a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126934736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1126934736
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3007032483
Short name T419
Test name
Test status
Simulation time 677084771 ps
CPU time 5.23 seconds
Started Apr 25 01:04:50 PM PDT 24
Finished Apr 25 01:04:56 PM PDT 24
Peak memory 199588 kb
Host smart-c1a69f6d-ca5a-40b6-aebc-b07d6876a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007032483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3007032483
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.977161634
Short name T263
Test name
Test status
Simulation time 103676313879 ps
CPU time 1314.4 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:26:53 PM PDT 24
Peak memory 207900 kb
Host smart-1a1ce653-eea2-4522-8367-ce66e4e91195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977161634 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.977161634
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3067446730
Short name T367
Test name
Test status
Simulation time 558538345 ps
CPU time 1.21 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 199656 kb
Host smart-6cbc078c-bcfa-4417-97f0-c92bd6da9c28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067446730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3067446730
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.4166667733
Short name T232
Test name
Test status
Simulation time 406328062470 ps
CPU time 521.23 seconds
Started Apr 25 01:04:46 PM PDT 24
Finished Apr 25 01:13:28 PM PDT 24
Peak memory 199668 kb
Host smart-f2c65e1c-3faf-415d-8bb7-e398add269b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166667733 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.4166667733
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1353303750
Short name T353
Test name
Test status
Simulation time 2169873724 ps
CPU time 65.78 seconds
Started Apr 25 01:04:39 PM PDT 24
Finished Apr 25 01:05:45 PM PDT 24
Peak memory 199760 kb
Host smart-22bd5a63-bb4c-4401-a1e2-d62827bb44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353303750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1353303750
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2293935386
Short name T215
Test name
Test status
Simulation time 14701003 ps
CPU time 0.58 seconds
Started Apr 25 01:04:41 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 194888 kb
Host smart-ae9fba78-ce3c-4936-81e3-8623fe23a35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293935386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2293935386
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4248145928
Short name T52
Test name
Test status
Simulation time 1886346939 ps
CPU time 14.96 seconds
Started Apr 25 01:04:38 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 231616 kb
Host smart-750c5a36-c29c-4477-bfda-467b6e4d1b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248145928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4248145928
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3113128048
Short name T513
Test name
Test status
Simulation time 2603341399 ps
CPU time 26.94 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 199692 kb
Host smart-72814b86-1ee5-4dbb-beab-dba27a2a2b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113128048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3113128048
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2607065385
Short name T43
Test name
Test status
Simulation time 3675169183 ps
CPU time 88.68 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:06:16 PM PDT 24
Peak memory 199684 kb
Host smart-b53a37ae-2da9-4e60-9035-77b827666a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607065385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2607065385
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3673142061
Short name T270
Test name
Test status
Simulation time 2497468305 ps
CPU time 45.59 seconds
Started Apr 25 01:04:36 PM PDT 24
Finished Apr 25 01:05:23 PM PDT 24
Peak memory 199664 kb
Host smart-5c860ba6-4544-4fd7-adf7-73fe73d2edfb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673142061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3673142061
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2994829422
Short name T458
Test name
Test status
Simulation time 57877528108 ps
CPU time 81.28 seconds
Started Apr 25 01:04:39 PM PDT 24
Finished Apr 25 01:06:01 PM PDT 24
Peak memory 199716 kb
Host smart-2eb82f46-e98c-431c-a319-898bdd92fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994829422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2994829422
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2013189746
Short name T599
Test name
Test status
Simulation time 1061308634 ps
CPU time 3.43 seconds
Started Apr 25 01:04:39 PM PDT 24
Finished Apr 25 01:04:43 PM PDT 24
Peak memory 199672 kb
Host smart-ead84df2-3ea0-43db-b57f-d860182ac058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013189746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2013189746
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3631549567
Short name T48
Test name
Test status
Simulation time 286124683619 ps
CPU time 368.54 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 232416 kb
Host smart-6f590604-044e-480a-a227-ffb75623fb9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631549567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3631549567
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2087953377
Short name T261
Test name
Test status
Simulation time 51970763 ps
CPU time 0.99 seconds
Started Apr 25 01:04:52 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 199280 kb
Host smart-cbd3b1ba-b94d-4f48-b045-e176441f7310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087953377 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2087953377
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3183654933
Short name T237
Test name
Test status
Simulation time 30111342148 ps
CPU time 431.72 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:12:09 PM PDT 24
Peak memory 199688 kb
Host smart-c8a7240f-82ac-4165-a7d3-f5db998e72b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183654933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3183654933
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2480606918
Short name T149
Test name
Test status
Simulation time 4065448993 ps
CPU time 53.9 seconds
Started Apr 25 01:04:41 PM PDT 24
Finished Apr 25 01:05:36 PM PDT 24
Peak memory 199276 kb
Host smart-cd6cdb38-0a64-48ff-808e-8d77d6c1c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480606918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2480606918
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.310257396
Short name T572
Test name
Test status
Simulation time 42206837 ps
CPU time 0.59 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 195296 kb
Host smart-e34b962c-69cd-4bbf-9f95-df9a6ad6414b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310257396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.310257396
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1823171927
Short name T19
Test name
Test status
Simulation time 13702645227 ps
CPU time 41.84 seconds
Started Apr 25 01:04:40 PM PDT 24
Finished Apr 25 01:05:22 PM PDT 24
Peak memory 224196 kb
Host smart-082694e8-aeba-40a4-9ec5-f8a9cef9da55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823171927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1823171927
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1633137541
Short name T554
Test name
Test status
Simulation time 6544566389 ps
CPU time 51.73 seconds
Started Apr 25 01:04:45 PM PDT 24
Finished Apr 25 01:05:37 PM PDT 24
Peak memory 199712 kb
Host smart-8d3e01c4-244b-4fa0-8f26-f358fb306bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633137541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1633137541
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.639091597
Short name T121
Test name
Test status
Simulation time 3969590735 ps
CPU time 55.17 seconds
Started Apr 25 01:04:38 PM PDT 24
Finished Apr 25 01:05:34 PM PDT 24
Peak memory 199728 kb
Host smart-8f105315-cbb2-4cdb-b994-d3e8fd215c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639091597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.639091597
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3874728306
Short name T296
Test name
Test status
Simulation time 2816880251 ps
CPU time 151.27 seconds
Started Apr 25 01:04:40 PM PDT 24
Finished Apr 25 01:07:12 PM PDT 24
Peak memory 199272 kb
Host smart-f4ad52f4-b787-4fe2-85d9-00a5bd07a91a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874728306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3874728306
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2900853016
Short name T266
Test name
Test status
Simulation time 2683381392 ps
CPU time 76.97 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:06:14 PM PDT 24
Peak memory 199604 kb
Host smart-e5fc2cc8-3878-493b-88cf-23b52c1d64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900853016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2900853016
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2452580485
Short name T388
Test name
Test status
Simulation time 1555721166 ps
CPU time 4.99 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:04:48 PM PDT 24
Peak memory 199672 kb
Host smart-169757b4-64a6-4ce6-8922-46404ad48e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452580485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2452580485
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3162565918
Short name T68
Test name
Test status
Simulation time 70198238599 ps
CPU time 824.97 seconds
Started Apr 25 01:04:45 PM PDT 24
Finished Apr 25 01:18:31 PM PDT 24
Peak memory 224324 kb
Host smart-2bc2b674-21f8-4f6f-b21b-6d660080c27f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162565918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3162565918
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1407079440
Short name T198
Test name
Test status
Simulation time 48660641 ps
CPU time 1.11 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 199304 kb
Host smart-f686f538-3dba-439f-9475-b7b5a756509c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407079440 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1407079440
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.511344010
Short name T471
Test name
Test status
Simulation time 45677248382 ps
CPU time 433.22 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:12:06 PM PDT 24
Peak memory 199576 kb
Host smart-0a863db8-5859-4cac-a7c1-def989ec066f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511344010 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.511344010
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3005774891
Short name T27
Test name
Test status
Simulation time 8007392397 ps
CPU time 63 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:05:50 PM PDT 24
Peak memory 199736 kb
Host smart-ee1dc117-8271-484a-bfd3-0c4fa5096a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005774891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3005774891
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.397315793
Short name T21
Test name
Test status
Simulation time 12014506 ps
CPU time 0.58 seconds
Started Apr 25 01:03:40 PM PDT 24
Finished Apr 25 01:03:41 PM PDT 24
Peak memory 195052 kb
Host smart-54b7a947-210a-479a-92cf-b22545ab9226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397315793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.397315793
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3822326641
Short name T464
Test name
Test status
Simulation time 3756062125 ps
CPU time 36.65 seconds
Started Apr 25 01:03:34 PM PDT 24
Finished Apr 25 01:04:11 PM PDT 24
Peak memory 210116 kb
Host smart-51ac62dd-c1f2-4e1d-b2e0-fe2546634fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822326641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3822326641
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3190374139
Short name T6
Test name
Test status
Simulation time 1762972674 ps
CPU time 12.72 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:03:57 PM PDT 24
Peak memory 199728 kb
Host smart-2d28a2d5-8d9a-4651-b24f-35be140ec0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190374139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3190374139
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.945570149
Short name T342
Test name
Test status
Simulation time 46198420 ps
CPU time 0.74 seconds
Started Apr 25 01:03:49 PM PDT 24
Finished Apr 25 01:03:51 PM PDT 24
Peak memory 197756 kb
Host smart-32127cd7-de61-4edb-b13f-6f4683cd29c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945570149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.945570149
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4209215372
Short name T386
Test name
Test status
Simulation time 8723511063 ps
CPU time 27.06 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:04:01 PM PDT 24
Peak memory 199708 kb
Host smart-186eb629-7fea-4e64-80b3-3608e53a4a14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209215372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4209215372
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3980845761
Short name T338
Test name
Test status
Simulation time 5856901303 ps
CPU time 86.43 seconds
Started Apr 25 01:03:39 PM PDT 24
Finished Apr 25 01:05:07 PM PDT 24
Peak memory 199788 kb
Host smart-fe1eec71-73ef-4366-9140-60eb78a7bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980845761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3980845761
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1781000102
Short name T37
Test name
Test status
Simulation time 193371580 ps
CPU time 0.94 seconds
Started Apr 25 01:03:46 PM PDT 24
Finished Apr 25 01:03:48 PM PDT 24
Peak memory 218880 kb
Host smart-b9895487-f6c9-44e2-bae1-febffe4bcb95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781000102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1781000102
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1098397310
Short name T540
Test name
Test status
Simulation time 2660097855 ps
CPU time 7.28 seconds
Started Apr 25 01:03:36 PM PDT 24
Finished Apr 25 01:03:44 PM PDT 24
Peak memory 199720 kb
Host smart-ce20f4cb-bdb5-470c-897d-5dbc6c8fbc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098397310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1098397310
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1506836970
Short name T31
Test name
Test status
Simulation time 48292823108 ps
CPU time 650.87 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:14:36 PM PDT 24
Peak memory 199744 kb
Host smart-07be746c-0139-45ce-b070-94a09301faf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506836970 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1506836970
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.58734518
Short name T252
Test name
Test status
Simulation time 81333973 ps
CPU time 0.99 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:03:46 PM PDT 24
Peak memory 199524 kb
Host smart-7d4d1f3b-0500-4c38-8fa2-29bbd089791f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58734518 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.hmac_test_hmac_vectors.58734518
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.852600200
Short name T343
Test name
Test status
Simulation time 29336772059 ps
CPU time 358.63 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:09:43 PM PDT 24
Peak memory 199456 kb
Host smart-f10d6a69-7045-4d36-8a95-48a1bdf96b82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852600200 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.852600200
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.45152514
Short name T329
Test name
Test status
Simulation time 4887903603 ps
CPU time 83.96 seconds
Started Apr 25 01:03:28 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 199744 kb
Host smart-10d8d597-e2c5-49a0-8137-a81fb9b9f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45152514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.45152514
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.900720980
Short name T530
Test name
Test status
Simulation time 14692932 ps
CPU time 0.63 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:04 PM PDT 24
Peak memory 195348 kb
Host smart-11774a52-f9b7-4f1f-af86-f2076e605ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900720980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.900720980
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1574110032
Short name T568
Test name
Test status
Simulation time 651057783 ps
CPU time 24.74 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:23 PM PDT 24
Peak memory 209932 kb
Host smart-840b881a-b1ca-498e-bd8c-dadd07f262bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574110032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1574110032
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2424774860
Short name T290
Test name
Test status
Simulation time 7026673578 ps
CPU time 30.72 seconds
Started Apr 25 01:04:41 PM PDT 24
Finished Apr 25 01:05:12 PM PDT 24
Peak memory 199268 kb
Host smart-a897fd23-c12a-405f-9eed-228841fd6df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424774860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2424774860
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.724729242
Short name T369
Test name
Test status
Simulation time 983010719 ps
CPU time 58.88 seconds
Started Apr 25 01:04:34 PM PDT 24
Finished Apr 25 01:05:34 PM PDT 24
Peak memory 199516 kb
Host smart-b7d2b02b-3618-4be3-94c7-be176d928682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724729242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.724729242
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.308685473
Short name T432
Test name
Test status
Simulation time 4455640692 ps
CPU time 158.9 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:07:33 PM PDT 24
Peak memory 199624 kb
Host smart-7f0d831a-4d3e-40e8-99d7-51df1f64a79f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308685473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.308685473
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1190634742
Short name T566
Test name
Test status
Simulation time 322986332 ps
CPU time 18.45 seconds
Started Apr 25 01:04:37 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 199628 kb
Host smart-959adb89-ed51-40ca-925c-87bfaaab4c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190634742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1190634742
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2403164261
Short name T404
Test name
Test status
Simulation time 307165326 ps
CPU time 5.13 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199628 kb
Host smart-dc431d52-585c-4509-a161-e538b81480b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403164261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2403164261
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.920516228
Short name T373
Test name
Test status
Simulation time 21041887731 ps
CPU time 77.52 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:06:00 PM PDT 24
Peak memory 227392 kb
Host smart-49009b27-b216-4311-ad21-eb3e2d12c6f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920516228 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.920516228
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.331019901
Short name T298
Test name
Test status
Simulation time 113829902 ps
CPU time 1.27 seconds
Started Apr 25 01:05:00 PM PDT 24
Finished Apr 25 01:05:02 PM PDT 24
Peak memory 199636 kb
Host smart-a47ade9c-d8b5-42e7-8a2a-049914344702
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331019901 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.331019901
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.210477750
Short name T199
Test name
Test status
Simulation time 34712668236 ps
CPU time 435.47 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:12:12 PM PDT 24
Peak memory 199660 kb
Host smart-28e5cc4b-0c5f-471f-a3b4-14a4eb74098f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210477750 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.210477750
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.757450219
Short name T450
Test name
Test status
Simulation time 3363999228 ps
CPU time 17.34 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:05:11 PM PDT 24
Peak memory 199712 kb
Host smart-d6da4420-995f-440a-90ca-d58f403d1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757450219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.757450219
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2409082611
Short name T385
Test name
Test status
Simulation time 35958348 ps
CPU time 0.57 seconds
Started Apr 25 01:04:54 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 194288 kb
Host smart-11da851a-5b3e-4d36-9f29-c8c4993b2208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409082611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2409082611
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1323040268
Short name T304
Test name
Test status
Simulation time 3041019440 ps
CPU time 56.42 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:55 PM PDT 24
Peak memory 232460 kb
Host smart-3e471d68-adde-438f-9745-eba88a43ca78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323040268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1323040268
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2147100837
Short name T368
Test name
Test status
Simulation time 558135264 ps
CPU time 27.18 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 199632 kb
Host smart-dfea29b6-71e2-4804-b278-e9ef264fc163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147100837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2147100837
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3997667612
Short name T138
Test name
Test status
Simulation time 540819453 ps
CPU time 5.29 seconds
Started Apr 25 01:05:01 PM PDT 24
Finished Apr 25 01:05:07 PM PDT 24
Peak memory 199700 kb
Host smart-9e19d7bc-4b0e-4af3-af8f-9cab26361a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997667612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3997667612
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3433143594
Short name T507
Test name
Test status
Simulation time 4931670727 ps
CPU time 94.14 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:06:22 PM PDT 24
Peak memory 199700 kb
Host smart-d485ef80-d19c-4df9-bd77-bfb11b9b7a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433143594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3433143594
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2905906900
Short name T517
Test name
Test status
Simulation time 451028143 ps
CPU time 2.07 seconds
Started Apr 25 01:04:43 PM PDT 24
Finished Apr 25 01:04:46 PM PDT 24
Peak memory 199672 kb
Host smart-f8657697-f2c6-4dc8-9214-8e474ee4c07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905906900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2905906900
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.939147103
Short name T311
Test name
Test status
Simulation time 86005585409 ps
CPU time 826.23 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:18:29 PM PDT 24
Peak memory 224344 kb
Host smart-98458055-e3a1-4ec0-83e1-97e825763afb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939147103 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.939147103
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3908331053
Short name T299
Test name
Test status
Simulation time 97448913 ps
CPU time 1.06 seconds
Started Apr 25 01:04:40 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 199576 kb
Host smart-1348cbe0-dbae-42dc-b44b-1ff7f7f5d556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908331053 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3908331053
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2563799173
Short name T189
Test name
Test status
Simulation time 154893725730 ps
CPU time 484.62 seconds
Started Apr 25 01:04:39 PM PDT 24
Finished Apr 25 01:12:45 PM PDT 24
Peak memory 199496 kb
Host smart-2b15c021-10f6-4636-ba9c-2c27fcf4b30c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563799173 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2563799173
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2650338661
Short name T128
Test name
Test status
Simulation time 41675569420 ps
CPU time 62.87 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:05:59 PM PDT 24
Peak memory 199704 kb
Host smart-8ce31458-f82b-4f18-a7d3-0d4bc9c7e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650338661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2650338661
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1703994024
Short name T147
Test name
Test status
Simulation time 40109313 ps
CPU time 0.59 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 195136 kb
Host smart-044d3020-1b31-427c-98d0-6122524e9496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703994024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1703994024
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.801748957
Short name T504
Test name
Test status
Simulation time 1333157569 ps
CPU time 30.53 seconds
Started Apr 25 01:04:42 PM PDT 24
Finished Apr 25 01:05:13 PM PDT 24
Peak memory 232404 kb
Host smart-3755d5a3-7bf1-4116-bcab-e5a8e640a3eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801748957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.801748957
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1785004550
Short name T192
Test name
Test status
Simulation time 259564256 ps
CPU time 5.02 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:10 PM PDT 24
Peak memory 199684 kb
Host smart-e5c82994-e9fc-4702-8e8d-2ec9984ff7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785004550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1785004550
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1645315699
Short name T130
Test name
Test status
Simulation time 1825622840 ps
CPU time 112.86 seconds
Started Apr 25 01:04:41 PM PDT 24
Finished Apr 25 01:06:34 PM PDT 24
Peak memory 199724 kb
Host smart-f21fa6f0-52c2-4b13-8881-e1b34adc2152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645315699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1645315699
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.954603746
Short name T312
Test name
Test status
Simulation time 1856930036 ps
CPU time 12.89 seconds
Started Apr 25 01:04:44 PM PDT 24
Finished Apr 25 01:04:58 PM PDT 24
Peak memory 199596 kb
Host smart-e9931c3f-845c-4808-9adb-0bdd1930fb7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954603746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.954603746
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2556947596
Short name T512
Test name
Test status
Simulation time 2292412823 ps
CPU time 74.33 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:06:10 PM PDT 24
Peak memory 199660 kb
Host smart-c6d482f8-c3ea-4908-a02d-30f873425f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556947596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2556947596
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3899514247
Short name T177
Test name
Test status
Simulation time 331857995 ps
CPU time 1.8 seconds
Started Apr 25 01:04:52 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 199620 kb
Host smart-6957b21b-884b-4588-8a34-0a6078466696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899514247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3899514247
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.492892654
Short name T294
Test name
Test status
Simulation time 212328729894 ps
CPU time 330.12 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:10:29 PM PDT 24
Peak memory 199700 kb
Host smart-f95af6b1-fcf1-4416-81d5-0ba0d5044fe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492892654 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.492892654
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2748212270
Short name T408
Test name
Test status
Simulation time 121977889 ps
CPU time 1.24 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 199656 kb
Host smart-b6004461-6a8f-4727-9fed-4b9ee3aa8183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748212270 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2748212270
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2702907362
Short name T127
Test name
Test status
Simulation time 170898444208 ps
CPU time 535.81 seconds
Started Apr 25 01:04:43 PM PDT 24
Finished Apr 25 01:13:39 PM PDT 24
Peak memory 199652 kb
Host smart-0aa5378c-4a53-4e5d-b2da-b6e2ae6512a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702907362 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2702907362
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3160625138
Short name T190
Test name
Test status
Simulation time 1832912101 ps
CPU time 94.48 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:06:34 PM PDT 24
Peak memory 199700 kb
Host smart-afbc59fa-58d9-4b62-bf4f-ac689d5a5733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160625138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3160625138
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.998245383
Short name T314
Test name
Test status
Simulation time 24144628 ps
CPU time 0.6 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 195376 kb
Host smart-097bd14a-eba0-47d9-a39f-9da3d395b3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998245383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.998245383
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.829419345
Short name T414
Test name
Test status
Simulation time 5855062282 ps
CPU time 44.48 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:05:41 PM PDT 24
Peak memory 213040 kb
Host smart-90064caf-8618-42e8-9853-a29957ffafef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829419345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.829419345
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.173408406
Short name T228
Test name
Test status
Simulation time 1461806198 ps
CPU time 32.06 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:32 PM PDT 24
Peak memory 199628 kb
Host smart-cbae994d-ca91-4e51-b88c-4a02e6e870a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173408406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.173408406
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2687013969
Short name T547
Test name
Test status
Simulation time 1366082186 ps
CPU time 84.49 seconds
Started Apr 25 01:04:50 PM PDT 24
Finished Apr 25 01:06:15 PM PDT 24
Peak memory 199656 kb
Host smart-ca935e0f-4b5d-4ff2-96ac-e20e2181b341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687013969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2687013969
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2541358166
Short name T145
Test name
Test status
Simulation time 4402055769 ps
CPU time 79.67 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:06:19 PM PDT 24
Peak memory 199704 kb
Host smart-c23a5299-dc7a-4c19-886c-070dd4f30f68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541358166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2541358166
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.794130030
Short name T480
Test name
Test status
Simulation time 6906089954 ps
CPU time 31.99 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:32 PM PDT 24
Peak memory 199688 kb
Host smart-370d00a6-8caa-4042-8673-37191cb62fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794130030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.794130030
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1715380851
Short name T433
Test name
Test status
Simulation time 736152112 ps
CPU time 5.38 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:05:12 PM PDT 24
Peak memory 199612 kb
Host smart-b9ae0215-5ed4-41e8-9f0f-194bc84cefc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715380851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1715380851
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.143378089
Short name T595
Test name
Test status
Simulation time 2668594391 ps
CPU time 48.18 seconds
Started Apr 25 01:04:50 PM PDT 24
Finished Apr 25 01:05:39 PM PDT 24
Peak memory 199720 kb
Host smart-aa28fcd4-8cd3-4237-8e0b-fc340afa63a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143378089 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.143378089
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.848165104
Short name T362
Test name
Test status
Simulation time 212045669 ps
CPU time 1.25 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 199648 kb
Host smart-04dd412e-1ffa-491d-a07e-ab0869f2e50b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848165104 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.848165104
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.162803285
Short name T374
Test name
Test status
Simulation time 60615915672 ps
CPU time 429.38 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:12:13 PM PDT 24
Peak memory 199660 kb
Host smart-bb73838a-7523-4030-897f-909598f606ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162803285 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.162803285
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4169289129
Short name T193
Test name
Test status
Simulation time 3865768164 ps
CPU time 26.43 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:05:15 PM PDT 24
Peak memory 199716 kb
Host smart-23292af4-a6ae-4f9d-a27c-7bcd29dfcfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169289129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4169289129
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.921094367
Short name T417
Test name
Test status
Simulation time 60675146 ps
CPU time 0.6 seconds
Started Apr 25 01:04:47 PM PDT 24
Finished Apr 25 01:04:49 PM PDT 24
Peak memory 195240 kb
Host smart-5fbcfdd7-1f67-4a40-a68c-260bc5137137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921094367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.921094367
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3323575436
Short name T463
Test name
Test status
Simulation time 1001510857 ps
CPU time 8.46 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 207796 kb
Host smart-f09542bc-dcd5-4a90-b4c9-bb529e535524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323575436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3323575436
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.71175090
Short name T358
Test name
Test status
Simulation time 2245061339 ps
CPU time 8.49 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 199756 kb
Host smart-d44df679-4f25-4f42-a275-b9fd8d7f8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71175090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.71175090
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.260268768
Short name T405
Test name
Test status
Simulation time 6846182829 ps
CPU time 182.46 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:07:51 PM PDT 24
Peak memory 199736 kb
Host smart-e8777924-886b-421b-9029-e92d44c1711d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260268768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.260268768
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2432790038
Short name T444
Test name
Test status
Simulation time 6355199030 ps
CPU time 84.44 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:06:18 PM PDT 24
Peak memory 199712 kb
Host smart-4083c71a-9e16-4ee0-be11-3f911d1b6c52
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432790038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2432790038
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.859805845
Short name T532
Test name
Test status
Simulation time 892168443 ps
CPU time 13.43 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:12 PM PDT 24
Peak memory 199652 kb
Host smart-b9e2aee7-bdc8-4ddc-addc-5f82928c3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859805845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.859805845
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3770112134
Short name T440
Test name
Test status
Simulation time 4923136111 ps
CPU time 7.01 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 199700 kb
Host smart-22aeb888-3514-49ba-a195-29fed3a2f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770112134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3770112134
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1692234319
Short name T103
Test name
Test status
Simulation time 16961903286 ps
CPU time 648.4 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:15:40 PM PDT 24
Peak memory 199660 kb
Host smart-491a2f1b-68f3-41f8-9694-de45f01fdace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692234319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1692234319
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3396157486
Short name T240
Test name
Test status
Simulation time 105766688 ps
CPU time 1.04 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:05:07 PM PDT 24
Peak memory 199096 kb
Host smart-bdfbad5f-cdda-4742-a2ce-a2d227467514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396157486 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3396157486
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3867008375
Short name T39
Test name
Test status
Simulation time 47050290457 ps
CPU time 436.27 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:12:16 PM PDT 24
Peak memory 199672 kb
Host smart-ecd69849-5d71-47e9-933f-9696915e410f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867008375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3867008375
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.441077361
Short name T591
Test name
Test status
Simulation time 169860946 ps
CPU time 2.54 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:02 PM PDT 24
Peak memory 199620 kb
Host smart-6114e9f4-add7-4878-9869-519a6987c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441077361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.441077361
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2147604037
Short name T327
Test name
Test status
Simulation time 171718149 ps
CPU time 6.97 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:06 PM PDT 24
Peak memory 207856 kb
Host smart-fa9d8041-f38d-40ed-abf2-c835c8893547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147604037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2147604037
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3941787200
Short name T125
Test name
Test status
Simulation time 5672691358 ps
CPU time 40.77 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:05:48 PM PDT 24
Peak memory 199660 kb
Host smart-89929c21-3506-4fd1-bba6-028cf548327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941787200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3941787200
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.912620832
Short name T272
Test name
Test status
Simulation time 3759447119 ps
CPU time 107.03 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:06:44 PM PDT 24
Peak memory 199668 kb
Host smart-d3d66a1e-4cb5-4c66-941a-05a25f2556ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912620832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.912620832
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1081033198
Short name T171
Test name
Test status
Simulation time 7241137422 ps
CPU time 26.6 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:31 PM PDT 24
Peak memory 199660 kb
Host smart-96ffea75-09b1-4979-ac42-c636a8221df3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081033198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1081033198
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1161270323
Short name T596
Test name
Test status
Simulation time 1644814855 ps
CPU time 48.69 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:05:49 PM PDT 24
Peak memory 199648 kb
Host smart-00bcbc04-f217-4923-9e54-3f167be01df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161270323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1161270323
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2878399597
Short name T246
Test name
Test status
Simulation time 61656342 ps
CPU time 1.23 seconds
Started Apr 25 01:04:48 PM PDT 24
Finished Apr 25 01:04:50 PM PDT 24
Peak memory 199632 kb
Host smart-398d9a82-0fbd-4718-99cd-2e3703b1ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878399597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2878399597
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3765892246
Short name T17
Test name
Test status
Simulation time 108022139894 ps
CPU time 1882.32 seconds
Started Apr 25 01:05:08 PM PDT 24
Finished Apr 25 01:36:31 PM PDT 24
Peak memory 232496 kb
Host smart-1716f14a-1370-452c-bd1f-9261ae0c322a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765892246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3765892246
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3408321171
Short name T516
Test name
Test status
Simulation time 242904588 ps
CPU time 1.19 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:00 PM PDT 24
Peak memory 199596 kb
Host smart-09d743c2-453a-4d42-b4e0-985a8ff086a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408321171 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3408321171
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2460222213
Short name T34
Test name
Test status
Simulation time 35298967360 ps
CPU time 471.99 seconds
Started Apr 25 01:05:06 PM PDT 24
Finished Apr 25 01:12:59 PM PDT 24
Peak memory 199688 kb
Host smart-b556fa69-f7af-4327-9e0a-a6c478b27f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460222213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2460222213
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1083811305
Short name T536
Test name
Test status
Simulation time 114275351 ps
CPU time 3.43 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:02 PM PDT 24
Peak memory 199644 kb
Host smart-fcc2fd2d-2e0c-42cd-aa7c-9986b7ad732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083811305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1083811305
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3020351810
Short name T509
Test name
Test status
Simulation time 12103622 ps
CPU time 0.59 seconds
Started Apr 25 01:05:04 PM PDT 24
Finished Apr 25 01:05:06 PM PDT 24
Peak memory 195364 kb
Host smart-5bacd7d6-5a7f-440f-ab0b-6f83852b987e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020351810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3020351810
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2748089677
Short name T563
Test name
Test status
Simulation time 277293768 ps
CPU time 6.04 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:05:03 PM PDT 24
Peak memory 224240 kb
Host smart-a92ba4ec-fdd7-43bc-a02d-301ad167695f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748089677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2748089677
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1387381820
Short name T492
Test name
Test status
Simulation time 6567339341 ps
CPU time 30.65 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:05:44 PM PDT 24
Peak memory 199720 kb
Host smart-e39388b9-4c7d-4576-a6d0-7b5e0d5c406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387381820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1387381820
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1791957326
Short name T122
Test name
Test status
Simulation time 1195125365 ps
CPU time 35.91 seconds
Started Apr 25 01:04:56 PM PDT 24
Finished Apr 25 01:05:33 PM PDT 24
Peak memory 199632 kb
Host smart-e9942a5f-02c0-4dca-9d0a-6abe054fdcfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791957326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1791957326
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1089276807
Short name T555
Test name
Test status
Simulation time 25902901778 ps
CPU time 187.84 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:08:15 PM PDT 24
Peak memory 199732 kb
Host smart-21b0071c-e04a-4bcf-93f2-39c580def2d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089276807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1089276807
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2155491888
Short name T205
Test name
Test status
Simulation time 837814558 ps
CPU time 13.88 seconds
Started Apr 25 01:04:54 PM PDT 24
Finished Apr 25 01:05:09 PM PDT 24
Peak memory 199644 kb
Host smart-1a69c89b-0353-47f6-ab5d-10620a0e7343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155491888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2155491888
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1507805696
Short name T134
Test name
Test status
Simulation time 260141471 ps
CPU time 3.54 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:05:00 PM PDT 24
Peak memory 199716 kb
Host smart-27593478-b7ea-481c-9ccf-0d35aa0a46cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507805696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1507805696
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1741795702
Short name T71
Test name
Test status
Simulation time 417599185995 ps
CPU time 1305.92 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:26:45 PM PDT 24
Peak memory 199728 kb
Host smart-192f707e-e4e5-4bc5-8622-c127437c4844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741795702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1741795702
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4141559824
Short name T255
Test name
Test status
Simulation time 58564794 ps
CPU time 1.14 seconds
Started Apr 25 01:04:54 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 199268 kb
Host smart-3e33162f-4e94-4f14-ae16-c6ea191a023a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141559824 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4141559824
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.740978803
Short name T154
Test name
Test status
Simulation time 147710569978 ps
CPU time 495.01 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:13:13 PM PDT 24
Peak memory 199676 kb
Host smart-7e35132f-3455-4d1c-b5e7-1fff7c423439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740978803 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.740978803
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.898609026
Short name T585
Test name
Test status
Simulation time 344386932 ps
CPU time 15.26 seconds
Started Apr 25 01:05:13 PM PDT 24
Finished Apr 25 01:05:30 PM PDT 24
Peak memory 199660 kb
Host smart-071775d0-efdf-468d-b264-2d39f77f8cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898609026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.898609026
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3917569644
Short name T538
Test name
Test status
Simulation time 11156775 ps
CPU time 0.61 seconds
Started Apr 25 01:04:51 PM PDT 24
Finished Apr 25 01:04:53 PM PDT 24
Peak memory 194324 kb
Host smart-0570e0f3-808f-46bc-bdaa-e12a3fa84520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917569644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3917569644
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4045268926
Short name T573
Test name
Test status
Simulation time 816493754 ps
CPU time 30.24 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:35 PM PDT 24
Peak memory 224252 kb
Host smart-1a44feab-53e7-4372-81ad-690420224158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045268926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4045268926
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3909459826
Short name T170
Test name
Test status
Simulation time 3847025786 ps
CPU time 49 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:05:43 PM PDT 24
Peak memory 199760 kb
Host smart-3a94dec5-9c78-4f8f-af2b-679be531c18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909459826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3909459826
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1535715317
Short name T222
Test name
Test status
Simulation time 2316943321 ps
CPU time 132.12 seconds
Started Apr 25 01:05:06 PM PDT 24
Finished Apr 25 01:07:20 PM PDT 24
Peak memory 199644 kb
Host smart-9b346842-e29f-4125-b496-087f1724fc60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535715317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1535715317
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3412743352
Short name T443
Test name
Test status
Simulation time 11884746066 ps
CPU time 131.09 seconds
Started Apr 25 01:04:55 PM PDT 24
Finished Apr 25 01:07:07 PM PDT 24
Peak memory 199760 kb
Host smart-0551f8dd-6854-4eed-98fb-629e7aae5c3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412743352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3412743352
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.349747090
Short name T597
Test name
Test status
Simulation time 2797035966 ps
CPU time 27.84 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:31 PM PDT 24
Peak memory 199744 kb
Host smart-701dd220-9582-440e-9ecd-42e973a602a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349747090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.349747090
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1691178105
Short name T230
Test name
Test status
Simulation time 48536064 ps
CPU time 1.75 seconds
Started Apr 25 01:04:54 PM PDT 24
Finished Apr 25 01:04:57 PM PDT 24
Peak memory 199688 kb
Host smart-34c1df45-a2fa-4340-b2b1-82acb1290115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691178105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1691178105
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.62033002
Short name T69
Test name
Test status
Simulation time 481113535414 ps
CPU time 498.88 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:13:22 PM PDT 24
Peak memory 199712 kb
Host smart-cc36951d-4728-45d1-8783-5819985435ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62033002 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.62033002
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3145543862
Short name T150
Test name
Test status
Simulation time 32207923 ps
CPU time 0.97 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:04:59 PM PDT 24
Peak memory 199092 kb
Host smart-06fb7c2e-006a-4868-a3b2-71c81817d4ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145543862 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3145543862
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2736839146
Short name T292
Test name
Test status
Simulation time 44327494984 ps
CPU time 473.42 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:12:58 PM PDT 24
Peak memory 199636 kb
Host smart-967151a1-d006-4bbc-8f2b-d2d87ae6ee6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736839146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2736839146
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1497610016
Short name T447
Test name
Test status
Simulation time 1957133061 ps
CPU time 23.58 seconds
Started Apr 25 01:05:04 PM PDT 24
Finished Apr 25 01:05:29 PM PDT 24
Peak memory 199680 kb
Host smart-4cf7c883-8249-420b-95cd-4a4fca953f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497610016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1497610016
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3759842246
Short name T335
Test name
Test status
Simulation time 11389029 ps
CPU time 0.6 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:04 PM PDT 24
Peak memory 194264 kb
Host smart-8d4387a6-4bfd-4878-b49c-653bfc400ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759842246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3759842246
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2350618767
Short name T53
Test name
Test status
Simulation time 2920892418 ps
CPU time 25.93 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:30 PM PDT 24
Peak memory 226264 kb
Host smart-77b961f5-4fda-41a6-a109-103edc6455fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350618767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2350618767
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3024459924
Short name T442
Test name
Test status
Simulation time 9671586440 ps
CPU time 36.05 seconds
Started Apr 25 01:05:00 PM PDT 24
Finished Apr 25 01:05:37 PM PDT 24
Peak memory 199680 kb
Host smart-3b65cc41-e311-45d1-9090-013de73c92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024459924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3024459924
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3794284657
Short name T375
Test name
Test status
Simulation time 2269416516 ps
CPU time 67.6 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:06:12 PM PDT 24
Peak memory 199744 kb
Host smart-1b003848-77b5-4d85-9bee-640c03d6094b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794284657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3794284657
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.39591499
Short name T420
Test name
Test status
Simulation time 878396629 ps
CPU time 11.84 seconds
Started Apr 25 01:04:57 PM PDT 24
Finished Apr 25 01:05:10 PM PDT 24
Peak memory 199504 kb
Host smart-dd0022b7-aad0-42ba-b8ee-401076128dc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.39591499
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.802863218
Short name T437
Test name
Test status
Simulation time 1276578294 ps
CPU time 26.49 seconds
Started Apr 25 01:05:05 PM PDT 24
Finished Apr 25 01:05:33 PM PDT 24
Peak memory 199676 kb
Host smart-faf49116-8f89-433f-84db-d51e05807bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802863218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.802863218
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2385300933
Short name T302
Test name
Test status
Simulation time 82499374 ps
CPU time 1.65 seconds
Started Apr 25 01:04:53 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 199664 kb
Host smart-6e9eead8-3056-44ba-b40a-fc8973439cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385300933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2385300933
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3014154649
Short name T13
Test name
Test status
Simulation time 46928122568 ps
CPU time 1210.16 seconds
Started Apr 25 01:05:07 PM PDT 24
Finished Apr 25 01:25:18 PM PDT 24
Peak memory 215600 kb
Host smart-e67c869b-0993-4ca0-8d29-808014c0ad7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014154649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3014154649
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1930772628
Short name T578
Test name
Test status
Simulation time 73279733 ps
CPU time 1.26 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199624 kb
Host smart-9b5b51fe-a8f0-49ed-a9b6-dd94cff65a13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930772628 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1930772628
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1855238883
Short name T181
Test name
Test status
Simulation time 40111616152 ps
CPU time 490.01 seconds
Started Apr 25 01:05:01 PM PDT 24
Finished Apr 25 01:13:12 PM PDT 24
Peak memory 199548 kb
Host smart-6a49ddd2-01e7-4e00-97b4-82f178a56641
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855238883 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1855238883
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1571848067
Short name T276
Test name
Test status
Simulation time 2233254590 ps
CPU time 36.4 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:36 PM PDT 24
Peak memory 199712 kb
Host smart-b7860a6f-2545-42d0-b64d-95296aa0be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571848067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1571848067
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4214014305
Short name T174
Test name
Test status
Simulation time 17798537 ps
CPU time 0.59 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 195024 kb
Host smart-732ac474-d13b-4841-8af0-a5ad5eb3d8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214014305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4214014305
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.209162173
Short name T54
Test name
Test status
Simulation time 1931869283 ps
CPU time 6.74 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:05:07 PM PDT 24
Peak memory 199616 kb
Host smart-5c7b7ffc-dddd-4bfc-aeb4-37acc4cbf819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209162173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.209162173
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2689479750
Short name T2
Test name
Test status
Simulation time 13875257490 ps
CPU time 30.06 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:33 PM PDT 24
Peak memory 199764 kb
Host smart-8c9eb535-0024-4f18-ada3-a9d60e9f70e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689479750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2689479750
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1042617556
Short name T460
Test name
Test status
Simulation time 6365634451 ps
CPU time 95.6 seconds
Started Apr 25 01:05:03 PM PDT 24
Finished Apr 25 01:06:40 PM PDT 24
Peak memory 199700 kb
Host smart-157cd264-983f-48b9-84c9-e6653aee3f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042617556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1042617556
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1131752783
Short name T575
Test name
Test status
Simulation time 597491887 ps
CPU time 7.91 seconds
Started Apr 25 01:05:24 PM PDT 24
Finished Apr 25 01:05:32 PM PDT 24
Peak memory 199584 kb
Host smart-582f7d4b-416d-44b8-888c-dd87515f90ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131752783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1131752783
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2917790334
Short name T245
Test name
Test status
Simulation time 8947807719 ps
CPU time 26.43 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:29 PM PDT 24
Peak memory 199616 kb
Host smart-53f53c50-df72-4b2f-a948-317da0f3f6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917790334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2917790334
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2585812353
Short name T351
Test name
Test status
Simulation time 74944423 ps
CPU time 1.49 seconds
Started Apr 25 01:05:02 PM PDT 24
Finished Apr 25 01:05:05 PM PDT 24
Peak memory 199652 kb
Host smart-0f37290a-022f-47a2-bbaa-4b746c1b4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585812353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2585812353
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3743222674
Short name T531
Test name
Test status
Simulation time 31941072035 ps
CPU time 820.93 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:18:41 PM PDT 24
Peak memory 232204 kb
Host smart-18865b08-15d2-435f-b3a9-0f7c5d60effb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743222674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3743222674
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.770069189
Short name T185
Test name
Test status
Simulation time 61299342 ps
CPU time 1.37 seconds
Started Apr 25 01:04:58 PM PDT 24
Finished Apr 25 01:05:01 PM PDT 24
Peak memory 199616 kb
Host smart-f0bce4bb-3646-4ac2-b898-9b51fe5a06a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770069189 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.770069189
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2468613060
Short name T137
Test name
Test status
Simulation time 13659401096 ps
CPU time 372.66 seconds
Started Apr 25 01:04:59 PM PDT 24
Finished Apr 25 01:11:13 PM PDT 24
Peak memory 199692 kb
Host smart-4eed1f12-1eb6-4e71-8397-81e8f564c5c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468613060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2468613060
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.612675786
Short name T499
Test name
Test status
Simulation time 2852610526 ps
CPU time 15.27 seconds
Started Apr 25 01:05:10 PM PDT 24
Finished Apr 25 01:05:27 PM PDT 24
Peak memory 199704 kb
Host smart-305d9bb1-c98f-4ac9-ad80-c646d942b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612675786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.612675786
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3106489384
Short name T455
Test name
Test status
Simulation time 32829390 ps
CPU time 0.59 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:03:39 PM PDT 24
Peak memory 194244 kb
Host smart-e251f453-7940-4b13-b451-52f74b35ee3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106489384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3106489384
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1233752296
Short name T515
Test name
Test status
Simulation time 6246954273 ps
CPU time 59.65 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:04:34 PM PDT 24
Peak memory 226344 kb
Host smart-4cb5ca62-1580-4ef1-9a13-3079af40d7bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233752296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1233752296
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.710741513
Short name T208
Test name
Test status
Simulation time 114467251 ps
CPU time 1.42 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:03:45 PM PDT 24
Peak memory 199440 kb
Host smart-b7ffaf48-64d0-433d-8df7-b356009d725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710741513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.710741513
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.193831713
Short name T482
Test name
Test status
Simulation time 88928582 ps
CPU time 1.33 seconds
Started Apr 25 01:03:32 PM PDT 24
Finished Apr 25 01:03:34 PM PDT 24
Peak memory 198584 kb
Host smart-bb64616a-d961-4d9d-9ce6-9154b370b919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193831713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.193831713
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1836306913
Short name T76
Test name
Test status
Simulation time 4644500472 ps
CPU time 79.66 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:05:04 PM PDT 24
Peak memory 199752 kb
Host smart-814a568f-55e7-4598-8bd3-2eb3068ac39a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836306913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1836306913
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2559144725
Short name T235
Test name
Test status
Simulation time 19786626689 ps
CPU time 94.86 seconds
Started Apr 25 01:03:48 PM PDT 24
Finished Apr 25 01:05:24 PM PDT 24
Peak memory 199772 kb
Host smart-1d42865c-7736-4583-9037-db341af1480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559144725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2559144725
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4087279752
Short name T188
Test name
Test status
Simulation time 935957440 ps
CPU time 1.92 seconds
Started Apr 25 01:03:32 PM PDT 24
Finished Apr 25 01:03:35 PM PDT 24
Peak memory 199684 kb
Host smart-3e5363e7-163f-4657-8e35-e7ac0971af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087279752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4087279752
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3601452692
Short name T74
Test name
Test status
Simulation time 135121136781 ps
CPU time 509.72 seconds
Started Apr 25 01:03:34 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 229712 kb
Host smart-c0e37042-1bee-4292-b21a-9d30e62cebfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601452692 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3601452692
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.600385322
Short name T381
Test name
Test status
Simulation time 128665583 ps
CPU time 1.19 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:03:35 PM PDT 24
Peak memory 199656 kb
Host smart-173f09f8-e231-4d9e-801a-cac2910abf37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600385322 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.600385322
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1409770980
Short name T488
Test name
Test status
Simulation time 17913986522 ps
CPU time 452.99 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 199628 kb
Host smart-361cc08a-3aec-48c1-b1c5-4d5e72df5012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409770980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1409770980
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.207840015
Short name T319
Test name
Test status
Simulation time 1037209984 ps
CPU time 20.19 seconds
Started Apr 25 01:03:42 PM PDT 24
Finished Apr 25 01:04:03 PM PDT 24
Peak memory 199716 kb
Host smart-5ba6ad96-1b21-46be-a334-1f1b72568cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207840015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.207840015
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1015996382
Short name T256
Test name
Test status
Simulation time 15197060 ps
CPU time 0.63 seconds
Started Apr 25 01:03:39 PM PDT 24
Finished Apr 25 01:03:41 PM PDT 24
Peak memory 195460 kb
Host smart-c4f9f8fb-4282-4a5c-aae6-1855c1f35709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015996382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1015996382
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.626212397
Short name T370
Test name
Test status
Simulation time 1910271766 ps
CPU time 20.27 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:04:18 PM PDT 24
Peak memory 239916 kb
Host smart-e7416af1-2bc0-4c59-b440-903b3c6804b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626212397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.626212397
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3959553796
Short name T44
Test name
Test status
Simulation time 5934659549 ps
CPU time 31.82 seconds
Started Apr 25 01:04:00 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 199760 kb
Host smart-b7220f4d-dfa5-47b3-b1c5-b9211ceec9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959553796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3959553796
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.374435872
Short name T500
Test name
Test status
Simulation time 6101297167 ps
CPU time 91.52 seconds
Started Apr 25 01:03:39 PM PDT 24
Finished Apr 25 01:05:12 PM PDT 24
Peak memory 199696 kb
Host smart-42e8636b-e599-487f-823f-05e92b5ea609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374435872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.374435872
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1816411665
Short name T537
Test name
Test status
Simulation time 1210566116 ps
CPU time 22.23 seconds
Started Apr 25 01:03:40 PM PDT 24
Finished Apr 25 01:04:03 PM PDT 24
Peak memory 199716 kb
Host smart-1ec410e1-fb09-4d77-8455-07b6899e44dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816411665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1816411665
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1105406290
Short name T552
Test name
Test status
Simulation time 50313093 ps
CPU time 1.07 seconds
Started Apr 25 01:03:32 PM PDT 24
Finished Apr 25 01:03:34 PM PDT 24
Peak memory 199604 kb
Host smart-04b4197f-5b36-41b1-9b70-75d52e0ce076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105406290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1105406290
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3271684060
Short name T165
Test name
Test status
Simulation time 36432817571 ps
CPU time 1950.37 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:36:16 PM PDT 24
Peak memory 240676 kb
Host smart-965582be-63d8-42c9-90a4-aebb13baab74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271684060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3271684060
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.909464351
Short name T594
Test name
Test status
Simulation time 169617174 ps
CPU time 1.13 seconds
Started Apr 25 01:03:42 PM PDT 24
Finished Apr 25 01:03:44 PM PDT 24
Peak memory 199160 kb
Host smart-07964091-753a-4b3f-be6a-878289a4cf71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909464351 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.909464351
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.864046033
Short name T212
Test name
Test status
Simulation time 16580975558 ps
CPU time 446.77 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 199664 kb
Host smart-02b33e06-0c67-42cb-9939-c911deecd35f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864046033 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.864046033
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4079447783
Short name T503
Test name
Test status
Simulation time 30069170783 ps
CPU time 78.37 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:05:16 PM PDT 24
Peak memory 199680 kb
Host smart-1a777e65-ab61-45ed-8e53-8a340e43db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079447783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4079447783
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4265870647
Short name T416
Test name
Test status
Simulation time 60719921 ps
CPU time 0.6 seconds
Started Apr 25 01:03:53 PM PDT 24
Finished Apr 25 01:03:55 PM PDT 24
Peak memory 195068 kb
Host smart-479cc102-267e-482c-89d5-74779980a0b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265870647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4265870647
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1154886802
Short name T587
Test name
Test status
Simulation time 755203463 ps
CPU time 34.33 seconds
Started Apr 25 01:03:57 PM PDT 24
Finished Apr 25 01:04:33 PM PDT 24
Peak memory 238488 kb
Host smart-224e3cb1-a5d3-4a6d-9621-b4165380de16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154886802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1154886802
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.568815140
Short name T448
Test name
Test status
Simulation time 191147196 ps
CPU time 1.27 seconds
Started Apr 25 01:03:34 PM PDT 24
Finished Apr 25 01:03:36 PM PDT 24
Peak memory 199536 kb
Host smart-88b6815a-1357-47b4-9a70-4b70603075a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568815140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.568815140
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2957449611
Short name T183
Test name
Test status
Simulation time 11211063812 ps
CPU time 170.28 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:06:30 PM PDT 24
Peak memory 199728 kb
Host smart-7b090835-20ea-4a0f-b1be-1c8a67fa222b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957449611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2957449611
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3961675348
Short name T273
Test name
Test status
Simulation time 30234917534 ps
CPU time 169.8 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:06:34 PM PDT 24
Peak memory 199512 kb
Host smart-e67076eb-5a19-474f-86c9-b30633fbf9c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961675348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3961675348
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2403054464
Short name T178
Test name
Test status
Simulation time 24680851148 ps
CPU time 123.17 seconds
Started Apr 25 01:03:43 PM PDT 24
Finished Apr 25 01:05:48 PM PDT 24
Peak memory 199708 kb
Host smart-4bbddcf7-0229-45d1-88ae-6bf6a2ff3951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403054464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2403054464
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1731148625
Short name T316
Test name
Test status
Simulation time 243529204 ps
CPU time 3.85 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:03:49 PM PDT 24
Peak memory 199648 kb
Host smart-b3538c59-d853-46cd-84b9-452fa965786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731148625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1731148625
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1857363802
Short name T275
Test name
Test status
Simulation time 1314626851 ps
CPU time 15.24 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:06 PM PDT 24
Peak memory 199648 kb
Host smart-16542e91-3206-41c7-9105-cd3a157c0590
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857363802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1857363802
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.4049189477
Short name T550
Test name
Test status
Simulation time 1090284701 ps
CPU time 1.31 seconds
Started Apr 25 01:03:41 PM PDT 24
Finished Apr 25 01:03:44 PM PDT 24
Peak memory 199684 kb
Host smart-e431ff25-2521-456a-aa80-5685f0eafc85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049189477 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.4049189477
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1694044522
Short name T415
Test name
Test status
Simulation time 82066396020 ps
CPU time 523.34 seconds
Started Apr 25 01:03:42 PM PDT 24
Finished Apr 25 01:12:27 PM PDT 24
Peak memory 199668 kb
Host smart-3235f07f-b02f-45ad-b1d9-8d04dcc5918c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694044522 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1694044522
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4078209548
Short name T187
Test name
Test status
Simulation time 15690070204 ps
CPU time 56.1 seconds
Started Apr 25 01:03:50 PM PDT 24
Finished Apr 25 01:04:47 PM PDT 24
Peak memory 199768 kb
Host smart-884273e1-56fb-4309-9218-71192cd8be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078209548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4078209548
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2465759190
Short name T472
Test name
Test status
Simulation time 36658669 ps
CPU time 0.68 seconds
Started Apr 25 01:03:36 PM PDT 24
Finished Apr 25 01:03:38 PM PDT 24
Peak memory 195188 kb
Host smart-f5f06054-12ad-45da-8b81-d48f459d70a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465759190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2465759190
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3031479693
Short name T223
Test name
Test status
Simulation time 1461465833 ps
CPU time 27.01 seconds
Started Apr 25 01:03:54 PM PDT 24
Finished Apr 25 01:04:22 PM PDT 24
Peak memory 215184 kb
Host smart-7db35a67-e76f-4ddc-ad83-d5071dd7c21f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031479693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3031479693
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.879366346
Short name T574
Test name
Test status
Simulation time 7875034262 ps
CPU time 28.25 seconds
Started Apr 25 01:03:56 PM PDT 24
Finished Apr 25 01:04:25 PM PDT 24
Peak memory 199712 kb
Host smart-90a2e22d-1491-4190-8fdc-969a64f5a949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879366346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.879366346
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2842642481
Short name T333
Test name
Test status
Simulation time 9678316818 ps
CPU time 130.93 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:05:50 PM PDT 24
Peak memory 199736 kb
Host smart-005af28f-1d7c-4ec9-9ab5-6e86188de14e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842642481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2842642481
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3166523399
Short name T484
Test name
Test status
Simulation time 555931830 ps
CPU time 7.5 seconds
Started Apr 25 01:04:08 PM PDT 24
Finished Apr 25 01:04:16 PM PDT 24
Peak memory 199524 kb
Host smart-24346fe6-ed54-4f4c-81da-74f877575190
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166523399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3166523399
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2699433304
Short name T202
Test name
Test status
Simulation time 769175015 ps
CPU time 15.96 seconds
Started Apr 25 01:03:44 PM PDT 24
Finished Apr 25 01:04:01 PM PDT 24
Peak memory 199672 kb
Host smart-4ed00276-0a98-4914-bcbf-65e78af34982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699433304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2699433304
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1570049131
Short name T57
Test name
Test status
Simulation time 1177277161 ps
CPU time 2.38 seconds
Started Apr 25 01:03:55 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 199608 kb
Host smart-84c1a53a-9cfd-427a-9ebf-5137c4dca1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570049131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1570049131
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3869683762
Short name T156
Test name
Test status
Simulation time 55832649 ps
CPU time 1.12 seconds
Started Apr 25 01:03:33 PM PDT 24
Finished Apr 25 01:03:35 PM PDT 24
Peak memory 199596 kb
Host smart-3fb093f2-8970-4abc-92b5-615ea2d5aade
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869683762 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3869683762
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.910510600
Short name T525
Test name
Test status
Simulation time 108789832856 ps
CPU time 469.88 seconds
Started Apr 25 01:03:49 PM PDT 24
Finished Apr 25 01:11:41 PM PDT 24
Peak memory 199652 kb
Host smart-b9565039-ab0b-4ef4-81b1-1d0b044094bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910510600 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.910510600
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1877632730
Short name T359
Test name
Test status
Simulation time 884170008 ps
CPU time 9.01 seconds
Started Apr 25 01:03:49 PM PDT 24
Finished Apr 25 01:03:59 PM PDT 24
Peak memory 199676 kb
Host smart-b6354355-3b79-4d97-860d-fdee93208d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877632730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1877632730
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4052521717
Short name T317
Test name
Test status
Simulation time 30898106 ps
CPU time 0.54 seconds
Started Apr 25 01:03:59 PM PDT 24
Finished Apr 25 01:04:01 PM PDT 24
Peak memory 195116 kb
Host smart-dc44f4da-f9b8-4038-a4eb-ff6cfb8eb6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052521717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4052521717
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2851933685
Short name T360
Test name
Test status
Simulation time 664593388 ps
CPU time 22.78 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:04:01 PM PDT 24
Peak memory 207868 kb
Host smart-a687e25e-3023-48a7-982c-836ccd7ebe20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851933685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2851933685
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2881008327
Short name T226
Test name
Test status
Simulation time 7761214357 ps
CPU time 43.93 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:04:37 PM PDT 24
Peak memory 199736 kb
Host smart-b91d4129-63a2-4569-8fe9-b6aef08edf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881008327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2881008327
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3612657530
Short name T259
Test name
Test status
Simulation time 816744369 ps
CPU time 45.21 seconds
Started Apr 25 01:03:36 PM PDT 24
Finished Apr 25 01:04:22 PM PDT 24
Peak memory 199668 kb
Host smart-aa350ac6-3ee7-434f-9e5f-6311837595d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612657530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3612657530
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2907395168
Short name T337
Test name
Test status
Simulation time 11346002686 ps
CPU time 103.97 seconds
Started Apr 25 01:03:52 PM PDT 24
Finished Apr 25 01:05:37 PM PDT 24
Peak memory 199748 kb
Host smart-e99de340-e3f5-4c7c-8118-d171567fec35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907395168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2907395168
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2140594543
Short name T387
Test name
Test status
Simulation time 33028140084 ps
CPU time 136.16 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:05:54 PM PDT 24
Peak memory 199732 kb
Host smart-f6b64d6e-1e43-4d87-9d85-9bed6a99bbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140594543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2140594543
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.566170566
Short name T354
Test name
Test status
Simulation time 162839548 ps
CPU time 1.72 seconds
Started Apr 25 01:03:38 PM PDT 24
Finished Apr 25 01:03:41 PM PDT 24
Peak memory 199692 kb
Host smart-6b88d672-b27e-4bfa-9722-39fa1cffdd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566170566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.566170566
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.85749681
Short name T451
Test name
Test status
Simulation time 138983504831 ps
CPU time 657.06 seconds
Started Apr 25 01:03:46 PM PDT 24
Finished Apr 25 01:14:44 PM PDT 24
Peak memory 232412 kb
Host smart-80ff0e42-eab5-46fa-be3a-89f27e12e07f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85749681 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.85749681
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3996038961
Short name T313
Test name
Test status
Simulation time 110924795 ps
CPU time 1.26 seconds
Started Apr 25 01:04:04 PM PDT 24
Finished Apr 25 01:04:07 PM PDT 24
Peak memory 199588 kb
Host smart-1d22e574-9446-43c6-979f-6eae189676f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996038961 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3996038961
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2752389110
Short name T309
Test name
Test status
Simulation time 101787061337 ps
CPU time 456.62 seconds
Started Apr 25 01:03:47 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 199664 kb
Host smart-dba15c17-69ac-474f-b099-428a9edf2620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752389110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.2752389110
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.30040549
Short name T26
Test name
Test status
Simulation time 5161437885 ps
CPU time 50.21 seconds
Started Apr 25 01:03:37 PM PDT 24
Finished Apr 25 01:04:29 PM PDT 24
Peak memory 199724 kb
Host smart-600b3bda-58a8-4eb4-8224-ec8f841c06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30040549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.30040549
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.1212410478
Short name T8
Test name
Test status
Simulation time 46600547717 ps
CPU time 1146.34 seconds
Started Apr 25 01:05:11 PM PDT 24
Finished Apr 25 01:24:21 PM PDT 24
Peak memory 216176 kb
Host smart-a24b110e-2431-47b1-a755-399441108f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212410478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.1212410478
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.2251053422
Short name T66
Test name
Test status
Simulation time 696387113543 ps
CPU time 3302.16 seconds
Started Apr 25 01:05:28 PM PDT 24
Finished Apr 25 02:00:32 PM PDT 24
Peak memory 248836 kb
Host smart-13615fbf-42ea-4e7c-8319-bb6f28f5fe64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251053422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.2251053422
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest
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