Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47188965

1

T1

787

T2

349536

T3

10224

full_word

44584321

1

T1

1773

T2

351945

T3

8091

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91772916	1			T1	2560		T2	701481		T3	18315
auto[TlIntgErrCmd]	116	1			T61	5		T62	4		T63	8
auto[TlIntgErrData]	118	1			T61	6		T62	2		T63	11
auto[TlIntgErrBoth]	136	1			T61	9		T62	4		T63	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36080518

1

T1

1072

T2

282625

T3

10680

auto[1]

55692768

1

T1

1488

T2

418856

T3

7635

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19462596	1			T1	776		T2	141732		T3	9986
auto[TlIntgErrNone]	partial	auto[1]	27726032	1			T1	11		T2	207804		T3	238
auto[TlIntgErrNone]	full_word	auto[0]	16617759	1			T1	296		T2	140893		T3	694
auto[TlIntgErrNone]	full_word	auto[1]	27966529	1			T1	1477		T2	211052		T3	7397
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T61	1		T62	1		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T61	4		T62	3		T63	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T106	1		T100	2		T102	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T100	1		T101	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T61	5		T63	5		T106	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T61	1		T62	2		T63	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T63	1		T100	1		T101	4
auto[TlIntgErrData]	full_word	auto[1]	6	1			T63	1		T100	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T61	6		T62	1		T63	4
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T61	2		T62	3		T63	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T61	1		T105	1		T107	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T108	1		T101	2		T102	1