Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	444427046	3260663	0	0
intr_enable_rd_A	444427046	3097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444427046	3260663	0	0
T6	697243	302005	0	0
T7	0	64376	0	0
T8	0	13286	0	0
T9	0	431227	0	0
T12	531447	214544	0	0
T13	976530	0	0	0
T18	1386	0	0	0
T40	94543	0	0	0
T41	104646	0	0	0
T57	268864	0	0	0
T58	6363	0	0	0
T59	4124	0	0	0
T60	74744	0	0	0
T67	0	128881	0	0
T68	0	325554	0	0
T69	0	34911	0	0
T70	0	19263	0	0
T71	0	165498	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444427046	3097	0	0
T2	735743	47	0	0
T3	41526	0	0	0
T4	779203	0	0	0
T5	109347	0	0	0
T15	4883	0	0	0
T16	2633	0	0	0
T23	46124	0	0	0
T24	120821	0	0	0
T28	0	30	0	0
T29	59602	0	0	0
T30	1511	0	0	0
T43	0	52	0	0
T50	0	45	0	0
T72	0	15	0	0
T73	0	19	0	0
T74	0	69	0	0
T75	0	8	0	0
T76	0	15	0	0
T77	0	12	0	0