Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38858362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41748493

1

T1

39432

T2

1

T3

36687

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32105703	1			T1	36365		T2	1		T3	32274
values[0x0]	22603937	1			T1	20137		T2	2		T3	21251
values[0x1]	25897215	1			T1	22946		T2	2		T3	26183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28530799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52076056

1

T1

49041

T2

1

T3

48243

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	262234	1			T1	356		T3	303		T4	608
valid_sources[0x01]	281520	1			T1	330		T3	285		T4	3305
valid_sources[0x02]	312587	1			T1	290		T3	324		T4	2147
valid_sources[0x03]	269089	1			T1	287		T3	320		T4	957
valid_sources[0x04]	656976	1			T1	310		T3	343		T4	693
valid_sources[0x05]	268922	1			T1	300		T3	318		T4	351
valid_sources[0x06]	271082	1			T1	364		T3	314		T4	1057
valid_sources[0x07]	292292	1			T1	300		T3	310		T4	4115
valid_sources[0x08]	296932	1			T1	322		T3	313		T4	915
valid_sources[0x09]	300513	1			T1	334		T3	348		T4	306
valid_sources[0x0a]	273936	1			T1	344		T3	286		T4	607
valid_sources[0x0b]	288810	1			T1	324		T3	318		T4	340
valid_sources[0x0c]	261988	1			T1	324		T3	305		T4	1944
valid_sources[0x0d]	277018	1			T1	288		T3	349		T4	784
valid_sources[0x0e]	616699	1			T1	337		T3	304		T4	508
valid_sources[0x0f]	639882	1			T1	277		T3	336		T4	369
valid_sources[0x10]	654885	1			T1	286		T3	318		T4	670
valid_sources[0x11]	280550	1			T1	246		T3	293		T4	636
valid_sources[0x12]	281558	1			T1	243		T3	338		T4	503
valid_sources[0x13]	266817	1			T1	373		T3	309		T4	493
valid_sources[0x14]	271091	1			T1	361		T3	337		T4	403
valid_sources[0x15]	276093	1			T1	306		T3	332		T4	414
valid_sources[0x16]	274102	1			T1	291		T3	310		T4	447
valid_sources[0x17]	269957	1			T1	318		T3	270		T4	633
valid_sources[0x18]	286222	1			T1	277		T3	333		T4	5260
valid_sources[0x19]	291716	1			T1	322		T3	314		T4	2417
valid_sources[0x1a]	284337	1			T1	339		T3	306		T4	7892
valid_sources[0x1b]	289487	1			T1	293		T3	277		T4	630
valid_sources[0x1c]	662631	1			T1	294		T3	311		T4	1012
valid_sources[0x1d]	265102	1			T1	283		T3	299		T4	612
valid_sources[0x1e]	302360	1			T1	291		T3	325		T4	2336
valid_sources[0x1f]	279990	1			T1	358		T3	327		T4	576
valid_sources[0x20]	278146	1			T1	337		T3	322		T4	5226
valid_sources[0x21]	293667	1			T1	312		T3	354		T4	1625
valid_sources[0x22]	286418	1			T1	335		T3	291		T4	5355
valid_sources[0x23]	290509	1			T1	349		T3	302		T4	10608
valid_sources[0x24]	263506	1			T1	293		T3	337		T4	440
valid_sources[0x25]	268009	1			T1	323		T3	272		T4	297
valid_sources[0x26]	269185	1			T1	361		T3	315		T4	2199
valid_sources[0x27]	273666	1			T1	311		T3	312		T4	386
valid_sources[0x28]	263787	1			T1	313		T3	342		T4	557
valid_sources[0x29]	276631	1			T1	261		T3	376		T4	3953
valid_sources[0x2a]	688160	1			T1	305		T3	312		T4	458
valid_sources[0x2b]	277796	1			T1	279		T3	293		T4	365
valid_sources[0x2c]	278321	1			T1	320		T3	311		T4	314
valid_sources[0x2d]	276469	1			T1	270		T3	309		T4	549
valid_sources[0x2e]	301521	1			T1	299		T3	312		T4	883
valid_sources[0x2f]	1027075	1			T1	292		T3	285		T4	499
valid_sources[0x30]	309107	1			T1	331		T3	314		T4	429
valid_sources[0x31]	283269	1			T1	290		T3	308		T4	367
valid_sources[0x32]	300731	1			T1	254		T3	274		T4	364
valid_sources[0x33]	300647	1			T1	348		T3	312		T4	1329
valid_sources[0x34]	271971	1			T1	318		T3	306		T4	740
valid_sources[0x35]	266637	1			T1	364		T3	286		T4	422
valid_sources[0x36]	284998	1			T1	317		T3	314		T4	4113
valid_sources[0x37]	269469	1			T1	323		T3	305		T4	484
valid_sources[0x38]	264922	1			T1	362		T3	286		T4	3559
valid_sources[0x39]	278946	1			T1	359		T2	5		T3	313
valid_sources[0x3a]	272827	1			T1	327		T3	312		T4	498
valid_sources[0x3b]	316171	1			T1	345		T3	359		T4	487
valid_sources[0x3c]	277133	1			T1	271		T3	298		T4	1323
valid_sources[0x3d]	269654	1			T1	314		T3	348		T4	644
valid_sources[0x3e]	260602	1			T1	316		T3	369		T4	438
valid_sources[0x3f]	264531	1			T1	340		T3	322		T4	332
valid_sources[0x40]	269069	1			T1	247		T3	331		T4	411
valid_sources[0x41]	274797	1			T1	328		T3	300		T4	965
valid_sources[0x42]	289819	1			T1	295		T3	288		T4	936
valid_sources[0x43]	267469	1			T1	236		T3	315		T4	562
valid_sources[0x44]	262617	1			T1	317		T3	273		T4	506
valid_sources[0x45]	263348	1			T1	342		T3	337		T4	1932
valid_sources[0x46]	645103	1			T1	342		T3	329		T4	545
valid_sources[0x47]	272183	1			T1	312		T3	315		T4	512
valid_sources[0x48]	301221	1			T1	296		T3	278		T4	515
valid_sources[0x49]	274335	1			T1	337		T3	305		T4	4075
valid_sources[0x4a]	301564	1			T1	292		T3	319		T4	493
valid_sources[0x4b]	264417	1			T1	305		T3	310		T4	547
valid_sources[0x4c]	280869	1			T1	377		T3	307		T4	1932
valid_sources[0x4d]	271255	1			T1	360		T3	318		T4	1288
valid_sources[0x4e]	280932	1			T1	305		T3	332		T4	356
valid_sources[0x4f]	300763	1			T1	342		T3	299		T4	1490
valid_sources[0x50]	270342	1			T1	329		T3	306		T4	2186
valid_sources[0x51]	263911	1			T1	291		T3	333		T4	429
valid_sources[0x52]	265371	1			T1	311		T3	323		T4	305
valid_sources[0x53]	261708	1			T1	280		T3	271		T4	501
valid_sources[0x54]	279520	1			T1	297		T3	358		T4	552
valid_sources[0x55]	260555	1			T1	337		T3	288		T4	289
valid_sources[0x56]	266965	1			T1	288		T3	340		T4	203
valid_sources[0x57]	687116	1			T1	295		T3	302		T4	2700
valid_sources[0x58]	291903	1			T1	261		T3	324		T4	606
valid_sources[0x59]	313551	1			T1	281		T3	345		T4	546
valid_sources[0x5a]	266709	1			T1	308		T3	295		T4	686
valid_sources[0x5b]	266887	1			T1	301		T3	310		T4	447
valid_sources[0x5c]	290935	1			T1	277		T3	305		T4	1378
valid_sources[0x5d]	274132	1			T1	324		T3	296		T4	465
valid_sources[0x5e]	266673	1			T1	307		T3	328		T4	367
valid_sources[0x5f]	286193	1			T1	300		T3	302		T4	2324
valid_sources[0x60]	289401	1			T1	307		T3	287		T4	349
valid_sources[0x61]	644634	1			T1	307		T3	314		T4	361
valid_sources[0x62]	296527	1			T1	292		T3	317		T4	2320
valid_sources[0x63]	658496	1			T1	303		T3	327		T4	423
valid_sources[0x64]	265633	1			T1	302		T3	338		T4	622
valid_sources[0x65]	275592	1			T1	281		T3	294		T4	1785
valid_sources[0x66]	658057	1			T1	263		T3	289		T4	567
valid_sources[0x67]	288864	1			T1	299		T3	298		T4	341
valid_sources[0x68]	291402	1			T1	326		T3	346		T4	495
valid_sources[0x69]	284516	1			T1	302		T3	348		T4	4946
valid_sources[0x6a]	312666	1			T1	295		T3	317		T4	309
valid_sources[0x6b]	269069	1			T1	309		T3	319		T4	4381
valid_sources[0x6c]	265673	1			T1	321		T3	346		T4	589
valid_sources[0x6d]	276524	1			T1	325		T3	310		T4	627
valid_sources[0x6e]	286167	1			T1	295		T3	314		T4	5222
valid_sources[0x6f]	270664	1			T1	312		T3	309		T4	1534
valid_sources[0x70]	293503	1			T1	311		T3	314		T4	3082
valid_sources[0x71]	274568	1			T1	363		T3	351		T4	593
valid_sources[0x72]	291284	1			T1	332		T3	305		T4	374
valid_sources[0x73]	625224	1			T1	305		T3	320		T4	352
valid_sources[0x74]	602957	1			T1	328		T3	279		T4	252
valid_sources[0x75]	277021	1			T1	273		T3	331		T4	460
valid_sources[0x76]	271874	1			T1	296		T3	306		T4	1106
valid_sources[0x77]	270740	1			T1	274		T3	371		T4	611
valid_sources[0x78]	264864	1			T1	296		T3	319		T4	1493
valid_sources[0x79]	269560	1			T1	346		T3	286		T4	667
valid_sources[0x7a]	296920	1			T1	352		T3	291		T4	422
valid_sources[0x7b]	264118	1			T1	358		T3	282		T4	1506
valid_sources[0x7c]	269813	1			T1	351		T3	303		T4	3841
valid_sources[0x7d]	276075	1			T1	328		T3	319		T4	396
valid_sources[0x7e]	262974	1			T1	325		T3	307		T4	403
valid_sources[0x7f]	348118	1			T1	284		T3	284		T4	391
valid_sources[0x80]	264078	1			T1	287		T3	295		T4	783

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15431573

1

T1

18242

T2

1

T3

16148

values[0x0]

all_enables

biggest_size

13834118

1

T1

11259

T3

10898

T4

52321

values[0x1]

all_enables

biggest_size

12482802

1

T1

9931

T3

9641

T4

47325