Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43468125

1

T1

40016

T2

4

T3

43021

full_word

42049051

1

T1

39432

T2

1

T3

36687

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85516786	1			T1	79448		T2	5		T3	79708
auto[TlIntgErrCmd]	136	1			T56	6		T57	8		T58	6
auto[TlIntgErrData]	119	1			T56	3		T57	5		T58	2
auto[TlIntgErrBoth]	135	1			T56	1		T57	7		T58	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33655304

1

T1

36365

T2

1

T3

32274

auto[1]

51861872

1

T1

43083

T2

4

T3

47434

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18105591	1			T1	18123		T3	16126		T4	95397
auto[TlIntgErrNone]	partial	auto[1]	25362188	1			T1	21893		T2	4		T3	26895
auto[TlIntgErrNone]	full_word	auto[0]	15549557	1			T1	18242		T2	1		T3	16148
auto[TlIntgErrNone]	full_word	auto[1]	26499450	1			T1	21190		T3	20539		T4	102170
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T56	1		T57	2		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T56	4		T57	4		T58	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T56	1		T104	1		T62	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	2		T104	1		T106	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T57	4		T58	1		T103	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T56	2		T57	1		T58	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T103	1		T101	2		T107	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T56	1		T104	1		T108	3
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T57	3		T103	3		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T56	1		T57	3		T58	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T62	1		T101	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T57	1		T106	1		T62	1