Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38448895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40982008

1

T2

8978

T3

218038

T4

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31821306	1			T1	1		T2	659		T3	171521
values[0x0]	22161496	1			T2	4645		T3	117396		T4	117
values[0x1]	25448101	1			T2	5139		T3	129994		T4	140

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28218576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51212327

1

T1

1

T2

9539

T3

267672

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1461675	1			T3	1641		T6	329		T5	110
valid_sources[0x01]	269336	1			T3	1600		T6	290		T5	147
valid_sources[0x02]	284271	1			T3	1750		T6	298		T5	123
valid_sources[0x03]	252353	1			T3	1666		T6	375		T5	114
valid_sources[0x04]	302007	1			T3	1716		T6	326		T5	106
valid_sources[0x05]	292608	1			T3	1637		T6	310		T5	117
valid_sources[0x06]	282958	1			T3	1649		T6	381		T5	106
valid_sources[0x07]	275484	1			T3	1744		T6	376		T5	111
valid_sources[0x08]	280105	1			T3	1587		T6	283		T5	95
valid_sources[0x09]	283468	1			T3	1717		T6	333		T5	132
valid_sources[0x0a]	262359	1			T3	1605		T6	385		T5	138
valid_sources[0x0b]	261327	1			T3	1589		T6	353		T5	113
valid_sources[0x0c]	281617	1			T3	1568		T6	353		T5	119
valid_sources[0x0d]	269898	1			T3	1695		T6	332		T5	115
valid_sources[0x0e]	669966	1			T3	1585		T6	393		T5	88
valid_sources[0x0f]	279081	1			T3	1668		T6	422		T5	110
valid_sources[0x10]	260608	1			T3	1632		T6	349		T5	116
valid_sources[0x11]	280557	1			T3	1687		T6	354		T5	91
valid_sources[0x12]	274026	1			T3	1720		T6	334		T5	112
valid_sources[0x13]	284494	1			T3	1632		T6	358		T5	112
valid_sources[0x14]	255523	1			T3	1636		T6	395		T5	119
valid_sources[0x15]	297543	1			T3	1581		T6	348		T5	140
valid_sources[0x16]	342808	1			T3	1607		T6	360		T5	129
valid_sources[0x17]	339335	1			T3	1662		T6	318		T5	122
valid_sources[0x18]	275076	1			T3	1764		T6	368		T5	131
valid_sources[0x19]	268436	1			T3	1660		T6	345		T5	97
valid_sources[0x1a]	282359	1			T3	1655		T6	335		T5	141
valid_sources[0x1b]	296551	1			T3	1645		T6	407		T5	99
valid_sources[0x1c]	279875	1			T3	1681		T6	334		T5	116
valid_sources[0x1d]	285633	1			T3	1585		T6	367		T5	91
valid_sources[0x1e]	276083	1			T3	1538		T6	397		T5	87
valid_sources[0x1f]	271049	1			T3	1725		T6	376		T5	129
valid_sources[0x20]	264756	1			T3	1545		T6	319		T5	120
valid_sources[0x21]	289565	1			T3	1674		T6	335		T5	97
valid_sources[0x22]	298797	1			T3	1676		T6	382		T5	129
valid_sources[0x23]	258397	1			T3	1603		T6	347		T5	96
valid_sources[0x24]	266115	1			T3	1517		T6	371		T5	101
valid_sources[0x25]	644766	1			T3	1645		T6	336		T5	107
valid_sources[0x26]	269272	1			T3	1719		T6	368		T5	102
valid_sources[0x27]	304913	1			T2	2499		T3	1633		T6	340
valid_sources[0x28]	262218	1			T3	1674		T6	340		T5	120
valid_sources[0x29]	273401	1			T3	1658		T6	349		T5	109
valid_sources[0x2a]	273039	1			T3	1559		T6	333		T5	129
valid_sources[0x2b]	286208	1			T3	1540		T6	371		T5	82
valid_sources[0x2c]	262164	1			T3	1581		T6	359		T5	125
valid_sources[0x2d]	274437	1			T3	1706		T6	344		T5	103
valid_sources[0x2e]	281157	1			T3	1665		T6	344		T5	111
valid_sources[0x2f]	283749	1			T3	1689		T6	326		T5	121
valid_sources[0x30]	270366	1			T3	1707		T6	360		T5	124
valid_sources[0x31]	284051	1			T3	1584		T6	370		T5	154
valid_sources[0x32]	273389	1			T3	1603		T6	346		T5	110
valid_sources[0x33]	253171	1			T3	1643		T6	387		T5	104
valid_sources[0x34]	278291	1			T3	1649		T6	376		T5	93
valid_sources[0x35]	268035	1			T3	1751		T6	344		T5	109
valid_sources[0x36]	302650	1			T3	1606		T6	381		T5	96
valid_sources[0x37]	312594	1			T3	1550		T6	336		T5	102
valid_sources[0x38]	645558	1			T3	1628		T6	304		T5	107
valid_sources[0x39]	272751	1			T3	1760		T6	299		T5	78
valid_sources[0x3a]	281188	1			T3	1577		T6	310		T5	81
valid_sources[0x3b]	267720	1			T3	1668		T6	351		T5	102
valid_sources[0x3c]	256674	1			T3	1612		T6	348		T5	114
valid_sources[0x3d]	271565	1			T3	1639		T6	409		T5	148
valid_sources[0x3e]	265879	1			T3	1595		T6	388		T5	115
valid_sources[0x3f]	284077	1			T3	1652		T6	361		T5	113
valid_sources[0x40]	635787	1			T3	1635		T6	318		T5	100
valid_sources[0x41]	281372	1			T3	1603		T6	352		T5	95
valid_sources[0x42]	257342	1			T3	1640		T6	322		T5	115
valid_sources[0x43]	278161	1			T3	1592		T6	357		T5	112
valid_sources[0x44]	268429	1			T3	1581		T6	380		T5	110
valid_sources[0x45]	950464	1			T3	1652		T6	367		T5	136
valid_sources[0x46]	270310	1			T3	1479		T6	397		T5	120
valid_sources[0x47]	282811	1			T3	1647		T6	345		T5	139
valid_sources[0x48]	259399	1			T3	1650		T6	373		T5	85
valid_sources[0x49]	286193	1			T3	1722		T6	364		T5	134
valid_sources[0x4a]	267203	1			T3	1638		T6	363		T5	88
valid_sources[0x4b]	272521	1			T3	1664		T6	370		T5	110
valid_sources[0x4c]	274979	1			T3	1618		T6	391		T5	134
valid_sources[0x4d]	272091	1			T3	1648		T6	344		T5	117
valid_sources[0x4e]	274151	1			T3	1606		T6	323		T5	78
valid_sources[0x4f]	437840	1			T3	1679		T6	349		T5	125
valid_sources[0x50]	307519	1			T1	1		T3	1555		T6	367
valid_sources[0x51]	252830	1			T3	1683		T6	380		T5	138
valid_sources[0x52]	277753	1			T3	1614		T6	357		T5	109
valid_sources[0x53]	316759	1			T3	1531		T6	386		T5	108
valid_sources[0x54]	273016	1			T3	1626		T6	347		T5	115
valid_sources[0x55]	272111	1			T3	1540		T6	319		T5	108
valid_sources[0x56]	284064	1			T3	1707		T6	410		T5	107
valid_sources[0x57]	308075	1			T3	1623		T6	388		T5	101
valid_sources[0x58]	293610	1			T3	1667		T6	331		T5	114
valid_sources[0x59]	265515	1			T3	1623		T6	351		T5	108
valid_sources[0x5a]	250282	1			T3	1698		T6	388		T5	78
valid_sources[0x5b]	321604	1			T2	1709		T3	1545		T6	359
valid_sources[0x5c]	279540	1			T3	1658		T6	357		T5	97
valid_sources[0x5d]	292759	1			T3	1598		T6	379		T5	133
valid_sources[0x5e]	264782	1			T3	1727		T6	353		T5	103
valid_sources[0x5f]	279303	1			T3	1704		T6	344		T5	117
valid_sources[0x60]	260333	1			T3	1530		T6	320		T5	124
valid_sources[0x61]	264985	1			T3	1627		T6	292		T5	100
valid_sources[0x62]	277012	1			T3	1649		T6	384		T5	108
valid_sources[0x63]	252789	1			T3	1628		T6	304		T5	81
valid_sources[0x64]	284561	1			T3	1611		T6	353		T5	116
valid_sources[0x65]	318574	1			T3	1556		T6	389		T5	115
valid_sources[0x66]	269213	1			T3	1615		T6	340		T5	73
valid_sources[0x67]	260933	1			T3	1690		T6	282		T5	147
valid_sources[0x68]	271752	1			T3	1671		T6	336		T5	105
valid_sources[0x69]	283965	1			T3	1677		T6	370		T5	130
valid_sources[0x6a]	277698	1			T3	1567		T6	373		T5	93
valid_sources[0x6b]	299077	1			T3	1698		T6	377		T5	101
valid_sources[0x6c]	672834	1			T3	1669		T6	330		T5	117
valid_sources[0x6d]	287497	1			T3	1698		T6	378		T5	110
valid_sources[0x6e]	276813	1			T3	1691		T6	378		T5	123
valid_sources[0x6f]	276787	1			T3	1734		T6	375		T5	118
valid_sources[0x70]	268614	1			T3	1600		T6	328		T5	120
valid_sources[0x71]	274054	1			T3	1573		T6	385		T5	111
valid_sources[0x72]	265204	1			T3	1761		T6	413		T5	100
valid_sources[0x73]	277031	1			T3	1550		T6	362		T5	144
valid_sources[0x74]	255292	1			T3	1653		T6	368		T5	92
valid_sources[0x75]	270189	1			T3	1648		T6	356		T5	118
valid_sources[0x76]	598567	1			T3	1670		T6	383		T5	142
valid_sources[0x77]	293935	1			T3	1685		T6	345		T5	95
valid_sources[0x78]	343587	1			T3	1704		T6	362		T5	107
valid_sources[0x79]	278294	1			T3	1673		T4	478		T6	393
valid_sources[0x7a]	261799	1			T3	1683		T6	342		T5	97
valid_sources[0x7b]	281631	1			T3	1491		T6	417		T5	122
valid_sources[0x7c]	286966	1			T3	1699		T6	320		T5	96
valid_sources[0x7d]	258363	1			T3	1668		T6	334		T5	127
valid_sources[0x7e]	340482	1			T3	1723		T6	327		T5	88
valid_sources[0x7f]	257998	1			T3	1601		T6	372		T5	114
valid_sources[0x80]	277274	1			T3	1710		T6	385		T5	132

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15284260

1

T2

229

T3

85492

T4

113

values[0x0]

all_enables

biggest_size

13516292

1

T2

4297

T3

70048

T4

70

values[0x1]

all_enables

biggest_size

12181456

1

T2

4452

T3

62498

T4

80