Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43357448

1

T1

1

T2

1465

T3

200873

full_word

41302169

1

T2

8978

T3

218038

T4

263

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84659217	1			T1	1		T2	10443		T3	418911
auto[TlIntgErrCmd]	120	1			T51	4		T52	2		T53	6
auto[TlIntgErrData]	139	1			T51	5		T52	4		T53	11
auto[TlIntgErrBoth]	141	1			T51	1		T52	4		T53	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33472802

1

T1

1

T2

659

T3

171521

auto[1]

51186815

1

T2

9784

T3

247390

T4

257

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18061925	1			T1	1		T2	430		T3	86029
auto[TlIntgErrNone]	partial	auto[1]	25295165	1			T2	1035		T3	114844		T4	107
auto[TlIntgErrNone]	full_word	auto[0]	15410687	1			T2	229		T3	85492		T4	113
auto[TlIntgErrNone]	full_word	auto[1]	25891440	1			T2	8749		T3	132546		T4	150
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T52	1		T53	3		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T51	4		T52	1		T53	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T117	1		T118	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T114	1		T118	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T51	1		T52	1		T53	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T51	3		T52	2		T53	8
auto[TlIntgErrData]	full_word	auto[0]	11	1			T116	1		T113	1		T114	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T52	1		T53	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T51	1		T53	1		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T52	4		T53	2		T116	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T118	2		T121	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T116	2		T113	1		T58	2