Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	448438630	2803352	0	0
intr_enable_rd_A	448438630	2593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448438630	2803352	0	0
T8	955960	24192	0	0
T9	0	45821	0	0
T10	0	55480	0	0
T11	0	175459	0	0
T12	0	150704	0	0
T14	0	230963	0	0
T40	0	24456	0	0
T59	0	210735	0	0
T60	0	135082	0	0
T61	0	164732	0	0
T62	233864	0	0	0
T63	89355	0	0	0
T64	754780	0	0	0
T65	594019	0	0	0
T66	167512	0	0	0
T67	744904	0	0	0
T68	752140	0	0	0
T69	9214	0	0	0
T70	203179	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448438630	2593	0	0
T8	0	17	0	0
T17	633920	63	0	0
T40	0	29	0	0
T41	0	13	0	0
T44	104291	16	0	0
T71	0	19	0	0
T72	0	27	0	0
T73	0	16	0	0
T74	0	14	0	0
T75	0	12	0	0
T76	2761	0	0	0
T77	13237	0	0	0
T78	12734	0	0	0
T79	828	0	0	0
T80	246637	0	0	0
T81	13722	0	0	0
T82	530512	0	0	0
T83	138497	0	0	0