Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14862579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16696006

1

T1

12897

T2

98093

T3

211790

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12248626	1			T1	8656		T2	76855		T3	166741
values[0x0]	9022514	1			T1	6141		T2	53166		T3	113464
values[0x1]	10287445	1			T1	5994		T2	63322		T3	126659

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10977613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20580972

1

T1

16433

T2

124508

T3

260185

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	97303	1			T1	72		T2	704		T3	1643
valid_sources[0x01]	92683	1			T1	83		T2	766		T3	1573
valid_sources[0x02]	96144	1			T1	90		T2	794		T3	1499
valid_sources[0x03]	96821	1			T1	81		T2	794		T3	1600
valid_sources[0x04]	97955	1			T1	100		T2	755		T3	1634
valid_sources[0x05]	95170	1			T1	82		T2	755		T3	1569
valid_sources[0x06]	98808	1			T1	99		T2	789		T3	1615
valid_sources[0x07]	93691	1			T1	42		T2	815		T3	1557
valid_sources[0x08]	98209	1			T1	99		T2	765		T3	1646
valid_sources[0x09]	111232	1			T1	85		T2	711		T3	1579
valid_sources[0x0a]	95572	1			T1	96		T2	768		T3	1627
valid_sources[0x0b]	95421	1			T1	50		T2	774		T3	1610
valid_sources[0x0c]	94167	1			T1	94		T2	688		T3	1554
valid_sources[0x0d]	95236	1			T1	78		T2	748		T3	1556
valid_sources[0x0e]	94000	1			T1	58		T2	752		T3	1582
valid_sources[0x0f]	95796	1			T1	70		T2	746		T3	1609
valid_sources[0x10]	97416	1			T1	77		T2	838		T3	1582
valid_sources[0x11]	114808	1			T1	65		T2	809		T3	1658
valid_sources[0x12]	95048	1			T1	78		T2	809		T3	1579
valid_sources[0x13]	97808	1			T1	72		T2	703		T3	1552
valid_sources[0x14]	99806	1			T1	79		T2	679		T3	1520
valid_sources[0x15]	145326	1			T1	80		T2	769		T3	1570
valid_sources[0x16]	95115	1			T1	96		T2	744		T3	1593
valid_sources[0x17]	95033	1			T1	81		T2	766		T3	1573
valid_sources[0x18]	117046	1			T1	78		T2	710		T3	1482
valid_sources[0x19]	93841	1			T1	93		T2	763		T3	1588
valid_sources[0x1a]	101200	1			T1	79		T2	711		T3	1650
valid_sources[0x1b]	94217	1			T1	78		T2	838		T3	1555
valid_sources[0x1c]	121191	1			T1	96		T2	820		T3	1602
valid_sources[0x1d]	95158	1			T1	90		T2	704		T3	1618
valid_sources[0x1e]	126591	1			T1	65		T2	852		T3	1677
valid_sources[0x1f]	104033	1			T1	79		T2	767		T3	1617
valid_sources[0x20]	100673	1			T1	106		T2	774		T3	1567
valid_sources[0x21]	100612	1			T1	69		T2	778		T3	1583
valid_sources[0x22]	97050	1			T1	91		T2	706		T3	1608
valid_sources[0x23]	96620	1			T1	90		T2	796		T3	1534
valid_sources[0x24]	93869	1			T1	96		T2	734		T3	1588
valid_sources[0x25]	96408	1			T1	88		T2	729		T3	1559
valid_sources[0x26]	95966	1			T1	78		T2	754		T3	1538
valid_sources[0x27]	93783	1			T1	97		T2	783		T3	1676
valid_sources[0x28]	95721	1			T1	88		T2	838		T3	1625
valid_sources[0x29]	94131	1			T1	67		T2	681		T3	1606
valid_sources[0x2a]	95355	1			T1	73		T2	771		T3	1545
valid_sources[0x2b]	96412	1			T1	96		T2	846		T3	1592
valid_sources[0x2c]	95566	1			T1	82		T2	714		T3	1557
valid_sources[0x2d]	95453	1			T1	74		T2	761		T3	1577
valid_sources[0x2e]	93113	1			T1	83		T2	790		T3	1594
valid_sources[0x2f]	98193	1			T1	89		T2	718		T3	1558
valid_sources[0x30]	458690	1			T1	81		T2	793		T3	1559
valid_sources[0x31]	93381	1			T1	67		T2	799		T3	1587
valid_sources[0x32]	95990	1			T1	97		T2	740		T3	1632
valid_sources[0x33]	108791	1			T1	75		T2	663		T3	1535
valid_sources[0x34]	95102	1			T1	71		T2	783		T3	1611
valid_sources[0x35]	98376	1			T1	95		T2	702		T3	1635
valid_sources[0x36]	94684	1			T1	69		T2	800		T3	1554
valid_sources[0x37]	114848	1			T1	64		T2	747		T3	1529
valid_sources[0x38]	95246	1			T1	76		T2	760		T3	1636
valid_sources[0x39]	854046	1			T1	81		T2	752		T3	1602
valid_sources[0x3a]	95661	1			T1	83		T2	744		T3	1493
valid_sources[0x3b]	97133	1			T1	55		T2	733		T3	1600
valid_sources[0x3c]	96297	1			T1	70		T2	708		T3	1550
valid_sources[0x3d]	98483	1			T1	52		T2	797		T3	1710
valid_sources[0x3e]	96358	1			T1	65		T2	747		T3	1631
valid_sources[0x3f]	93737	1			T1	99		T2	785		T3	1613
valid_sources[0x40]	95965	1			T1	56		T2	737		T3	1633
valid_sources[0x41]	94914	1			T1	85		T2	745		T3	1620
valid_sources[0x42]	93785	1			T1	81		T2	768		T3	1497
valid_sources[0x43]	94848	1			T1	66		T2	784		T3	1635
valid_sources[0x44]	96352	1			T1	73		T2	721		T3	1527
valid_sources[0x45]	96624	1			T1	102		T2	782		T3	1583
valid_sources[0x46]	413323	1			T1	88		T2	766		T3	1600
valid_sources[0x47]	94262	1			T1	82		T2	765		T3	1525
valid_sources[0x48]	106596	1			T1	77		T2	797		T3	1594
valid_sources[0x49]	132084	1			T1	73		T2	756		T3	1591
valid_sources[0x4a]	98943	1			T1	62		T2	763		T3	1595
valid_sources[0x4b]	98705	1			T1	78		T2	768		T3	1544
valid_sources[0x4c]	93641	1			T1	74		T2	746		T3	1527
valid_sources[0x4d]	93962	1			T1	89		T2	736		T3	1639
valid_sources[0x4e]	96973	1			T1	75		T2	718		T3	1561
valid_sources[0x4f]	94342	1			T1	70		T2	761		T3	1703
valid_sources[0x50]	98466	1			T1	46		T2	781		T3	1624
valid_sources[0x51]	95296	1			T1	53		T2	764		T3	1544
valid_sources[0x52]	95635	1			T1	74		T2	729		T3	1646
valid_sources[0x53]	94774	1			T1	94		T2	750		T3	1590
valid_sources[0x54]	460545	1			T1	79		T2	716		T3	1494
valid_sources[0x55]	97093	1			T1	71		T2	698		T3	1580
valid_sources[0x56]	95806	1			T1	64		T2	738		T3	1536
valid_sources[0x57]	96916	1			T1	88		T2	746		T3	1704
valid_sources[0x58]	99659	1			T1	79		T2	731		T3	1729
valid_sources[0x59]	99335	1			T1	104		T2	712		T3	1545
valid_sources[0x5a]	97980	1			T1	112		T2	754		T3	1565
valid_sources[0x5b]	95517	1			T1	67		T2	768		T3	1587
valid_sources[0x5c]	94736	1			T1	93		T2	726		T3	1560
valid_sources[0x5d]	94666	1			T1	85		T2	750		T3	1576
valid_sources[0x5e]	495160	1			T1	84		T2	731		T3	1611
valid_sources[0x5f]	107381	1			T1	73		T2	748		T3	1614
valid_sources[0x60]	94731	1			T1	82		T2	745		T3	1658
valid_sources[0x61]	105958	1			T1	58		T2	709		T3	1616
valid_sources[0x62]	94338	1			T1	100		T2	768		T3	1617
valid_sources[0x63]	93022	1			T1	90		T2	756		T3	1585
valid_sources[0x64]	98921	1			T1	76		T2	720		T3	1643
valid_sources[0x65]	94106	1			T1	72		T2	731		T3	1656
valid_sources[0x66]	93595	1			T1	88		T2	707		T3	1567
valid_sources[0x67]	98055	1			T1	87		T2	725		T3	1626
valid_sources[0x68]	96374	1			T1	112		T2	733		T3	1563
valid_sources[0x69]	97700	1			T1	87		T2	796		T3	1545
valid_sources[0x6a]	490080	1			T1	59		T2	791		T3	1551
valid_sources[0x6b]	106308	1			T1	95		T2	781		T3	1595
valid_sources[0x6c]	99609	1			T1	103		T2	717		T3	1587
valid_sources[0x6d]	95062	1			T1	76		T2	768		T3	1584
valid_sources[0x6e]	93678	1			T1	68		T2	794		T3	1636
valid_sources[0x6f]	93527	1			T1	99		T2	792		T3	1511
valid_sources[0x70]	101269	1			T1	105		T2	729		T3	1566
valid_sources[0x71]	96438	1			T1	80		T2	720		T3	1560
valid_sources[0x72]	97226	1			T1	85		T2	739		T3	1606
valid_sources[0x73]	96512	1			T1	88		T2	756		T3	1526
valid_sources[0x74]	118630	1			T1	70		T2	731		T3	1584
valid_sources[0x75]	95352	1			T1	106		T2	772		T3	1563
valid_sources[0x76]	94386	1			T1	70		T2	779		T3	1594
valid_sources[0x77]	99748	1			T1	110		T2	779		T3	1582
valid_sources[0x78]	103382	1			T1	99		T2	773		T3	1557
valid_sources[0x79]	95374	1			T1	70		T2	800		T3	1502
valid_sources[0x7a]	94525	1			T1	83		T2	756		T3	1534
valid_sources[0x7b]	102817	1			T1	75		T2	732		T3	1619
valid_sources[0x7c]	93432	1			T1	97		T2	741		T3	1659
valid_sources[0x7d]	96556	1			T1	69		T2	757		T3	1619
valid_sources[0x7e]	93260	1			T1	55		T2	782		T3	1558
valid_sources[0x7f]	130226	1			T1	64		T2	791		T3	1592
valid_sources[0x80]	97143	1			T1	103		T2	701		T3	1560

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6068216

1

T1

1101

T2

35556

T3

83270

values[0x0]

all_enables

biggest_size

5587138

1

T1

5999

T2

32433

T3

67742

values[0x1]

all_enables

biggest_size

5040652

1

T1

5797

T2

30104

T3

60778