SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 24745050 | 1 | T1 | 9590 | T2 | 112524 | T3 | 332578 | ||||
auto[1] | 9457872 | 1 | T1 | 11201 | T2 | 80819 | T3 | 74286 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34202684 | 1 | T1 | 20791 | T2 | 193343 | T3 | 406864 | ||||
values[1] | 23 | 1 | T23 | 1 | T50 | 3 | T52 | 1 | ||||
values[2] | 3 | 1 | T50 | 1 | T97 | 1 | T98 | 1 | ||||
values[3] | 126 | 1 | T23 | 3 | T50 | 8 | T52 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34202677 | 1 | T1 | 20791 | T2 | 193343 | T3 | 406864 | ||||
values[1] | 25 | 1 | T50 | 2 | T99 | 1 | T59 | 1 | ||||
values[2] | 9 | 1 | T50 | 2 | T99 | 2 | T100 | 1 | ||||
values[3] | 113 | 1 | T23 | 3 | T50 | 9 | T52 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34202572 | 1 | T1 | 20791 | T2 | 193343 | T3 | 406864 | ||||
auto[TlIntgErrCmd] | 105 | 1 | T23 | 4 | T50 | 9 | T52 | 3 | ||||
auto[TlIntgErrData] | 112 | 1 | T23 | 4 | T50 | 11 | T52 | 5 | ||||
auto[TlIntgErrBoth] | 133 | 1 | T23 | 2 | T50 | 10 | T52 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |