Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17345451

1

T1

7894

T2

95250

T3

195074

full_word

16857471

1

T1

12897

T2

98093

T3

211790

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34202572	1			T1	20791		T2	193343		T3	406864
auto[TlIntgErrCmd]	105	1			T23	4		T50	9		T52	3
auto[TlIntgErrData]	112	1			T23	4		T50	11		T52	5
auto[TlIntgErrBoth]	133	1			T23	2		T50	10		T52	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13080331

1

T1

8656

T2

76855

T3

166741

auto[1]

21122591

1

T1

12135

T2

116488

T3

240123

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6948877	1			T1	7555		T2	41299		T3	83471
auto[TlIntgErrNone]	partial	auto[1]	10396257	1			T1	339		T2	53951		T3	111603
auto[TlIntgErrNone]	full_word	auto[0]	6131283	1			T1	1101		T2	35556		T3	83270
auto[TlIntgErrNone]	full_word	auto[1]	10726155	1			T1	11796		T2	62537		T3	128520
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T50	4		T99	2		T59	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T23	2		T50	4		T52	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T23	1		T50	1		T52	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T23	1		T100	1		T101	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T23	2		T50	9		T52	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T23	2		T50	2		T52	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T102	1		T97	1		T103	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T99	2		T104	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T50	3		T99	3		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T23	2		T50	7		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T59	1		T106	1		T101	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T99	1		T107	1		T108	1