Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212572632	1429666	0	0
intr_enable_rd_A	212572632	2701	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212572632	1429666	0	0
T18	0	41250	0	0
T22	407122	178366	0	0
T23	0	4	0	0
T47	14438	0	0	0
T48	54168	0	0	0
T50	0	12	0	0
T51	0	366	0	0
T54	0	312	0	0
T55	0	26386	0	0
T56	0	604	0	0
T60	0	356	0	0
T61	0	615	0	0
T62	61187	0	0	0
T63	764	0	0	0
T64	9261	0	0	0
T65	1198	0	0	0
T66	192962	0	0	0
T67	5792	0	0	0
T68	52241	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212572632	2701	0	0
T2	201089	14	0	0
T3	286183	0	0	0
T4	181936	0	0	0
T5	74528	0	0	0
T6	793744	0	0	0
T7	369973	0	0	0
T8	61977	0	0	0
T15	1012	0	0	0
T16	1398	0	0	0
T23	0	79	0	0
T27	221397	0	0	0
T55	0	14	0	0
T69	0	42	0	0
T70	0	16	0	0
T71	0	68	0	0
T72	0	18	0	0
T73	0	27	0	0
T74	0	108	0	0
T75	0	10	0	0