Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13288334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15000438

1

T1

338

T2

2

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10923746	1			T1	68		T2	1		T3	1
values[0x0]	8127620	1			T1	162		T2	6		T3	9
values[0x1]	9237406	1			T1	187		T2	5		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9820314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18468458

1

T1

369

T2

2

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	89506	1			T1	1		T5	219		T6	144
valid_sources[0x01]	109068	1			T1	1		T5	349		T6	154
valid_sources[0x02]	83857	1			T1	1		T5	374		T6	131
valid_sources[0x03]	83899	1			T1	2		T5	278		T6	141
valid_sources[0x04]	83223	1			T1	1		T5	429		T6	147
valid_sources[0x05]	88957	1			T5	349		T6	116		T7	1
valid_sources[0x06]	84612	1			T5	339		T6	123		T7	8
valid_sources[0x07]	86529	1			T1	1		T5	434		T6	133
valid_sources[0x08]	87707	1			T1	4		T5	352		T6	104
valid_sources[0x09]	84163	1			T1	4		T5	292		T6	170
valid_sources[0x0a]	95997	1			T1	1		T5	325		T6	128
valid_sources[0x0b]	84000	1			T1	2		T5	434		T6	150
valid_sources[0x0c]	81559	1			T1	2		T5	239		T6	121
valid_sources[0x0d]	83662	1			T4	803		T5	258		T6	128
valid_sources[0x0e]	84810	1			T1	1		T4	2313		T5	387
valid_sources[0x0f]	83853	1			T5	248		T6	138		T7	32
valid_sources[0x10]	85700	1			T1	1		T19	1		T5	264
valid_sources[0x11]	83635	1			T1	1		T5	300		T6	122
valid_sources[0x12]	88347	1			T5	299		T6	128		T7	16
valid_sources[0x13]	107921	1			T5	251		T6	144		T7	15
valid_sources[0x14]	83864	1			T1	2		T5	310		T6	126
valid_sources[0x15]	86681	1			T1	4		T5	250		T6	113
valid_sources[0x16]	87004	1			T5	338		T6	160		T7	7
valid_sources[0x17]	86577	1			T1	1		T4	668		T5	162
valid_sources[0x18]	83728	1			T1	3		T5	184		T6	116
valid_sources[0x19]	93574	1			T1	4		T5	404		T6	163
valid_sources[0x1a]	84542	1			T5	321		T6	113		T7	2
valid_sources[0x1b]	84445	1			T5	217		T6	141		T7	11
valid_sources[0x1c]	477572	1			T1	1		T19	1		T5	266
valid_sources[0x1d]	85487	1			T1	2		T4	2585		T5	280
valid_sources[0x1e]	97929	1			T1	2		T5	218		T6	105
valid_sources[0x1f]	88881	1			T5	224		T6	132		T7	27
valid_sources[0x20]	82708	1			T1	1		T4	146		T5	314
valid_sources[0x21]	81879	1			T1	2		T5	419		T6	158
valid_sources[0x22]	96949	1			T5	241		T6	147		T7	12
valid_sources[0x23]	81870	1			T1	2		T5	296		T6	166
valid_sources[0x24]	84000	1			T1	2		T3	1		T5	294
valid_sources[0x25]	87334	1			T1	2		T5	285		T6	158
valid_sources[0x26]	86722	1			T1	3		T5	324		T6	109
valid_sources[0x27]	82491	1			T5	293		T6	133		T34	3
valid_sources[0x28]	82439	1			T1	1		T5	217		T6	112
valid_sources[0x29]	84511	1			T1	3		T5	283		T6	153
valid_sources[0x2a]	459715	1			T1	2		T5	411		T6	138
valid_sources[0x2b]	93189	1			T2	4		T5	276		T6	132
valid_sources[0x2c]	90995	1			T1	2		T5	274		T6	149
valid_sources[0x2d]	92634	1			T1	3		T5	299		T6	160
valid_sources[0x2e]	81947	1			T1	1		T5	255		T6	201
valid_sources[0x2f]	88592	1			T1	3		T5	199		T6	126
valid_sources[0x30]	96275	1			T1	2		T5	242		T6	160
valid_sources[0x31]	106081	1			T5	292		T6	147		T7	25
valid_sources[0x32]	87621	1			T1	1		T5	332		T6	142
valid_sources[0x33]	83771	1			T1	2		T5	285		T6	163
valid_sources[0x34]	84884	1			T1	1		T5	278		T6	169
valid_sources[0x35]	101610	1			T1	3		T4	1589		T5	243
valid_sources[0x36]	433220	1			T5	332		T6	152		T7	5
valid_sources[0x37]	84304	1			T1	2		T5	384		T6	153
valid_sources[0x38]	99808	1			T5	249		T6	136		T7	12
valid_sources[0x39]	81933	1			T1	2		T5	354		T6	164
valid_sources[0x3a]	103569	1			T1	2		T5	335		T6	127
valid_sources[0x3b]	85403	1			T1	2		T5	442		T6	170
valid_sources[0x3c]	467441	1			T5	279		T6	120		T7	18
valid_sources[0x3d]	83490	1			T1	1		T5	286		T6	169
valid_sources[0x3e]	91964	1			T1	3		T5	168		T6	123
valid_sources[0x3f]	83566	1			T1	1		T5	216		T6	121
valid_sources[0x40]	94065	1			T1	1		T5	274		T6	152
valid_sources[0x41]	82302	1			T1	2		T5	284		T6	128
valid_sources[0x42]	84842	1			T1	1		T5	335		T6	162
valid_sources[0x43]	86578	1			T4	372		T5	484		T6	187
valid_sources[0x44]	92463	1			T5	372		T6	144		T7	11
valid_sources[0x45]	83955	1			T1	1		T5	272		T6	169
valid_sources[0x46]	92870	1			T1	4		T5	237		T6	150
valid_sources[0x47]	84853	1			T1	1		T5	243		T6	134
valid_sources[0x48]	80228	1			T1	1		T5	357		T6	143
valid_sources[0x49]	82448	1			T1	3		T5	435		T6	168
valid_sources[0x4a]	87178	1			T1	1		T4	1747		T5	257
valid_sources[0x4b]	84168	1			T1	3		T5	367		T6	118
valid_sources[0x4c]	90352	1			T1	2		T5	240		T6	123
valid_sources[0x4d]	88381	1			T5	252		T6	134		T7	3
valid_sources[0x4e]	84242	1			T1	3		T5	322		T6	130
valid_sources[0x4f]	94351	1			T19	2		T5	298		T6	118
valid_sources[0x50]	86120	1			T1	1		T5	306		T6	147
valid_sources[0x51]	82065	1			T1	4		T5	227		T6	126
valid_sources[0x52]	83746	1			T1	1		T5	394		T6	138
valid_sources[0x53]	86833	1			T1	1		T5	235		T6	116
valid_sources[0x54]	85576	1			T1	3		T4	490		T5	242
valid_sources[0x55]	82424	1			T2	1		T5	304		T6	156
valid_sources[0x56]	87214	1			T1	2		T5	366		T6	125
valid_sources[0x57]	85198	1			T1	3		T2	7		T5	361
valid_sources[0x58]	82934	1			T5	261		T6	175		T7	3
valid_sources[0x59]	109463	1			T1	1		T5	179		T6	155
valid_sources[0x5a]	88567	1			T1	1		T5	283		T6	124
valid_sources[0x5b]	475605	1			T19	1		T5	305		T6	123
valid_sources[0x5c]	94618	1			T1	2		T5	462		T6	158
valid_sources[0x5d]	82582	1			T1	1		T4	73		T5	259
valid_sources[0x5e]	83163	1			T1	2		T5	366		T6	155
valid_sources[0x5f]	86397	1			T1	2		T5	320		T6	151
valid_sources[0x60]	85672	1			T1	2		T5	163		T6	120
valid_sources[0x61]	87759	1			T1	1		T5	331		T6	115
valid_sources[0x62]	101857	1			T5	254		T6	142		T33	1
valid_sources[0x63]	435507	1			T1	3		T5	239		T6	136
valid_sources[0x64]	82386	1			T5	255		T6	154		T7	11
valid_sources[0x65]	84704	1			T5	240		T6	139		T7	4
valid_sources[0x66]	82041	1			T1	2		T5	254		T6	188
valid_sources[0x67]	104370	1			T1	2		T5	223		T6	142
valid_sources[0x68]	484649	1			T5	322		T6	141		T7	5
valid_sources[0x69]	82672	1			T1	3		T5	199		T6	120
valid_sources[0x6a]	90604	1			T1	6		T19	1		T5	373
valid_sources[0x6b]	101000	1			T1	2		T5	413		T6	139
valid_sources[0x6c]	85600	1			T1	1		T5	249		T6	104
valid_sources[0x6d]	92297	1			T5	305		T6	130		T7	5
valid_sources[0x6e]	105896	1			T1	1		T5	265		T6	190
valid_sources[0x6f]	90023	1			T5	350		T6	92		T7	17
valid_sources[0x70]	86880	1			T1	5		T3	3		T4	405
valid_sources[0x71]	85950	1			T1	1		T5	230		T6	129
valid_sources[0x72]	82121	1			T5	221		T6	125		T12	73
valid_sources[0x73]	83112	1			T5	223		T6	188		T7	23
valid_sources[0x74]	82767	1			T1	5		T5	227		T6	161
valid_sources[0x75]	84391	1			T1	2		T5	307		T6	132
valid_sources[0x76]	82120	1			T1	1		T5	250		T6	156
valid_sources[0x77]	86049	1			T1	4		T4	331		T5	296
valid_sources[0x78]	88175	1			T1	3		T5	242		T6	160
valid_sources[0x79]	93189	1			T1	3		T5	206		T6	130
valid_sources[0x7a]	92058	1			T1	4		T5	229		T6	100
valid_sources[0x7b]	83553	1			T1	2		T5	261		T6	126
valid_sources[0x7c]	93214	1			T1	3		T5	305		T6	117
valid_sources[0x7d]	86514	1			T1	1		T5	282		T6	146
valid_sources[0x7e]	84130	1			T1	1		T5	230		T6	127
valid_sources[0x7f]	105050	1			T1	1		T5	285		T6	138
valid_sources[0x80]	83415	1			T1	3		T5	266		T6	141

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5374362

1

T1

21

T3

1

T4

816

values[0x0]

all_enables

biggest_size

5053841

1

T1

153

T2

1

T3

2

values[0x1]

all_enables

biggest_size

4572235

1

T1

164

T2

1

T3

1