Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14610057

1

T1

79

T2

10

T3

20

full_word

15086154

1

T1

338

T2

2

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29695831	1			T1	417		T2	12		T3	24
auto[TlIntgErrCmd]	132	1			T26	3		T58	4		T59	7
auto[TlIntgErrData]	125	1			T26	3		T58	5		T59	4
auto[TlIntgErrBoth]	123	1			T26	4		T58	1		T59	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11362686

1

T1

68

T2

1

T3

1

auto[1]

18333525

1

T1

349

T2

11

T3

23

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5954722	1			T1	47		T2	1		T4	949
auto[TlIntgErrNone]	partial	auto[1]	8654994	1			T1	32		T2	9		T3	20
auto[TlIntgErrNone]	full_word	auto[0]	5407796	1			T1	21		T3	1		T4	816
auto[TlIntgErrNone]	full_word	auto[1]	9678319	1			T1	317		T2	2		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T58	1		T59	4		T68	1
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T26	3		T58	2		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T122	1		T121	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T58	1		T69	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T26	1		T58	2		T59	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T26	2		T58	2		T59	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T58	1		T120	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T96	1		T126	2		T121	4
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T26	2		T58	1		T59	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T26	2		T59	7		T68	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T68	1		T69	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T59	1		T69	1		T96	2