Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	179505300	756664	0	0
intr_enable_rd_A	179505300	3077	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179505300	756664	0	0
T20	532082	15421	0	0
T25	0	468	0	0
T26	0	1	0	0
T57	0	15	0	0
T58	0	2	0	0
T59	0	4	0	0
T60	0	20	0	0
T61	0	308	0	0
T68	0	7	0	0
T69	0	5	0	0
T70	879	0	0	0
T71	3855	0	0	0
T72	1117	0	0	0
T73	839068	0	0	0
T74	49386	0	0	0
T75	757	0	0	0
T76	401627	0	0	0
T77	151838	0	0	0
T78	9990	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179505300	3077	0	0
T26	0	92	0	0
T63	155968	30	0	0
T79	0	41	0	0
T80	0	13	0	0
T81	0	21	0	0
T82	0	35	0	0
T83	0	81	0	0
T84	0	17	0	0
T85	0	36	0	0
T86	0	393	0	0
T87	66662	0	0	0
T88	68640	0	0	0
T89	1274	0	0	0
T90	56377	0	0	0
T91	43378	0	0	0
T92	106279	0	0	0
T93	720	0	0	0
T94	864758	0	0	0
T95	383218	0	0	0