Line Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 13 | 86.67 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 24 | 8 | 33.33 |
Logical | 24 | 8 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 24 | 20 | 83.33 |
Logical | 24 | 20 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T12,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T12,T18 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T6,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1693113004 |
190148412 |
0 |
0 |
T1 |
26628 |
1987 |
0 |
0 |
T2 |
8218 |
76 |
0 |
0 |
T3 |
8127 |
230 |
0 |
0 |
T4 |
800288 |
296937 |
0 |
0 |
T5 |
4309608 |
356589 |
0 |
0 |
T6 |
614536 |
174762 |
0 |
0 |
T7 |
307032 |
36827 |
0 |
0 |
T8 |
0 |
357584 |
0 |
0 |
T12 |
61098 |
104750 |
0 |
0 |
T13 |
147488 |
75924 |
0 |
0 |
T18 |
0 |
160250 |
0 |
0 |
T19 |
6704 |
98 |
0 |
0 |
T22 |
0 |
845 |
0 |
0 |
T33 |
11104 |
20 |
0 |
0 |
T34 |
8664 |
68 |
0 |
0 |
T47 |
0 |
15207 |
0 |
0 |
T48 |
674 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1693113004 |
1692420172 |
0 |
0 |
T1 |
38040 |
37080 |
0 |
0 |
T2 |
11740 |
11200 |
0 |
0 |
T3 |
11610 |
10820 |
0 |
0 |
T4 |
1000360 |
999550 |
0 |
0 |
T5 |
5387010 |
5385490 |
0 |
0 |
T6 |
768170 |
767600 |
0 |
0 |
T7 |
383790 |
383210 |
0 |
0 |
T19 |
8380 |
7630 |
0 |
0 |
T33 |
13880 |
12880 |
0 |
0 |
T34 |
10830 |
9890 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1693113004 |
1692420172 |
0 |
0 |
T1 |
38040 |
37080 |
0 |
0 |
T2 |
11740 |
11200 |
0 |
0 |
T3 |
11610 |
10820 |
0 |
0 |
T4 |
1000360 |
999550 |
0 |
0 |
T5 |
5387010 |
5385490 |
0 |
0 |
T6 |
768170 |
767600 |
0 |
0 |
T7 |
383790 |
383210 |
0 |
0 |
T19 |
8380 |
7630 |
0 |
0 |
T33 |
13880 |
12880 |
0 |
0 |
T34 |
10830 |
9890 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1693113004 |
1692420172 |
0 |
0 |
T1 |
38040 |
37080 |
0 |
0 |
T2 |
11740 |
11200 |
0 |
0 |
T3 |
11610 |
10820 |
0 |
0 |
T4 |
1000360 |
999550 |
0 |
0 |
T5 |
5387010 |
5385490 |
0 |
0 |
T6 |
768170 |
767600 |
0 |
0 |
T7 |
383790 |
383210 |
0 |
0 |
T19 |
8380 |
7630 |
0 |
0 |
T33 |
13880 |
12880 |
0 |
0 |
T34 |
10830 |
9890 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
616081204 |
25802631 |
0 |
0 |
T1 |
3804 |
297 |
0 |
0 |
T2 |
1174 |
0 |
0 |
0 |
T3 |
1161 |
0 |
0 |
0 |
T4 |
200072 |
88465 |
0 |
0 |
T5 |
1077402 |
50635 |
0 |
0 |
T6 |
153634 |
22860 |
0 |
0 |
T7 |
76758 |
2473 |
0 |
0 |
T8 |
0 |
209416 |
0 |
0 |
T12 |
61098 |
47112 |
0 |
0 |
T13 |
147488 |
46141 |
0 |
0 |
T18 |
0 |
74579 |
0 |
0 |
T19 |
1676 |
0 |
0 |
0 |
T22 |
0 |
741 |
0 |
0 |
T33 |
2776 |
0 |
0 |
0 |
T34 |
2166 |
0 |
0 |
0 |
T47 |
0 |
15207 |
0 |
0 |
T48 |
674 |
0 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3528 |
3528 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
6 |
6 |
0 |
0 |
T19 |
6 |
6 |
0 |
0 |
T33 |
6 |
6 |
0 |
0 |
T34 |
6 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 13 | 92.86 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests | Exclude Annotation |
0 | Covered | T1,T2,T3 |
1 | Excluded | |
VC_COV_UNR |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | |
VC_COV_UNR |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
130 |
1 |
1 |
100.00 |
TERNARY |
138 |
1 |
1 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete | Exclusion | Exclude Annotation |
DataKnown_A |
|
|
|
|
Excluded |
[UNSUPPORTED] excluded by fpv |
DepthKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
RvalidKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
WreadyKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
gen_normal_fifo.depthShallNotExceedParamDepth |
|
|
|
|
Excluded |
[UNSUPPORTED] excluded by fpv |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 13 | 12 | 92.31 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 0 | 0 | |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
|
excluded |
|
|
|
Exclude Annotation: [UNR] Pass is always '1' |
111 |
1 |
1 |
112 |
|
excluded |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 6 | 5 | 83.33 |
Logical | 6 | 5 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | |
VC_COV_UNR |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
138 |
1 |
1 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Covered |
T1,T2,T3 |
|
0 |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests | Exclude Annotation |
1 |
Excluded |
|
VC_COV_UNR |
0 |
Covered |
T1,T2,T3 |
|
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete | Exclusion | Exclude Annotation |
DataKnown_A |
|
|
|
|
Excluded |
[UNSUPPORTED] excluded by fpv |
DepthKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
RvalidKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
WreadyKnown_A |
154020301 |
153977224 |
0 |
0 |
|
|
gen_normal_fifo.depthShallNotExceedParamDepth |
|
|
|
|
Excluded |
[UNSUPPORTED] excluded by fpv |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_msg_fifo
| Total | Covered | Percent |
Conditions | 20 | 20 | 100.00 |
Logical | 20 | 20 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T12,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T5,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T12,T18 |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msg_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msg_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
13379389 |
0 |
0 |
T4 |
100036 |
60042 |
0 |
0 |
T5 |
538701 |
21706 |
0 |
0 |
T6 |
76817 |
9316 |
0 |
0 |
T7 |
38379 |
947 |
0 |
0 |
T8 |
0 |
135332 |
0 |
0 |
T12 |
61098 |
28207 |
0 |
0 |
T13 |
147488 |
31527 |
0 |
0 |
T18 |
0 |
46602 |
0 |
0 |
T19 |
838 |
0 |
0 |
0 |
T22 |
0 |
689 |
0 |
0 |
T33 |
1388 |
0 |
0 |
0 |
T34 |
1083 |
0 |
0 |
0 |
T47 |
0 |
15207 |
0 |
0 |
T48 |
674 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
13379389 |
0 |
0 |
T4 |
100036 |
60042 |
0 |
0 |
T5 |
538701 |
21706 |
0 |
0 |
T6 |
76817 |
9316 |
0 |
0 |
T7 |
38379 |
947 |
0 |
0 |
T8 |
0 |
135332 |
0 |
0 |
T12 |
61098 |
28207 |
0 |
0 |
T13 |
147488 |
31527 |
0 |
0 |
T18 |
0 |
46602 |
0 |
0 |
T19 |
838 |
0 |
0 |
0 |
T22 |
0 |
689 |
0 |
0 |
T33 |
1388 |
0 |
0 |
0 |
T34 |
1083 |
0 |
0 |
0 |
T47 |
0 |
15207 |
0 |
0 |
T48 |
674 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | Covered | T5,T6,T7 |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
12423242 |
0 |
0 |
T1 |
3804 |
297 |
0 |
0 |
T2 |
1174 |
0 |
0 |
0 |
T3 |
1161 |
0 |
0 |
0 |
T4 |
100036 |
28423 |
0 |
0 |
T5 |
538701 |
28929 |
0 |
0 |
T6 |
76817 |
13544 |
0 |
0 |
T7 |
38379 |
1526 |
0 |
0 |
T8 |
0 |
74084 |
0 |
0 |
T12 |
0 |
18905 |
0 |
0 |
T13 |
0 |
14614 |
0 |
0 |
T18 |
0 |
27977 |
0 |
0 |
T19 |
838 |
0 |
0 |
0 |
T22 |
0 |
52 |
0 |
0 |
T33 |
1388 |
0 |
0 |
0 |
T34 |
1083 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
153977224 |
0 |
0 |
T1 |
3804 |
3708 |
0 |
0 |
T2 |
1174 |
1120 |
0 |
0 |
T3 |
1161 |
1082 |
0 |
0 |
T4 |
100036 |
99955 |
0 |
0 |
T5 |
538701 |
538549 |
0 |
0 |
T6 |
76817 |
76760 |
0 |
0 |
T7 |
38379 |
38321 |
0 |
0 |
T19 |
838 |
763 |
0 |
0 |
T33 |
1388 |
1288 |
0 |
0 |
T34 |
1083 |
989 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154020301 |
12423242 |
0 |
0 |
T1 |
3804 |
297 |
0 |
0 |
T2 |
1174 |
0 |
0 |
0 |
T3 |
1161 |
0 |
0 |
0 |
T4 |
100036 |
28423 |
0 |
0 |
T5 |
538701 |
28929 |
0 |
0 |
T6 |
76817 |
13544 |
0 |
0 |
T7 |
38379 |
1526 |
0 |
0 |
T8 |
0 |
74084 |
0 |
0 |
T12 |
0 |
18905 |
0 |
0 |
T13 |
0 |
14614 |
0 |
0 |
T18 |
0 |
27977 |
0 |
0 |
T19 |
838 |
0 |
0 |
0 |
T22 |
0 |
52 |
0 |
0 |
T33 |
1388 |
0 |
0 |
0 |
T34 |
1083 |
0 |
0 |
0 |