Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 16102292 1 T1 6263 T2 5496 T3 39236
full_word 16495362 1 T1 23953 T2 17232 T3 33087



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32597294 1 T1 30216 T2 22728 T3 72323
auto[TlIntgErrCmd] 114 1 T56 2 T57 3 T58 5
auto[TlIntgErrData] 134 1 T56 5 T57 4 T58 2
auto[TlIntgErrBoth] 112 1 T56 3 T57 3 T58 3



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12863709 1 T1 7965 T2 6746 T3 29261
auto[1] 19733945 1 T1 22251 T2 15982 T3 43062



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 6620423 1 T1 4718 T2 4070 T3 14723
auto[TlIntgErrNone] partial auto[1] 9481542 1 T1 1545 T2 1426 T3 24513
auto[TlIntgErrNone] full_word auto[0] 6243129 1 T1 3247 T2 2676 T3 14538
auto[TlIntgErrNone] full_word auto[1] 10252200 1 T1 20706 T2 14556 T3 18549
auto[TlIntgErrCmd] partial auto[0] 44 1 T57 1 T58 2 T123 3
auto[TlIntgErrCmd] partial auto[1] 62 1 T56 2 T57 1 T58 3
auto[TlIntgErrCmd] full_word auto[0] 5 1 T123 1 T124 2 T127 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T57 1 T128 1 T129 1
auto[TlIntgErrData] partial auto[0] 55 1 T56 3 T57 1 T58 1
auto[TlIntgErrData] partial auto[1] 66 1 T56 2 T57 3 T58 1
auto[TlIntgErrData] full_word auto[0] 8 1 T130 1 T126 1 T127 2
auto[TlIntgErrData] full_word auto[1] 5 1 T131 1 T127 1 T132 3
auto[TlIntgErrBoth] partial auto[0] 38 1 T57 1 T58 1 T123 1
auto[TlIntgErrBoth] partial auto[1] 62 1 T56 3 T57 1 T58 2
auto[TlIntgErrBoth] full_word auto[0] 7 1 T123 1 T124 1 T125 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T57 1 T128 2 T132 1

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