Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	167515868	307002	0	0
intr_enable_rd_A	167515868	2269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167515868	307002	0	0
T11	142222	40759	0	0
T12	0	69216	0	0
T28	0	8783	0	0
T56	0	3	0	0
T57	0	2	0	0
T64	0	34	0	0
T65	0	553	0	0
T66	0	6	0	0
T67	0	406	0	0
T68	0	997	0	0
T69	16175	0	0	0
T70	372219	0	0	0
T71	373075	0	0	0
T72	420038	0	0	0
T73	5360	0	0	0
T74	1080	0	0	0
T75	381362	0	0	0
T76	266730	0	0	0
T77	421686	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167515868	2269	0	0
T25	207955	22	0	0
T47	50763	0	0	0
T48	42916	0	0	0
T63	0	67	0	0
T66	0	14	0	0
T78	0	6	0	0
T79	0	20	0	0
T80	0	8	0	0
T81	0	4	0	0
T82	0	31	0	0
T83	0	7	0	0
T84	0	23	0	0
T85	982	0	0	0
T86	2692	0	0	0
T87	1300	0	0	0
T88	439014	0	0	0
T89	707442	0	0	0
T90	29005	0	0	0
T91	5379	0	0	0