Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.43 97.10 75.22 80.77 84.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter 94.93 98.53 96.59 100.00 84.62



Module Instance : tb.dut.u_tlul_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.93 98.53 96.59 100.00 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.74 94.06 88.04 80.25 92.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.91 95.81 83.54 100.00 40.00 90.11 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 91.36 95.00 87.10 83.33 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 79.31 87.18 68.97 61.11 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 78.68 86.84 65.38 62.50 100.00

Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL696797.10
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS2318787.50
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN426100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43500
ALWAYS45333100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 0 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
401 1 1
402 1 1
403 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 0 1
428 1 1
435 unreachable
453 1 1
454 1 1
455 1 1
459 1 1
462 1 1
467 1 1
472 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1138575.22
Logical1138575.22
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000CoveredT11,T12,T28
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT11,T12,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T19
11CoveredT1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01CoveredT11,T12,T28
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT11,T12,T28
1110Not Covered
1111Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT11,T12,T28
10Not Covered
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT11,T12,T28
111CoveredT11,T12,T28

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT11,T12,T28

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T28
10CoveredT1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT11,T12,T28
111CoveredT1,T2,T3

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       403
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11Not Covered

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 21 80.77
TERNARY 108 2 2 100.00
TERNARY 293 2 1 50.00
TERNARY 299 3 1 33.33
TERNARY 344 2 2 100.00
TERNARY 467 2 1 50.00
IF 94 2 2 100.00
IF 233 4 3 75.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T11,T12,T28
1 0 1 Not Covered
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T11,T12,T28
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 162411536 162370586 0 0
DataIntgOptions_A 436 436 0 0
ReqOutKnown_A 162411536 162370586 0 0
SramDwHasByteGranularity_A 436 436 0 0
SramDwIsMultipleOfTlulWidth_A 436 436 0 0
TlOutKnownIfFifoKnown_A 162411536 162370586 0 0
TlOutValidKnown_A 162411536 162370586 0 0
WdataOutKnown_A 162411536 162370586 0 0
WeOutKnown_A 162411536 162370586 0 0
WmaskOutKnown_A 162411536 162370586 0 0
adapterNoReadOrWrite 436 436 0 0
rvalidHighReqFifoEmpty 162411536 0 0 0
rvalidHighWhenRspFifoFull 162411536 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 0 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter
Line No.TotalCoveredPercent
TOTAL686798.53
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23177100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN426100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43500
ALWAYS45333100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 excluded
Exclude Annotation: VC_COV_UNR
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
401 1 1
402 1 1
403 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 0 1
428 1 1
435 unreachable
453 1 1
454 1 1
455 1 1
459 1 1
462 1 1
467 1 1
472 unreachable


Cond Coverage for Instance : tb.dut.u_tlul_adapter
TotalCoveredPercent
Conditions888596.59
Logical888596.59
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001Excluded VC_COV_UNR
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTestsExclude Annotation
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Excluded VC_COV_UNR
001000CoveredT11,T12,T28
010000Unreachable
100000Excluded VC_COV_UNR

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT11,T12,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T8,T19
11CoveredT1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT11,T12,T28
10Excluded VC_COV_UNR

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Excluded VC_COV_UNR
1101CoveredT11,T12,T28
1110Excluded VC_COV_UNR
1111Excluded VC_COV_UNR

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT11,T12,T28
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT11,T12,T28
111CoveredT11,T12,T28

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT11,T12,T28

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T28
10CoveredT1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110CoveredT11,T12,T28
111CoveredT1,T2,T3

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11CoveredT1,T2,T3

 LINE       403
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10CoveredT11,T12,T28
11Excluded VC_COV_UNR

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T12,T28

Branch Coverage for Instance : tb.dut.u_tlul_adapter
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 108 2 2 100.00
TERNARY 293 1 1 100.00
TERNARY 299 1 1 100.00
TERNARY 344 2 2 100.00
TERNARY 467 1 1 100.00
IF 94 2 2 100.00
IF 233 3 3 100.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Excluded VC_COV_UNR
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTestsExclude Annotation
1 1 - Covered T11,T12,T28
1 0 1 Excluded VC_COV_UNR
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T11,T12,T28
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 162411536 162370586 0 0
DataIntgOptions_A 436 436 0 0
ReqOutKnown_A 162411536 162370586 0 0
SramDwHasByteGranularity_A 436 436 0 0
SramDwIsMultipleOfTlulWidth_A 436 436 0 0
TlOutKnownIfFifoKnown_A 162411536 162370586 0 0
TlOutValidKnown_A 162411536 162370586 0 0
WdataOutKnown_A 162411536 162370586 0 0
WeOutKnown_A 162411536 162370586 0 0
WmaskOutKnown_A 162411536 162370586 0 0
adapterNoReadOrWrite 436 436 0 0
rvalidHighReqFifoEmpty 162411536 0 0 0
rvalidHighWhenRspFifoFull 162411536 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 162370586 0 0
T1 303566 303506 0 0
T2 159104 159034 0 0
T3 753512 753434 0 0
T4 408422 408364 0 0
T5 36714 36645 0 0
T6 709068 708972 0 0
T8 48553 48460 0 0
T9 424341 424242 0 0
T13 26126 26030 0 0
T33 2375 2290 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T33 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 162411536 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%